Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8189688 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6006301 |
1 |
|
|
T29 |
226 |
|
T41 |
49 |
|
T42 |
484 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11747544 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
2448445 |
1 |
|
|
T29 |
148 |
|
T41 |
33 |
|
T42 |
83 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8194594 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6001395 |
1 |
|
|
T29 |
251 |
|
T41 |
73 |
|
T42 |
444 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1801104 |
1 |
|
|
T29 |
35 |
|
T41 |
37 |
|
T42 |
193 |
| auto[1] |
auto[0] |
auto[1] |
1239612 |
1 |
|
|
T29 |
65 |
|
T41 |
18 |
|
T42 |
44 |
| auto[1] |
auto[1] |
auto[0] |
1751846 |
1 |
|
|
T29 |
68 |
|
T41 |
3 |
|
T42 |
168 |
| auto[1] |
auto[1] |
auto[1] |
1208833 |
1 |
|
|
T29 |
83 |
|
T41 |
15 |
|
T42 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |