Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187759 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6008230 |
1 |
|
|
T29 |
166 |
|
T41 |
96 |
|
T42 |
587 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13436297 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
759692 |
1 |
|
|
T29 |
18 |
|
T41 |
3 |
|
T42 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210890 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
5985099 |
1 |
|
|
T29 |
237 |
|
T41 |
62 |
|
T42 |
514 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2629608 |
1 |
|
|
T29 |
114 |
|
T41 |
18 |
|
T42 |
195 |
| auto[1] |
auto[0] |
auto[1] |
382874 |
1 |
|
|
T29 |
9 |
|
T41 |
2 |
|
T42 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2595799 |
1 |
|
|
T29 |
105 |
|
T41 |
41 |
|
T42 |
302 |
| auto[1] |
auto[1] |
auto[1] |
376818 |
1 |
|
|
T29 |
9 |
|
T41 |
1 |
|
T42 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |