Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8122933 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6073056 |
1 |
|
|
T29 |
208 |
|
T41 |
116 |
|
T42 |
524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13425914 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
770075 |
1 |
|
|
T29 |
17 |
|
T41 |
4 |
|
T42 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8151742 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6044247 |
1 |
|
|
T29 |
225 |
|
T41 |
90 |
|
T42 |
417 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627113 |
1 |
|
|
T29 |
92 |
|
T41 |
26 |
|
T42 |
162 |
| auto[1] |
auto[0] |
auto[1] |
383705 |
1 |
|
|
T29 |
6 |
|
T42 |
5 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2647059 |
1 |
|
|
T29 |
116 |
|
T41 |
60 |
|
T42 |
241 |
| auto[1] |
auto[1] |
auto[1] |
386370 |
1 |
|
|
T29 |
11 |
|
T41 |
4 |
|
T42 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |