Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T766 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.491094948 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:00 PM PDT 24 34497407 ps
T767 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1541740566 Apr 28 12:22:15 PM PDT 24 Apr 28 12:22:19 PM PDT 24 23525915 ps
T768 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.159406287 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 128002340 ps
T769 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3943360460 Apr 28 12:21:44 PM PDT 24 Apr 28 12:21:45 PM PDT 24 13819864 ps
T770 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4026218943 Apr 28 12:18:00 PM PDT 24 Apr 28 12:18:01 PM PDT 24 44376041 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3243895690 Apr 28 12:22:11 PM PDT 24 Apr 28 12:22:15 PM PDT 24 54030164 ps
T772 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3135602983 Apr 28 12:23:12 PM PDT 24 Apr 28 12:23:15 PM PDT 24 13411950 ps
T773 /workspace/coverage/cover_reg_top/33.gpio_intr_test.106384308 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:42 PM PDT 24 14882651 ps
T774 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2544758202 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:07 PM PDT 24 170153045 ps
T87 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2823246284 Apr 28 12:22:46 PM PDT 24 Apr 28 12:22:57 PM PDT 24 11390064 ps
T775 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3865351375 Apr 28 12:23:32 PM PDT 24 Apr 28 12:23:33 PM PDT 24 25601711 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.355302338 Apr 28 12:18:52 PM PDT 24 Apr 28 12:18:55 PM PDT 24 674073952 ps
T88 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1997800297 Apr 28 12:23:02 PM PDT 24 Apr 28 12:23:10 PM PDT 24 115220338 ps
T777 /workspace/coverage/cover_reg_top/39.gpio_intr_test.4272208077 Apr 28 12:22:37 PM PDT 24 Apr 28 12:22:43 PM PDT 24 12009853 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2886238238 Apr 28 12:18:27 PM PDT 24 Apr 28 12:18:28 PM PDT 24 27695566 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2844546012 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:18 PM PDT 24 15952989 ps
T780 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1114486006 Apr 28 12:18:33 PM PDT 24 Apr 28 12:18:36 PM PDT 24 193891856 ps
T781 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3442247603 Apr 28 12:18:46 PM PDT 24 Apr 28 12:18:47 PM PDT 24 16800810 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.476818244 Apr 28 12:21:58 PM PDT 24 Apr 28 12:22:02 PM PDT 24 156610696 ps
T783 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2457049195 Apr 28 12:20:37 PM PDT 24 Apr 28 12:20:41 PM PDT 24 941986805 ps
T784 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2410325181 Apr 28 12:22:32 PM PDT 24 Apr 28 12:22:34 PM PDT 24 44376202 ps
T47 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1364338416 Apr 28 12:21:11 PM PDT 24 Apr 28 12:21:13 PM PDT 24 125321581 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4052941535 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 76331865 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.476460690 Apr 28 12:19:08 PM PDT 24 Apr 28 12:19:10 PM PDT 24 45835917 ps
T787 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.694972494 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:01 PM PDT 24 18065819 ps
T89 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2046546572 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 96582309 ps
T788 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4035379517 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:58 PM PDT 24 18327046 ps
T789 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2343625033 Apr 28 12:21:53 PM PDT 24 Apr 28 12:21:58 PM PDT 24 45730532 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1800551095 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:11 PM PDT 24 13533520 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2505533877 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:15 PM PDT 24 29654205 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2990400700 Apr 28 12:22:46 PM PDT 24 Apr 28 12:22:56 PM PDT 24 143828822 ps
T793 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1918137284 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:18 PM PDT 24 40546697 ps
T794 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1428905033 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:18 PM PDT 24 20760875 ps
T795 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1493431159 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:00 PM PDT 24 45455737 ps
T796 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3023677821 Apr 28 12:19:21 PM PDT 24 Apr 28 12:19:22 PM PDT 24 49541331 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3619838458 Apr 28 12:21:54 PM PDT 24 Apr 28 12:21:59 PM PDT 24 55020792 ps
T798 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3545447345 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:06 PM PDT 24 110504291 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2642282627 Apr 28 12:22:46 PM PDT 24 Apr 28 12:22:55 PM PDT 24 11184584 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3811092999 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 48902570 ps
T801 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.55544152 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:13 PM PDT 24 128195702 ps
T48 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2527472087 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:18 PM PDT 24 167945919 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.197340932 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 16315470 ps
T803 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2728866547 Apr 28 12:22:55 PM PDT 24 Apr 28 12:23:06 PM PDT 24 14819462 ps
T804 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4176222364 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:13 PM PDT 24 43217682 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3245026636 Apr 28 12:18:51 PM PDT 24 Apr 28 12:18:55 PM PDT 24 167228305 ps
T806 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.277111764 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:41 PM PDT 24 81967161 ps
T807 /workspace/coverage/cover_reg_top/28.gpio_intr_test.207869833 Apr 28 12:21:14 PM PDT 24 Apr 28 12:21:15 PM PDT 24 62917743 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4070634994 Apr 28 12:18:47 PM PDT 24 Apr 28 12:18:48 PM PDT 24 116310658 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2226110122 Apr 28 12:22:29 PM PDT 24 Apr 28 12:22:30 PM PDT 24 252054136 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4142515783 Apr 28 12:21:54 PM PDT 24 Apr 28 12:21:59 PM PDT 24 13761519 ps
T90 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4209543710 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:15 PM PDT 24 29489862 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.599263428 Apr 28 12:18:41 PM PDT 24 Apr 28 12:18:42 PM PDT 24 169368116 ps
T49 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2917043133 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:17 PM PDT 24 86211970 ps
T812 /workspace/coverage/cover_reg_top/48.gpio_intr_test.419601399 Apr 28 12:19:38 PM PDT 24 Apr 28 12:19:39 PM PDT 24 25382039 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2181267145 Apr 28 12:23:07 PM PDT 24 Apr 28 12:23:13 PM PDT 24 38978000 ps
T814 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2409517902 Apr 28 12:20:28 PM PDT 24 Apr 28 12:20:29 PM PDT 24 13330482 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1378050130 Apr 28 12:22:37 PM PDT 24 Apr 28 12:22:43 PM PDT 24 102069476 ps
T816 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1423148104 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:38 PM PDT 24 326209903 ps
T817 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2441051808 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:19 PM PDT 24 611028023 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.997877498 Apr 28 12:22:03 PM PDT 24 Apr 28 12:22:06 PM PDT 24 35210528 ps
T819 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1844854192 Apr 28 12:18:25 PM PDT 24 Apr 28 12:18:26 PM PDT 24 34907019 ps
T820 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3883650773 Apr 28 12:18:57 PM PDT 24 Apr 28 12:18:59 PM PDT 24 92069775 ps
T821 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1327645282 Apr 28 12:20:43 PM PDT 24 Apr 28 12:20:44 PM PDT 24 14473427 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1054779130 Apr 28 12:19:50 PM PDT 24 Apr 28 12:19:52 PM PDT 24 26313223 ps
T107 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1181230207 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:16 PM PDT 24 78470819 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4161707685 Apr 28 12:20:12 PM PDT 24 Apr 28 12:20:13 PM PDT 24 38590231 ps
T823 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.853735538 Apr 28 12:18:00 PM PDT 24 Apr 28 12:18:02 PM PDT 24 387936432 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1840113926 Apr 28 12:22:15 PM PDT 24 Apr 28 12:22:18 PM PDT 24 13595476 ps
T825 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3793694293 Apr 28 12:21:54 PM PDT 24 Apr 28 12:21:58 PM PDT 24 58407062 ps
T826 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3230029026 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:24 PM PDT 24 242106371 ps
T827 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3981945823 Apr 28 12:21:52 PM PDT 24 Apr 28 12:21:57 PM PDT 24 59627805 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2662472553 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 53874655 ps
T92 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3963714993 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 14641032 ps
T829 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1035678197 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:16 PM PDT 24 46062504 ps
T93 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.963447883 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:08 PM PDT 24 25808519 ps
T94 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3259331899 Apr 28 12:19:01 PM PDT 24 Apr 28 12:19:03 PM PDT 24 59786964 ps
T830 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1924637530 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:42 PM PDT 24 139052685 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2301840108 Apr 28 12:19:51 PM PDT 24 Apr 28 12:19:53 PM PDT 24 44762164 ps
T832 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4188411925 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 120012387 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1310113773 Apr 28 12:19:15 PM PDT 24 Apr 28 12:19:16 PM PDT 24 42825314 ps
T834 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1658645430 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:15 PM PDT 24 138058205 ps
T835 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1875051317 Apr 28 12:21:58 PM PDT 24 Apr 28 12:22:02 PM PDT 24 483258798 ps
T836 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1444526630 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:58 PM PDT 24 29224053 ps
T837 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1982259332 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:04 PM PDT 24 37151528 ps
T838 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.91351456 Apr 28 12:18:09 PM PDT 24 Apr 28 12:18:10 PM PDT 24 81464228 ps
T839 /workspace/coverage/cover_reg_top/32.gpio_intr_test.4237475233 Apr 28 12:21:27 PM PDT 24 Apr 28 12:21:28 PM PDT 24 25539960 ps
T95 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2558286306 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 26626265 ps
T840 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2987412810 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 12754850 ps
T841 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3147512732 Apr 28 12:22:27 PM PDT 24 Apr 28 12:22:28 PM PDT 24 27742672 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.761312483 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 31118158 ps
T842 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4294275871 Apr 28 12:22:08 PM PDT 24 Apr 28 12:22:11 PM PDT 24 19431773 ps
T843 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.808259340 Apr 28 12:18:50 PM PDT 24 Apr 28 12:18:51 PM PDT 24 225658373 ps
T97 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3962418840 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:10 PM PDT 24 46423773 ps
T844 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2271551688 Apr 28 12:18:57 PM PDT 24 Apr 28 12:18:58 PM PDT 24 19405044 ps
T845 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1843519255 Apr 28 12:22:08 PM PDT 24 Apr 28 12:22:11 PM PDT 24 47780492 ps
T846 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2618054728 Apr 28 12:18:51 PM PDT 24 Apr 28 12:18:53 PM PDT 24 60429553 ps
T847 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.291150441 Apr 28 12:18:42 PM PDT 24 Apr 28 12:18:43 PM PDT 24 161666672 ps
T848 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572661844 Apr 28 12:21:54 PM PDT 24 Apr 28 12:21:58 PM PDT 24 29529411 ps
T849 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3727061040 Apr 28 12:18:06 PM PDT 24 Apr 28 12:18:07 PM PDT 24 145017669 ps
T850 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3769951145 Apr 28 12:22:41 PM PDT 24 Apr 28 12:22:48 PM PDT 24 95780180 ps
T851 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2413959916 Apr 28 12:22:41 PM PDT 24 Apr 28 12:22:49 PM PDT 24 52688341 ps
T852 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.882284317 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:15 PM PDT 24 403932007 ps
T853 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2126600236 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 262268563 ps
T854 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.517449384 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:00 PM PDT 24 72096008 ps
T855 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2553487560 Apr 28 12:22:59 PM PDT 24 Apr 28 12:23:09 PM PDT 24 51323443 ps
T856 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1415621198 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:23 PM PDT 24 45074250 ps
T857 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.892294234 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:37 PM PDT 24 64217528 ps
T858 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3415164553 Apr 28 12:17:58 PM PDT 24 Apr 28 12:17:59 PM PDT 24 38321402 ps
T859 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3367777697 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:37 PM PDT 24 81754297 ps
T860 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2338093063 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:17 PM PDT 24 48965673 ps
T861 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3974094115 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:11 PM PDT 24 74635557 ps
T862 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3498528345 Apr 28 12:22:17 PM PDT 24 Apr 28 12:22:20 PM PDT 24 139747265 ps
T863 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3602352257 Apr 28 12:22:43 PM PDT 24 Apr 28 12:22:51 PM PDT 24 44571547 ps
T864 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3264560148 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:08 PM PDT 24 44033060 ps
T865 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.717224757 Apr 28 12:22:54 PM PDT 24 Apr 28 12:23:06 PM PDT 24 158654543 ps
T866 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1386494831 Apr 28 12:20:03 PM PDT 24 Apr 28 12:20:05 PM PDT 24 53219901 ps
T867 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3643612556 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:11 PM PDT 24 73064717 ps
T868 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3124746347 Apr 28 12:17:46 PM PDT 24 Apr 28 12:17:47 PM PDT 24 170726241 ps
T869 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2862480335 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:44 PM PDT 24 55406585 ps
T870 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1782754960 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:44 PM PDT 24 97370871 ps
T871 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4284563509 Apr 28 12:23:01 PM PDT 24 Apr 28 12:23:11 PM PDT 24 67517105 ps
T872 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3698608056 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 310802978 ps
T873 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.186091692 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:17 PM PDT 24 56179216 ps
T874 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2453720879 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:49 PM PDT 24 853122640 ps
T875 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1661063613 Apr 28 12:18:09 PM PDT 24 Apr 28 12:18:11 PM PDT 24 72560252 ps
T876 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.655690786 Apr 28 12:23:03 PM PDT 24 Apr 28 12:23:10 PM PDT 24 27410471 ps
T877 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.442035537 Apr 28 12:19:35 PM PDT 24 Apr 28 12:19:36 PM PDT 24 62515517 ps
T878 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2061982699 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:08 PM PDT 24 240814623 ps
T879 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1759113197 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 54381374 ps
T880 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3695506304 Apr 28 12:18:08 PM PDT 24 Apr 28 12:18:10 PM PDT 24 85855563 ps
T881 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3938239543 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:16 PM PDT 24 253542138 ps
T882 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1242436033 Apr 28 12:22:00 PM PDT 24 Apr 28 12:22:04 PM PDT 24 130488388 ps
T883 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376936415 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:09 PM PDT 24 628279003 ps
T884 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.41797701 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:17 PM PDT 24 86543251 ps
T885 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3078793544 Apr 28 12:18:42 PM PDT 24 Apr 28 12:18:44 PM PDT 24 79476761 ps
T886 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2605007974 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:38 PM PDT 24 51276440 ps
T887 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2162049935 Apr 28 12:21:53 PM PDT 24 Apr 28 12:22:00 PM PDT 24 321239439 ps
T888 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1258410973 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:16 PM PDT 24 120992619 ps
T889 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2245096820 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:13 PM PDT 24 165927561 ps
T890 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585065756 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:49 PM PDT 24 51015575 ps
T891 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3945812813 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:45 PM PDT 24 43497878 ps
T892 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.839279868 Apr 28 12:22:17 PM PDT 24 Apr 28 12:22:21 PM PDT 24 46775506 ps
T893 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3064449996 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 28967484 ps
T894 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2628157451 Apr 28 12:21:09 PM PDT 24 Apr 28 12:21:11 PM PDT 24 110060186 ps
T895 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.808156749 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:02 PM PDT 24 65083923 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.41898553 Apr 28 12:19:43 PM PDT 24 Apr 28 12:19:45 PM PDT 24 249982589 ps
T897 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1448188076 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:08 PM PDT 24 50419857 ps
T898 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3117666776 Apr 28 12:21:57 PM PDT 24 Apr 28 12:22:01 PM PDT 24 19059101 ps
T899 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.107632154 Apr 28 12:21:52 PM PDT 24 Apr 28 12:21:56 PM PDT 24 31075938 ps
T900 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2815697295 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 240050828 ps
T901 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486328459 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:41 PM PDT 24 105544795 ps
T902 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3197271163 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:49 PM PDT 24 205482168 ps
T903 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3863732710 Apr 28 12:17:40 PM PDT 24 Apr 28 12:17:41 PM PDT 24 118885732 ps
T904 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.935373594 Apr 28 12:21:57 PM PDT 24 Apr 28 12:22:02 PM PDT 24 74308612 ps
T905 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195353727 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:18 PM PDT 24 137151090 ps
T906 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3863682687 Apr 28 12:22:56 PM PDT 24 Apr 28 12:23:08 PM PDT 24 43343744 ps
T907 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.622606449 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:02 PM PDT 24 203049242 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.183017289 Apr 28 12:18:08 PM PDT 24 Apr 28 12:18:09 PM PDT 24 213772363 ps
T909 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3283648494 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:45 PM PDT 24 94047703 ps
T910 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2506400731 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:17 PM PDT 24 81749455 ps
T911 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3490783467 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:00 PM PDT 24 196632316 ps
T912 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2382629170 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:44 PM PDT 24 136304884 ps
T913 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1375373231 Apr 28 12:22:43 PM PDT 24 Apr 28 12:22:51 PM PDT 24 75209830 ps
T914 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1429400720 Apr 28 12:21:06 PM PDT 24 Apr 28 12:21:08 PM PDT 24 120104433 ps
T915 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1687124474 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:17 PM PDT 24 303868291 ps
T916 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1233554265 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:47 PM PDT 24 49425119 ps
T917 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2012935472 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:16 PM PDT 24 102918289 ps
T918 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043530022 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 77911167 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.895915322 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:16 PM PDT 24 66782751 ps
T920 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3165126157 Apr 28 12:20:41 PM PDT 24 Apr 28 12:20:43 PM PDT 24 267647546 ps
T921 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3187970557 Apr 28 12:18:00 PM PDT 24 Apr 28 12:18:01 PM PDT 24 39399581 ps
T922 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3498334906 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:48 PM PDT 24 79347784 ps
T923 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2375510159 Apr 28 12:18:58 PM PDT 24 Apr 28 12:18:59 PM PDT 24 35129377 ps
T924 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1835526758 Apr 28 12:19:01 PM PDT 24 Apr 28 12:19:02 PM PDT 24 58569019 ps
T925 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.680193703 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 324105677 ps
T926 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2927744556 Apr 28 12:22:08 PM PDT 24 Apr 28 12:22:11 PM PDT 24 31672015 ps
T927 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4163058648 Apr 28 12:18:41 PM PDT 24 Apr 28 12:18:42 PM PDT 24 62293074 ps
T928 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.903393081 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:57 PM PDT 24 208577451 ps
T929 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1461310524 Apr 28 12:20:25 PM PDT 24 Apr 28 12:20:27 PM PDT 24 98395007 ps
T930 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573744868 Apr 28 12:18:04 PM PDT 24 Apr 28 12:18:05 PM PDT 24 420675356 ps
T931 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1283944615 Apr 28 12:22:55 PM PDT 24 Apr 28 12:23:07 PM PDT 24 161033580 ps
T932 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4130936726 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:19 PM PDT 24 52160784 ps
T933 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122731774 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:09 PM PDT 24 205912811 ps
T934 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.646798523 Apr 28 12:19:50 PM PDT 24 Apr 28 12:19:53 PM PDT 24 94038490 ps
T935 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2830543252 Apr 28 12:23:05 PM PDT 24 Apr 28 12:23:12 PM PDT 24 120541271 ps
T936 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.664675440 Apr 28 12:20:17 PM PDT 24 Apr 28 12:20:19 PM PDT 24 156248829 ps
T937 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1557082369 Apr 28 12:18:03 PM PDT 24 Apr 28 12:18:05 PM PDT 24 44463161 ps
T938 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2816304400 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:02 PM PDT 24 46745447 ps
T939 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1151529245 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:08 PM PDT 24 204960139 ps
T940 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164549106 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:12 PM PDT 24 240664404 ps
T941 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.753311920 Apr 28 12:20:33 PM PDT 24 Apr 28 12:20:35 PM PDT 24 950545639 ps
T942 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1634312726 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:00 PM PDT 24 59753463 ps
T943 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2405327276 Apr 28 12:18:52 PM PDT 24 Apr 28 12:18:54 PM PDT 24 68173950 ps
T944 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3736791101 Apr 28 12:19:02 PM PDT 24 Apr 28 12:19:03 PM PDT 24 57827831 ps

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1152611313
Short name T24
Test name
Test status
Simulation time 54919702 ps
CPU time 2.16 seconds
Started Apr 28 12:24:20 PM PDT 24
Finished Apr 28 12:24:24 PM PDT 24
Peak memory 197948 kb
Host smart-f5263229-69aa-4dc6-bc70-3f70e2e0d046
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152611313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1152611313
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3145823714
Short name T42
Test name
Test status
Simulation time 202051301 ps
CPU time 2.39 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 197844 kb
Host smart-91a8199f-eccb-4bed-b8eb-6c4c6d8fe9ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145823714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3145823714
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3194405795
Short name T10
Test name
Test status
Simulation time 44507646211 ps
CPU time 270.7 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:28:51 PM PDT 24
Peak memory 198108 kb
Host smart-6f3859f1-bda0-4198-ba6a-b56fcd733206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3194405795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3194405795
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.208738896
Short name T38
Test name
Test status
Simulation time 2287809835 ps
CPU time 0.98 seconds
Started Apr 28 12:23:51 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 214852 kb
Host smart-ed8ae4e5-3734-430f-99fe-eac639a06f9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208738896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.208738896
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3640742506
Short name T83
Test name
Test status
Simulation time 1182595687 ps
CPU time 1.47 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 196372 kb
Host smart-bfa6599a-ccbf-4fb1-9ea2-9a8fd8b5eaf7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640742506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3640742506
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1364338416
Short name T47
Test name
Test status
Simulation time 125321581 ps
CPU time 1.57 seconds
Started Apr 28 12:21:11 PM PDT 24
Finished Apr 28 12:21:13 PM PDT 24
Peak memory 197648 kb
Host smart-d653217e-424c-4e36-b32c-7c8569e7e0ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364338416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1364338416
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2462099825
Short name T2
Test name
Test status
Simulation time 60737680412 ps
CPU time 155.76 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 196128 kb
Host smart-41e6520d-96f5-4a1c-bf70-373db4391bab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462099825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2462099825
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2633620629
Short name T112
Test name
Test status
Simulation time 11427319 ps
CPU time 0.55 seconds
Started Apr 28 12:18:50 PM PDT 24
Finished Apr 28 12:18:51 PM PDT 24
Peak memory 194496 kb
Host smart-cbbef9ec-8ed3-48b0-ad5c-2ebe13e1a868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633620629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2633620629
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2911654133
Short name T100
Test name
Test status
Simulation time 66346041 ps
CPU time 0.77 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 195648 kb
Host smart-ad4dcb56-e59b-460e-8398-f6c49492f1f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911654133 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2911654133
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2046546572
Short name T89
Test name
Test status
Simulation time 96582309 ps
CPU time 0.75 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 195328 kb
Host smart-ae2052d8-2fc4-405e-b6ce-e8aa393c4696
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046546572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2046546572
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1875051317
Short name T835
Test name
Test status
Simulation time 483258798 ps
CPU time 1.04 seconds
Started Apr 28 12:21:58 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 197252 kb
Host smart-bb4010b4-88d7-4e5e-96bc-17f80cfcf5cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875051317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1875051317
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3962418840
Short name T97
Test name
Test status
Simulation time 46423773 ps
CPU time 0.74 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 196044 kb
Host smart-82b412aa-0278-4e0a-bd33-3ad73750b9b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962418840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3962418840
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3619838458
Short name T797
Test name
Test status
Simulation time 55020792 ps
CPU time 0.62 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 194364 kb
Host smart-1c6a9d93-9bf6-496e-b100-e70837249ab3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619838458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3619838458
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.650498560
Short name T748
Test name
Test status
Simulation time 14309621 ps
CPU time 0.71 seconds
Started Apr 28 12:22:35 PM PDT 24
Finished Apr 28 12:22:38 PM PDT 24
Peak memory 197328 kb
Host smart-1e2d7c53-5c08-423f-9d17-31b1e1bd82f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650498560 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.650498560
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.476460690
Short name T786
Test name
Test status
Simulation time 45835917 ps
CPU time 0.63 seconds
Started Apr 28 12:19:08 PM PDT 24
Finished Apr 28 12:19:10 PM PDT 24
Peak memory 194872 kb
Host smart-b715e09e-f342-4224-bd79-6bd23c8b4176
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476460690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.476460690
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2642282627
Short name T799
Test name
Test status
Simulation time 11184584 ps
CPU time 0.56 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 193200 kb
Host smart-a1e1de56-85e4-4716-8065-0e8d24ad47c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642282627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2642282627
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2662472553
Short name T828
Test name
Test status
Simulation time 53874655 ps
CPU time 0.61 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 194948 kb
Host smart-afcc902b-ded4-4f8c-987e-8ae5a9110dc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662472553 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2662472553
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1658645430
Short name T834
Test name
Test status
Simulation time 138058205 ps
CPU time 0.94 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 196160 kb
Host smart-ed0dfaa6-7378-4b81-844f-1432519dbbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658645430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1658645430
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3811092999
Short name T800
Test name
Test status
Simulation time 48902570 ps
CPU time 0.9 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 196496 kb
Host smart-796deabe-9109-47d2-901e-10c5a8517a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811092999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3811092999
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.355302338
Short name T776
Test name
Test status
Simulation time 674073952 ps
CPU time 2.3 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:55 PM PDT 24
Peak memory 196576 kb
Host smart-bec015ea-a89b-4a8a-a442-c70bfdccc0bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355302338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.355302338
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2271551688
Short name T844
Test name
Test status
Simulation time 19405044 ps
CPU time 0.64 seconds
Started Apr 28 12:18:57 PM PDT 24
Finished Apr 28 12:18:58 PM PDT 24
Peak memory 194412 kb
Host smart-18535745-fcf2-4d43-b187-a8afdc5ceb76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271551688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2271551688
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.733464748
Short name T724
Test name
Test status
Simulation time 74570314 ps
CPU time 1 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 197336 kb
Host smart-f61d7bf5-0a5d-4596-865c-cafbbc8a9bc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733464748 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.733464748
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4209543710
Short name T90
Test name
Test status
Simulation time 29489862 ps
CPU time 0.72 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 195020 kb
Host smart-db519e33-0b44-43ec-8fc9-677c6cfd5370
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209543710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4209543710
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2987412810
Short name T840
Test name
Test status
Simulation time 12754850 ps
CPU time 0.56 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 193000 kb
Host smart-642e14ea-8ec6-4835-88f1-95535d5e4390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987412810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2987412810
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2505533877
Short name T791
Test name
Test status
Simulation time 29654205 ps
CPU time 0.62 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 194016 kb
Host smart-f160386e-7348-4a64-9efb-4e7e4ded74fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505533877 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2505533877
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3883650773
Short name T820
Test name
Test status
Simulation time 92069775 ps
CPU time 1.45 seconds
Started Apr 28 12:18:57 PM PDT 24
Finished Apr 28 12:18:59 PM PDT 24
Peak memory 197572 kb
Host smart-15a7d543-41ae-45dd-bc69-ac01bfb43fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883650773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3883650773
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.853735538
Short name T823
Test name
Test status
Simulation time 387936432 ps
CPU time 1.35 seconds
Started Apr 28 12:18:00 PM PDT 24
Finished Apr 28 12:18:02 PM PDT 24
Peak memory 197648 kb
Host smart-0640cb43-a987-4dfa-891b-5d926dd9d08b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853735538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.853735538
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3076246933
Short name T761
Test name
Test status
Simulation time 36690395 ps
CPU time 0.7 seconds
Started Apr 28 12:21:56 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 196692 kb
Host smart-d83f907a-2dd9-4714-be52-1aeee3dcded4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076246933 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3076246933
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3690007105
Short name T86
Test name
Test status
Simulation time 15227720 ps
CPU time 0.6 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 194464 kb
Host smart-51477c78-fb36-435f-8477-1f01dda7f661
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690007105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3690007105
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2343625033
Short name T789
Test name
Test status
Simulation time 45730532 ps
CPU time 0.63 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 192736 kb
Host smart-413e7dd4-52f1-4819-9774-abf220d7454b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343625033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2343625033
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1444526630
Short name T836
Test name
Test status
Simulation time 29224053 ps
CPU time 0.72 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 194968 kb
Host smart-7a4fde39-cc07-4aca-b26f-f81c07a8896d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444526630 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1444526630
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1114486006
Short name T780
Test name
Test status
Simulation time 193891856 ps
CPU time 2.18 seconds
Started Apr 28 12:18:33 PM PDT 24
Finished Apr 28 12:18:36 PM PDT 24
Peak memory 197636 kb
Host smart-315a72db-7551-44a1-b17b-8e5bda3d2172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114486006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1114486006
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3665628078
Short name T50
Test name
Test status
Simulation time 301185144 ps
CPU time 1.09 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 197552 kb
Host smart-6a64cccd-1a4c-4fc8-9944-404c345ab27d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665628078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3665628078
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3545447345
Short name T798
Test name
Test status
Simulation time 110504291 ps
CPU time 1.33 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 197608 kb
Host smart-f2c14f68-ea6b-45dd-9ebc-b6270cd2d469
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545447345 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3545447345
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.997877498
Short name T818
Test name
Test status
Simulation time 35210528 ps
CPU time 0.58 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:06 PM PDT 24
Peak memory 194296 kb
Host smart-1df5fe26-b1c5-40a6-aaf2-d43eb5516a7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997877498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.997877498
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3865351375
Short name T775
Test name
Test status
Simulation time 25601711 ps
CPU time 0.56 seconds
Started Apr 28 12:23:32 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 193164 kb
Host smart-8c8d7dae-ba2e-4604-beeb-ad22e5867b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865351375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3865351375
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2583692614
Short name T103
Test name
Test status
Simulation time 18205816 ps
CPU time 0.78 seconds
Started Apr 28 12:18:08 PM PDT 24
Finished Apr 28 12:18:10 PM PDT 24
Peak memory 195844 kb
Host smart-37df49d2-0153-4660-aa60-299195b81bdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583692614 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2583692614
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2457049195
Short name T783
Test name
Test status
Simulation time 941986805 ps
CPU time 3.19 seconds
Started Apr 28 12:20:37 PM PDT 24
Finished Apr 28 12:20:41 PM PDT 24
Peak memory 197576 kb
Host smart-10bba779-a3bc-45e0-b63d-8bf42488712b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457049195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2457049195
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.808259340
Short name T843
Test name
Test status
Simulation time 225658373 ps
CPU time 1.51 seconds
Started Apr 28 12:18:50 PM PDT 24
Finished Apr 28 12:18:51 PM PDT 24
Peak memory 197600 kb
Host smart-c6975b16-72ea-4483-bbf1-238958f1d669
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808259340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.808259340
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1035678197
Short name T829
Test name
Test status
Simulation time 46062504 ps
CPU time 0.86 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:16 PM PDT 24
Peak memory 197412 kb
Host smart-1ee1aaf9-e546-4c5f-85b8-d238ec02d297
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035678197 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1035678197
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2558286306
Short name T95
Test name
Test status
Simulation time 26626265 ps
CPU time 0.56 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 194104 kb
Host smart-e35de1dd-8a2c-44a9-b78d-163c08a19a66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558286306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2558286306
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.932170931
Short name T721
Test name
Test status
Simulation time 17165988 ps
CPU time 0.62 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:48 PM PDT 24
Peak memory 193972 kb
Host smart-8b2ef8a6-9d16-47b5-a426-d492ecbbf20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932170931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.932170931
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2578753264
Short name T101
Test name
Test status
Simulation time 41944030 ps
CPU time 0.69 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:55 PM PDT 24
Peak memory 193876 kb
Host smart-95fe94bf-9b20-42c2-85b4-f94a1cedb791
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578753264 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2578753264
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.476818244
Short name T782
Test name
Test status
Simulation time 156610696 ps
CPU time 1.06 seconds
Started Apr 28 12:21:58 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 197040 kb
Host smart-d4591309-909d-4487-b7fc-c3db225cf45e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476818244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.476818244
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1181230207
Short name T107
Test name
Test status
Simulation time 78470819 ps
CPU time 0.8 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:16 PM PDT 24
Peak memory 197380 kb
Host smart-4b2e5301-8ff3-4fc8-930f-b5ce28322544
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181230207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1181230207
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1654748044
Short name T722
Test name
Test status
Simulation time 66918285 ps
CPU time 0.7 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 195536 kb
Host smart-d6526932-b030-4a9c-9809-fb0f13329e38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654748044 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1654748044
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1997800297
Short name T88
Test name
Test status
Simulation time 115220338 ps
CPU time 0.64 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 192644 kb
Host smart-4b8f39f1-0cb4-45fa-822b-8c7e9efdca29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997800297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1997800297
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2355075405
Short name T733
Test name
Test status
Simulation time 17824201 ps
CPU time 0.63 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 192184 kb
Host smart-bd128467-3f7d-4981-8ef5-a140cdce022f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355075405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2355075405
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.694972494
Short name T787
Test name
Test status
Simulation time 18065819 ps
CPU time 0.63 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 194368 kb
Host smart-53efd4af-1479-45da-9898-def86b6b2759
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694972494 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.694972494
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.491094948
Short name T766
Test name
Test status
Simulation time 34497407 ps
CPU time 1.78 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 197180 kb
Host smart-750cb603-0325-4326-950a-ee40964df0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491094948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.491094948
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2544758202
Short name T774
Test name
Test status
Simulation time 170153045 ps
CPU time 0.81 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 196836 kb
Host smart-df87dcd4-ac2e-4e89-b3e9-7ece3215e901
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544758202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2544758202
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1541740566
Short name T767
Test name
Test status
Simulation time 23525915 ps
CPU time 1 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 197248 kb
Host smart-70dda4ed-86e6-43a8-8044-e6aca2adc80c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541740566 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1541740566
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3963714993
Short name T92
Test name
Test status
Simulation time 14641032 ps
CPU time 0.58 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 193932 kb
Host smart-b9725579-ba88-4a6b-ab4f-29bcb597c5ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963714993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3963714993
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3972440509
Short name T726
Test name
Test status
Simulation time 24614499 ps
CPU time 0.59 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 193356 kb
Host smart-77bc8851-494c-4a58-aec6-bf62f8eed9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972440509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3972440509
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3253710164
Short name T104
Test name
Test status
Simulation time 18502149 ps
CPU time 0.7 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 195464 kb
Host smart-e6632d68-b068-4291-9c7f-62aaa8c0c0c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253710164 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3253710164
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2441051808
Short name T817
Test name
Test status
Simulation time 611028023 ps
CPU time 3 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 197524 kb
Host smart-67312267-b4c0-4083-a30b-776cbc3e5a62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441051808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2441051808
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.873853241
Short name T37
Test name
Test status
Simulation time 149849188 ps
CPU time 0.85 seconds
Started Apr 28 12:23:11 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 196620 kb
Host smart-67150dfd-7eea-4226-994a-2aab2b2c65ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873853241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.873853241
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3595288968
Short name T751
Test name
Test status
Simulation time 133154996 ps
CPU time 0.96 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 197408 kb
Host smart-8ddf6de8-2d4e-4d2a-973b-4981b739253e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595288968 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3595288968
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2668363464
Short name T742
Test name
Test status
Simulation time 10657877 ps
CPU time 0.62 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 193296 kb
Host smart-2244498d-01ff-49e7-9e5f-58fae2de18fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668363464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2668363464
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2409517902
Short name T814
Test name
Test status
Simulation time 13330482 ps
CPU time 0.63 seconds
Started Apr 28 12:20:28 PM PDT 24
Finished Apr 28 12:20:29 PM PDT 24
Peak memory 193388 kb
Host smart-a937c831-fba1-4c9e-8e77-c6f87e1ca18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409517902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2409517902
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3245026636
Short name T805
Test name
Test status
Simulation time 167228305 ps
CPU time 2.41 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:55 PM PDT 24
Peak memory 197604 kb
Host smart-36b64995-c39e-44cc-bae2-6bd638ae9adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245026636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3245026636
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2527472087
Short name T48
Test name
Test status
Simulation time 167945919 ps
CPU time 1.09 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 195868 kb
Host smart-59e93f55-e9fd-48c0-a949-4ac3df28e93f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527472087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2527472087
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.159406287
Short name T768
Test name
Test status
Simulation time 128002340 ps
CPU time 1.02 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 197348 kb
Host smart-4ccd10e0-4e0c-4ce4-b975-9e969b11cbe8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159406287 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.159406287
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2823246284
Short name T87
Test name
Test status
Simulation time 11390064 ps
CPU time 0.59 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 194216 kb
Host smart-88fe8a81-ecc4-4c29-9aaa-2060c7f4b074
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823246284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2823246284
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.4239683135
Short name T760
Test name
Test status
Simulation time 46160037 ps
CPU time 0.58 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 192932 kb
Host smart-37256d54-92b5-4850-b34f-bfbcd1c6af3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239683135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.4239683135
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1924637530
Short name T830
Test name
Test status
Simulation time 139052685 ps
CPU time 0.83 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 194816 kb
Host smart-cd288945-6d7a-4e83-ab18-1f03df405b85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924637530 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1924637530
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4094519599
Short name T756
Test name
Test status
Simulation time 44108266 ps
CPU time 1.04 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 197288 kb
Host smart-30dcf8f4-fa14-4dc9-9a22-85a745968413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094519599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.4094519599
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2849183611
Short name T46
Test name
Test status
Simulation time 388011046 ps
CPU time 1.43 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 196380 kb
Host smart-a79f2785-67d7-4aa4-8c56-f96bc6341b85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849183611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2849183611
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3736915018
Short name T762
Test name
Test status
Simulation time 134368625 ps
CPU time 1.03 seconds
Started Apr 28 12:18:13 PM PDT 24
Finished Apr 28 12:18:14 PM PDT 24
Peak memory 197664 kb
Host smart-9e768268-64a4-4dc7-b78c-43339baa2d3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736915018 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3736915018
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1982259332
Short name T837
Test name
Test status
Simulation time 37151528 ps
CPU time 0.56 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 194472 kb
Host smart-59cfcb48-2dc9-4d29-aa25-f7dd3d722ba7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982259332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1982259332
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.445655677
Short name T731
Test name
Test status
Simulation time 11400419 ps
CPU time 0.6 seconds
Started Apr 28 12:18:17 PM PDT 24
Finished Apr 28 12:18:18 PM PDT 24
Peak memory 193928 kb
Host smart-f685dc35-039d-466b-ab30-c6bd12d129ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445655677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.445655677
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4161707685
Short name T822
Test name
Test status
Simulation time 38590231 ps
CPU time 0.9 seconds
Started Apr 28 12:20:12 PM PDT 24
Finished Apr 28 12:20:13 PM PDT 24
Peak memory 196104 kb
Host smart-d2256218-9fc0-4f62-a775-19551114b467
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161707685 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4161707685
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.423697040
Short name T758
Test name
Test status
Simulation time 65404414 ps
CPU time 1.3 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:43 PM PDT 24
Peak memory 197576 kb
Host smart-5b0e00c4-bb11-4693-944a-ec7403a049ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423697040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.423697040
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1378050130
Short name T815
Test name
Test status
Simulation time 102069476 ps
CPU time 1.15 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:43 PM PDT 24
Peak memory 197552 kb
Host smart-e5ea5ac0-a79f-4c01-88b9-3153443be8ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378050130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1378050130
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3230029026
Short name T826
Test name
Test status
Simulation time 242106371 ps
CPU time 1.06 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 196244 kb
Host smart-674b78c6-2792-4fe2-8139-290f814a629c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230029026 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3230029026
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4142515783
Short name T810
Test name
Test status
Simulation time 13761519 ps
CPU time 0.61 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 191660 kb
Host smart-0c393c07-9e9c-49c9-bb03-cb70097bf781
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142515783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4142515783
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2886238238
Short name T778
Test name
Test status
Simulation time 27695566 ps
CPU time 0.64 seconds
Started Apr 28 12:18:27 PM PDT 24
Finished Apr 28 12:18:28 PM PDT 24
Peak memory 193360 kb
Host smart-fc5a99ce-0e0e-4cee-a656-1acf5e4aa9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886238238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2886238238
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1376742891
Short name T98
Test name
Test status
Simulation time 132573822 ps
CPU time 0.81 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 195348 kb
Host smart-41970689-2e08-4be5-bee0-e33229a08fd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376742891 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1376742891
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.710484435
Short name T743
Test name
Test status
Simulation time 383289996 ps
CPU time 2.67 seconds
Started Apr 28 12:18:19 PM PDT 24
Finished Apr 28 12:18:22 PM PDT 24
Peak memory 197648 kb
Host smart-d7135973-3a6e-4118-b8a8-d91426b33627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710484435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.710484435
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2512172884
Short name T35
Test name
Test status
Simulation time 256001374 ps
CPU time 1.14 seconds
Started Apr 28 12:18:19 PM PDT 24
Finished Apr 28 12:18:21 PM PDT 24
Peak memory 197152 kb
Host smart-999af041-bb78-411e-b323-fc7ec11ae0bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512172884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2512172884
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.277111764
Short name T806
Test name
Test status
Simulation time 81967161 ps
CPU time 0.92 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:41 PM PDT 24
Peak memory 197424 kb
Host smart-a96fe6e7-2359-4f3d-b22a-d2823aa975c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277111764 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.277111764
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1844854192
Short name T819
Test name
Test status
Simulation time 34907019 ps
CPU time 0.63 seconds
Started Apr 28 12:18:25 PM PDT 24
Finished Apr 28 12:18:26 PM PDT 24
Peak memory 194148 kb
Host smart-9e0c19e3-de11-4e28-8b97-7a13f402eea4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844854192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1844854192
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1840113926
Short name T824
Test name
Test status
Simulation time 13595476 ps
CPU time 0.54 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 192820 kb
Host smart-1979a1c5-975d-48bf-8898-34a83eb02c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840113926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1840113926
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1310113773
Short name T833
Test name
Test status
Simulation time 42825314 ps
CPU time 0.99 seconds
Started Apr 28 12:19:15 PM PDT 24
Finished Apr 28 12:19:16 PM PDT 24
Peak memory 197008 kb
Host smart-56e355e9-c910-45ed-bbcf-9512d075d8ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310113773 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1310113773
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3167398965
Short name T719
Test name
Test status
Simulation time 1283771737 ps
CPU time 2.13 seconds
Started Apr 28 12:18:36 PM PDT 24
Finished Apr 28 12:18:38 PM PDT 24
Peak memory 197608 kb
Host smart-f72a8f21-2421-488e-9fb2-d6974159d1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167398965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3167398965
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4197398866
Short name T36
Test name
Test status
Simulation time 120084454 ps
CPU time 1.07 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 196636 kb
Host smart-3affb86b-f63a-40e6-9143-84adf8c1c4aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197398866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4197398866
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.761312483
Short name T96
Test name
Test status
Simulation time 31118158 ps
CPU time 0.83 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 195420 kb
Host smart-8f5a4d2e-9d3e-4401-a09b-22c99ec47ae0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761312483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.761312483
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3122178017
Short name T753
Test name
Test status
Simulation time 1043330727 ps
CPU time 3.11 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:22:16 PM PDT 24
Peak memory 197240 kb
Host smart-f783fb95-6400-4dfe-8434-2ed0a39713f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122178017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3122178017
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4070634994
Short name T808
Test name
Test status
Simulation time 116310658 ps
CPU time 0.66 seconds
Started Apr 28 12:18:47 PM PDT 24
Finished Apr 28 12:18:48 PM PDT 24
Peak memory 195196 kb
Host smart-5886c61c-25ec-42ee-bf94-8925032adea3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070634994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4070634994
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2443082139
Short name T732
Test name
Test status
Simulation time 22171475 ps
CPU time 0.93 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 197112 kb
Host smart-050fab2b-d19d-4b0e-a97d-3f95b6879f28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443082139 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2443082139
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4294275871
Short name T842
Test name
Test status
Simulation time 19431773 ps
CPU time 0.58 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 192904 kb
Host smart-7404fd7b-1cd4-41f1-b5a2-bac80a7d5a07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294275871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4294275871
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2990400700
Short name T792
Test name
Test status
Simulation time 143828822 ps
CPU time 0.65 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:56 PM PDT 24
Peak memory 192872 kb
Host smart-6e786989-553d-44ae-af76-e1dfd77fa55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990400700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2990400700
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1987302137
Short name T84
Test name
Test status
Simulation time 79278587 ps
CPU time 0.64 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 194344 kb
Host smart-7860db71-4ed9-4e1c-b0f1-2bc9e0292fe5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987302137 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1987302137
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1528262769
Short name T747
Test name
Test status
Simulation time 2163725044 ps
CPU time 2.89 seconds
Started Apr 28 12:21:17 PM PDT 24
Finished Apr 28 12:21:20 PM PDT 24
Peak memory 197692 kb
Host smart-aaeffbae-f36c-4f96-9f37-356a1ea11f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528262769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1528262769
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2863039607
Short name T729
Test name
Test status
Simulation time 22554098 ps
CPU time 0.62 seconds
Started Apr 28 12:18:33 PM PDT 24
Finished Apr 28 12:18:34 PM PDT 24
Peak memory 193272 kb
Host smart-b3f64cd8-b351-4c47-b9a1-dbb8edc69b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863039607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2863039607
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.341973434
Short name T757
Test name
Test status
Simulation time 97710528 ps
CPU time 0.58 seconds
Started Apr 28 12:18:40 PM PDT 24
Finished Apr 28 12:18:41 PM PDT 24
Peak memory 193948 kb
Host smart-cba01517-8c58-418d-937f-31e51b71719a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341973434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.341973434
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3442247603
Short name T781
Test name
Test status
Simulation time 16800810 ps
CPU time 0.63 seconds
Started Apr 28 12:18:46 PM PDT 24
Finished Apr 28 12:18:47 PM PDT 24
Peak memory 193296 kb
Host smart-b5b717e8-a336-400d-ad4f-676cb96daced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442247603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3442247603
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1327645282
Short name T821
Test name
Test status
Simulation time 14473427 ps
CPU time 0.62 seconds
Started Apr 28 12:20:43 PM PDT 24
Finished Apr 28 12:20:44 PM PDT 24
Peak memory 193920 kb
Host smart-64950035-ac34-4b9a-be0b-33ff77793d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327645282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1327645282
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3215130371
Short name T745
Test name
Test status
Simulation time 14701991 ps
CPU time 0.58 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 193020 kb
Host smart-5557134f-e5c7-448f-8891-7ede81245d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215130371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3215130371
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1493431159
Short name T795
Test name
Test status
Simulation time 45455737 ps
CPU time 0.56 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 192864 kb
Host smart-99f24b9c-66bf-40f7-a2cc-f3230298c52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493431159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1493431159
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3135602983
Short name T772
Test name
Test status
Simulation time 13411950 ps
CPU time 0.56 seconds
Started Apr 28 12:23:12 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 193236 kb
Host smart-6460219f-cbd4-41d6-bbd9-5e9cbed33270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135602983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3135602983
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.591013530
Short name T727
Test name
Test status
Simulation time 15713525 ps
CPU time 0.58 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 193496 kb
Host smart-12e416f8-f020-418e-943f-87261ce7da7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591013530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.591013530
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.207869833
Short name T807
Test name
Test status
Simulation time 62917743 ps
CPU time 0.57 seconds
Started Apr 28 12:21:14 PM PDT 24
Finished Apr 28 12:21:15 PM PDT 24
Peak memory 193288 kb
Host smart-7d8bddb8-8784-4534-928c-6fc6f6850a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207869833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.207869833
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1446888325
Short name T723
Test name
Test status
Simulation time 11875530 ps
CPU time 0.6 seconds
Started Apr 28 12:19:34 PM PDT 24
Finished Apr 28 12:19:36 PM PDT 24
Peak memory 193312 kb
Host smart-2bd7aa02-5593-4b04-b8ab-d61456ed3f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446888325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1446888325
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.91351456
Short name T838
Test name
Test status
Simulation time 81464228 ps
CPU time 0.64 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:18:10 PM PDT 24
Peak memory 194752 kb
Host smart-09666e48-e118-4dc4-a279-36e8a5ca079b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91351456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
gpio_csr_aliasing.91351456
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3813296026
Short name T105
Test name
Test status
Simulation time 231863213 ps
CPU time 2.18 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 197512 kb
Host smart-4e6b23ab-d7dd-484d-abe7-e9d0d7f19396
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813296026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3813296026
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.433447104
Short name T82
Test name
Test status
Simulation time 44956230 ps
CPU time 0.71 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 192892 kb
Host smart-c8c97be4-c208-43e2-a380-d43857ee4e17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433447104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.433447104
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2410325181
Short name T784
Test name
Test status
Simulation time 44376202 ps
CPU time 0.88 seconds
Started Apr 28 12:22:32 PM PDT 24
Finished Apr 28 12:22:34 PM PDT 24
Peak memory 196692 kb
Host smart-ce73ffff-2131-4f3c-a1cc-698831d5ac87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410325181 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2410325181
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1800551095
Short name T790
Test name
Test status
Simulation time 13533520 ps
CPU time 0.66 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 192948 kb
Host smart-f66fbe07-11cf-474e-a497-c91a28a2fefc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800551095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1800551095
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2874204423
Short name T735
Test name
Test status
Simulation time 12688738 ps
CPU time 0.58 seconds
Started Apr 28 12:20:33 PM PDT 24
Finished Apr 28 12:20:35 PM PDT 24
Peak memory 193764 kb
Host smart-5b27f766-de29-4cf2-8751-78f57aa7a3f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874204423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2874204423
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3169581141
Short name T99
Test name
Test status
Simulation time 97652791 ps
CPU time 0.73 seconds
Started Apr 28 12:19:47 PM PDT 24
Finished Apr 28 12:19:49 PM PDT 24
Peak memory 196504 kb
Host smart-ebc0cf57-bbbd-4024-af11-032232b82665
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169581141 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3169581141
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3243895690
Short name T771
Test name
Test status
Simulation time 54030164 ps
CPU time 1.15 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 197256 kb
Host smart-2a508630-7175-451f-a4ff-e90d3f353d27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243895690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3243895690
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.413722461
Short name T45
Test name
Test status
Simulation time 524717840 ps
CPU time 1.5 seconds
Started Apr 28 12:21:18 PM PDT 24
Finished Apr 28 12:21:20 PM PDT 24
Peak memory 197384 kb
Host smart-46ff27a3-2c7d-40fc-9181-9165e82a7861
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413722461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.413722461
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2728866547
Short name T803
Test name
Test status
Simulation time 14819462 ps
CPU time 0.56 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 193168 kb
Host smart-3368e6f6-9e27-4b39-b7b5-f75ed4d6a254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728866547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2728866547
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1428905033
Short name T794
Test name
Test status
Simulation time 20760875 ps
CPU time 0.58 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 191760 kb
Host smart-1267e35c-314a-4ae2-bcaa-600efe35d556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428905033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1428905033
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4237475233
Short name T839
Test name
Test status
Simulation time 25539960 ps
CPU time 0.62 seconds
Started Apr 28 12:21:27 PM PDT 24
Finished Apr 28 12:21:28 PM PDT 24
Peak memory 193328 kb
Host smart-043630d0-447a-42c0-b35f-9032c572bddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237475233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4237475233
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.106384308
Short name T773
Test name
Test status
Simulation time 14882651 ps
CPU time 0.61 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 193840 kb
Host smart-d95f9495-7f2a-4893-89ec-311fbc1410c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106384308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.106384308
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3023677821
Short name T796
Test name
Test status
Simulation time 49541331 ps
CPU time 0.6 seconds
Started Apr 28 12:19:21 PM PDT 24
Finished Apr 28 12:19:22 PM PDT 24
Peak memory 193240 kb
Host smart-28bd25eb-618b-4112-86c6-3c53299a27f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023677821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3023677821
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.57476047
Short name T725
Test name
Test status
Simulation time 11694634 ps
CPU time 0.69 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 192036 kb
Host smart-8f387082-21a7-4d79-b3e7-e74ab44de9af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57476047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.57476047
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3943360460
Short name T769
Test name
Test status
Simulation time 13819864 ps
CPU time 0.62 seconds
Started Apr 28 12:21:44 PM PDT 24
Finished Apr 28 12:21:45 PM PDT 24
Peak memory 193336 kb
Host smart-35e4daf2-7306-4a71-a549-82e7cd8d4c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943360460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3943360460
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4035379517
Short name T788
Test name
Test status
Simulation time 18327046 ps
CPU time 0.59 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 192956 kb
Host smart-02e57470-861e-4c4e-b860-9f8afa529eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035379517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4035379517
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1903573353
Short name T720
Test name
Test status
Simulation time 12596234 ps
CPU time 0.56 seconds
Started Apr 28 12:19:35 PM PDT 24
Finished Apr 28 12:19:36 PM PDT 24
Peak memory 193264 kb
Host smart-f7bca153-4599-4a07-8cee-8fda5862f185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903573353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1903573353
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4272208077
Short name T777
Test name
Test status
Simulation time 12009853 ps
CPU time 0.59 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:43 PM PDT 24
Peak memory 193264 kb
Host smart-fef767ce-e627-4d44-857d-3e3aaf4cc75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272208077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4272208077
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3259331899
Short name T94
Test name
Test status
Simulation time 59786964 ps
CPU time 0.79 seconds
Started Apr 28 12:19:01 PM PDT 24
Finished Apr 28 12:19:03 PM PDT 24
Peak memory 196292 kb
Host smart-f924cd67-9eb2-4134-95fd-6136036fa66c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259331899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3259331899
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3232931816
Short name T106
Test name
Test status
Simulation time 1038990335 ps
CPU time 2.39 seconds
Started Apr 28 12:22:18 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 197188 kb
Host smart-31d249f8-5efe-49f4-992f-512a1d664200
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232931816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3232931816
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.963447883
Short name T93
Test name
Test status
Simulation time 25808519 ps
CPU time 0.61 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 194376 kb
Host smart-660a684b-204e-4bbb-8866-0984a7b76cfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963447883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.963447883
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2181267145
Short name T813
Test name
Test status
Simulation time 38978000 ps
CPU time 1.65 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 197300 kb
Host smart-638be14a-2a35-4522-8420-302023b0f1b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181267145 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2181267145
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1054779130
Short name T91
Test name
Test status
Simulation time 26313223 ps
CPU time 0.54 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:19:52 PM PDT 24
Peak memory 192484 kb
Host smart-bfc4c2d6-9b8f-470e-8ae1-0c3bad28365c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054779130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1054779130
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4141532769
Short name T764
Test name
Test status
Simulation time 11559626 ps
CPU time 0.61 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:21:57 PM PDT 24
Peak memory 193032 kb
Host smart-a6365541-5f45-472c-ae3c-e91e39a8fb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141532769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4141532769
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.665761597
Short name T102
Test name
Test status
Simulation time 23775524 ps
CPU time 0.68 seconds
Started Apr 28 12:21:50 PM PDT 24
Finished Apr 28 12:21:52 PM PDT 24
Peak memory 193156 kb
Host smart-4ab1b60a-5947-4fdd-a32f-16419d70e104
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665761597 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.665761597
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3981945823
Short name T827
Test name
Test status
Simulation time 59627805 ps
CPU time 2.56 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:57 PM PDT 24
Peak memory 196472 kb
Host smart-bb70a472-b47c-4f8c-a086-836bbfba6df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981945823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3981945823
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2226110122
Short name T809
Test name
Test status
Simulation time 252054136 ps
CPU time 1.08 seconds
Started Apr 28 12:22:29 PM PDT 24
Finished Apr 28 12:22:30 PM PDT 24
Peak memory 197524 kb
Host smart-34c43260-ffcc-4199-8989-5baa708e1073
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226110122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2226110122
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1045590015
Short name T718
Test name
Test status
Simulation time 99635477 ps
CPU time 0.62 seconds
Started Apr 28 12:21:17 PM PDT 24
Finished Apr 28 12:21:18 PM PDT 24
Peak memory 193300 kb
Host smart-0638dd38-86b0-45de-b6d5-a02f68fec0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045590015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1045590015
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1918137284
Short name T793
Test name
Test status
Simulation time 40546697 ps
CPU time 0.65 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 191552 kb
Host smart-5023ec21-e394-41b2-b946-b05827309a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918137284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1918137284
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3147512732
Short name T841
Test name
Test status
Simulation time 27742672 ps
CPU time 0.61 seconds
Started Apr 28 12:22:27 PM PDT 24
Finished Apr 28 12:22:28 PM PDT 24
Peak memory 193340 kb
Host smart-585cc78f-007b-4a23-aecb-4239ba2cf802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147512732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3147512732
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3913873835
Short name T750
Test name
Test status
Simulation time 35179710 ps
CPU time 0.6 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 191772 kb
Host smart-199eb5d0-16a9-48f0-80b1-22b48773668d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913873835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3913873835
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1227374586
Short name T749
Test name
Test status
Simulation time 49168890 ps
CPU time 0.59 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:48 PM PDT 24
Peak memory 193220 kb
Host smart-a3490742-698c-475e-be30-cad2f3c4aaeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227374586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1227374586
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3793694293
Short name T825
Test name
Test status
Simulation time 58407062 ps
CPU time 0.62 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 192512 kb
Host smart-8e50eec5-c782-4edc-a4a8-9775e597d8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793694293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3793694293
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3440351601
Short name T759
Test name
Test status
Simulation time 56201719 ps
CPU time 0.61 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 193232 kb
Host smart-f16e1a7e-9086-47a3-9fcb-fac09db31c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440351601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3440351601
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1419211860
Short name T730
Test name
Test status
Simulation time 66985838 ps
CPU time 0.56 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:21:56 PM PDT 24
Peak memory 193888 kb
Host smart-ee8dfdae-985d-4c4b-afa4-b047be536b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419211860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1419211860
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.419601399
Short name T812
Test name
Test status
Simulation time 25382039 ps
CPU time 0.57 seconds
Started Apr 28 12:19:38 PM PDT 24
Finished Apr 28 12:19:39 PM PDT 24
Peak memory 193324 kb
Host smart-b1eb9446-5f2d-4175-8e3f-4d952836fde9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419601399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.419601399
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3455323248
Short name T737
Test name
Test status
Simulation time 13196354 ps
CPU time 0.59 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:48 PM PDT 24
Peak memory 193232 kb
Host smart-3afa0071-8cb3-4a93-9d38-fbe55bd3b490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455323248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3455323248
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1628626501
Short name T746
Test name
Test status
Simulation time 73366137 ps
CPU time 1.48 seconds
Started Apr 28 12:21:50 PM PDT 24
Finished Apr 28 12:21:53 PM PDT 24
Peak memory 195672 kb
Host smart-25165d90-5199-43e2-9d6f-ec83e77cfa92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628626501 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1628626501
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.385761534
Short name T740
Test name
Test status
Simulation time 15378746 ps
CPU time 0.58 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 194208 kb
Host smart-b289c6d3-6403-45e6-888b-911f8a8248d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385761534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.385761534
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3515082043
Short name T754
Test name
Test status
Simulation time 16353817 ps
CPU time 0.59 seconds
Started Apr 28 12:17:41 PM PDT 24
Finished Apr 28 12:17:42 PM PDT 24
Peak memory 193280 kb
Host smart-8f69e5f5-2cef-4be7-a1b2-66cd3d9cc66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515082043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3515082043
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4176222364
Short name T804
Test name
Test status
Simulation time 43217682 ps
CPU time 0.62 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 194376 kb
Host smart-a6532a3c-1ba7-4f30-9709-6907a361f9ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176222364 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4176222364
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2617158466
Short name T763
Test name
Test status
Simulation time 447366151 ps
CPU time 2.3 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 197588 kb
Host smart-98de4072-43ab-4b9c-8788-3cc6608609f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617158466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2617158466
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1423148104
Short name T816
Test name
Test status
Simulation time 326209903 ps
CPU time 1.29 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:38 PM PDT 24
Peak memory 196312 kb
Host smart-a3ab960b-6a74-4d14-982f-1f05c26d32cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423148104 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1423148104
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1363028547
Short name T79
Test name
Test status
Simulation time 35295351 ps
CPU time 0.56 seconds
Started Apr 28 12:18:19 PM PDT 24
Finished Apr 28 12:18:20 PM PDT 24
Peak memory 193068 kb
Host smart-11c2dd1d-57be-4670-87cf-b148045009be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363028547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1363028547
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2029294748
Short name T741
Test name
Test status
Simulation time 13318572 ps
CPU time 0.69 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:37 PM PDT 24
Peak memory 192676 kb
Host smart-f0c457a4-8b4c-49f2-a5dc-20540b887ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029294748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2029294748
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.55544152
Short name T801
Test name
Test status
Simulation time 128195702 ps
CPU time 0.72 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 195708 kb
Host smart-07782cab-f49a-406e-acd8-c592ee4856c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55544152 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.gpio_same_csr_outstanding.55544152
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4067893739
Short name T739
Test name
Test status
Simulation time 107292587 ps
CPU time 1.87 seconds
Started Apr 28 12:17:54 PM PDT 24
Finished Apr 28 12:17:57 PM PDT 24
Peak memory 197556 kb
Host smart-418355b0-5d6c-4409-8326-721b55904310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067893739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4067893739
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4188411925
Short name T832
Test name
Test status
Simulation time 120012387 ps
CPU time 0.87 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196272 kb
Host smart-dd49603d-60b9-4ef4-ac37-21d882c13b4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188411925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4188411925
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3434100346
Short name T752
Test name
Test status
Simulation time 24450110 ps
CPU time 1.13 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 197324 kb
Host smart-646420e7-4db2-4429-8c36-99fbd040790a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434100346 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3434100346
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3035282670
Short name T738
Test name
Test status
Simulation time 18061727 ps
CPU time 0.62 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 194020 kb
Host smart-1f91d744-b25f-4d29-832b-5e60a86cb477
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035282670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3035282670
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2844546012
Short name T779
Test name
Test status
Simulation time 15952989 ps
CPU time 0.65 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 193040 kb
Host smart-a785aa99-bece-4189-bdbb-0f90f0120625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844546012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2844546012
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.197340932
Short name T802
Test name
Test status
Simulation time 16315470 ps
CPU time 0.64 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 194308 kb
Host smart-68c86233-dc12-46cd-82dc-375d6cab6081
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197340932 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.197340932
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.6561577
Short name T755
Test name
Test status
Simulation time 80126129 ps
CPU time 1.58 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:03 PM PDT 24
Peak memory 197620 kb
Host smart-1bde92c2-7f41-4c42-807d-30fe955ec5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6561577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.6561577
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.599263428
Short name T811
Test name
Test status
Simulation time 169368116 ps
CPU time 1.01 seconds
Started Apr 28 12:18:41 PM PDT 24
Finished Apr 28 12:18:42 PM PDT 24
Peak memory 197412 kb
Host smart-6e1a7049-6bd2-4db5-b225-168fc04e6c19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599263428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.599263428
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2149578956
Short name T765
Test name
Test status
Simulation time 55711273 ps
CPU time 1.43 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 195428 kb
Host smart-63e50dca-68ca-4a13-8129-ebfd9573b99b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149578956 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2149578956
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3388273607
Short name T734
Test name
Test status
Simulation time 17817870 ps
CPU time 0.6 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 191320 kb
Host smart-96ecb5ba-0487-468f-81f8-18ff4c50f983
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388273607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3388273607
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4026218943
Short name T770
Test name
Test status
Simulation time 44376041 ps
CPU time 0.59 seconds
Started Apr 28 12:18:00 PM PDT 24
Finished Apr 28 12:18:01 PM PDT 24
Peak memory 193988 kb
Host smart-6cd576fa-874e-4319-9729-a8e7d913c9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026218943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4026218943
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3989967805
Short name T81
Test name
Test status
Simulation time 70795394 ps
CPU time 0.77 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 195680 kb
Host smart-d819c501-2abd-4237-bfd2-4b888daceb48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989967805 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3989967805
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2136355589
Short name T728
Test name
Test status
Simulation time 160311143 ps
CPU time 1.82 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:19:53 PM PDT 24
Peak memory 196388 kb
Host smart-3266c71c-9ad2-451c-8768-663eb28d6b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136355589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2136355589
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2301840108
Short name T831
Test name
Test status
Simulation time 44762164 ps
CPU time 0.85 seconds
Started Apr 28 12:19:51 PM PDT 24
Finished Apr 28 12:19:53 PM PDT 24
Peak memory 196452 kb
Host smart-2378f27b-fd10-45e7-9dee-a9783785ac54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301840108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2301840108
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4052941535
Short name T785
Test name
Test status
Simulation time 76331865 ps
CPU time 0.74 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 197308 kb
Host smart-8964ef74-f3c6-4830-bead-1eed5dfa21e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052941535 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4052941535
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.287328925
Short name T85
Test name
Test status
Simulation time 15413251 ps
CPU time 0.61 seconds
Started Apr 28 12:19:40 PM PDT 24
Finished Apr 28 12:19:41 PM PDT 24
Peak memory 194684 kb
Host smart-221cd853-2eeb-4466-bb61-cece243daa92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287328925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.287328925
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.971767141
Short name T744
Test name
Test status
Simulation time 95627863 ps
CPU time 0.6 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:06 PM PDT 24
Peak memory 193908 kb
Host smart-ac3baeb3-e476-4d2f-ab62-64bcbfe3463f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971767141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.971767141
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3226193060
Short name T80
Test name
Test status
Simulation time 20412730 ps
CPU time 0.81 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 195812 kb
Host smart-dc8963eb-4870-4c38-b600-a8c6447e7584
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226193060 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3226193060
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3957936363
Short name T736
Test name
Test status
Simulation time 224408222 ps
CPU time 1.21 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 197464 kb
Host smart-d9c81632-d092-4808-bd84-32c6e62883ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957936363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3957936363
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2917043133
Short name T49
Test name
Test status
Simulation time 86211970 ps
CPU time 1.09 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 197552 kb
Host smart-e5c98adb-8a13-4fca-9876-7dc90840b6b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917043133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2917043133
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.279058453
Short name T308
Test name
Test status
Simulation time 24942930 ps
CPU time 0.53 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 193508 kb
Host smart-8d127a82-8413-4099-9d50-5e6822839f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279058453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.279058453
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2043677682
Short name T632
Test name
Test status
Simulation time 22553509 ps
CPU time 0.73 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 195924 kb
Host smart-cedf268c-b688-467b-bc2d-e13a28f4c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043677682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2043677682
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3327824387
Short name T125
Test name
Test status
Simulation time 4603486781 ps
CPU time 27.08 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:26 PM PDT 24
Peak memory 197776 kb
Host smart-88f8853d-9088-4dcb-b77b-511539f303b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327824387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3327824387
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1102106766
Short name T396
Test name
Test status
Simulation time 21628885 ps
CPU time 0.68 seconds
Started Apr 28 12:20:28 PM PDT 24
Finished Apr 28 12:20:29 PM PDT 24
Peak memory 194368 kb
Host smart-88f2335b-5b97-406c-b124-dc9bc6e2c147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102106766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1102106766
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2006073648
Short name T453
Test name
Test status
Simulation time 111213918 ps
CPU time 0.87 seconds
Started Apr 28 12:21:50 PM PDT 24
Finished Apr 28 12:21:52 PM PDT 24
Peak memory 193796 kb
Host smart-7f03dcbe-96e4-45d5-a359-6768f46910a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006073648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2006073648
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.986670334
Short name T167
Test name
Test status
Simulation time 375487557 ps
CPU time 3.65 seconds
Started Apr 28 12:18:15 PM PDT 24
Finished Apr 28 12:18:19 PM PDT 24
Peak memory 197976 kb
Host smart-a222dd4f-19f9-4467-a2cb-14400ef74bb1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986670334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.986670334
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3406674145
Short name T147
Test name
Test status
Simulation time 73952876 ps
CPU time 1.71 seconds
Started Apr 28 12:20:26 PM PDT 24
Finished Apr 28 12:20:28 PM PDT 24
Peak memory 195916 kb
Host smart-09478e7b-7265-4f17-84fb-e5a02c05045a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406674145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3406674145
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1859887440
Short name T409
Test name
Test status
Simulation time 252532899 ps
CPU time 0.77 seconds
Started Apr 28 12:18:03 PM PDT 24
Finished Apr 28 12:18:05 PM PDT 24
Peak memory 195312 kb
Host smart-6a88abc8-13b7-4a7e-95ee-3cd8039d0a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859887440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1859887440
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3141029217
Short name T636
Test name
Test status
Simulation time 17030437 ps
CPU time 0.67 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 195720 kb
Host smart-210d2081-38a9-4a03-a8f7-309562d3e700
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141029217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3141029217
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1269288611
Short name T645
Test name
Test status
Simulation time 188223024 ps
CPU time 2.27 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 197812 kb
Host smart-82ea8e1c-f968-49be-a959-d96de2a30d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269288611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1269288611
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.852437746
Short name T52
Test name
Test status
Simulation time 78171853 ps
CPU time 0.87 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 214388 kb
Host smart-151aa18d-939c-453f-a337-b124a25c6ce3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852437746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.852437746
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.946698690
Short name T301
Test name
Test status
Simulation time 39808217 ps
CPU time 1.11 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 195452 kb
Host smart-75557d6a-c2a7-498e-82d6-1eecb096b111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946698690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.946698690
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1726789500
Short name T499
Test name
Test status
Simulation time 116911979 ps
CPU time 1.2 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 194388 kb
Host smart-eb3bff60-e3c5-486e-929c-eab69892cb2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726789500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1726789500
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.311524143
Short name T433
Test name
Test status
Simulation time 22426146486 ps
CPU time 140.09 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 197280 kb
Host smart-5fe35dd6-9377-4fd5-b11f-336d998b57a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311524143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.311524143
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2688378037
Short name T581
Test name
Test status
Simulation time 28262788 ps
CPU time 0.75 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 193948 kb
Host smart-b21e01e2-69c5-450e-98c8-826724b15e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688378037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2688378037
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3833774892
Short name T207
Test name
Test status
Simulation time 912254412 ps
CPU time 6.87 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 195068 kb
Host smart-176f076a-9057-4e5a-9fdc-1fbdfb783fcf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833774892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3833774892
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2473224766
Short name T483
Test name
Test status
Simulation time 76130835 ps
CPU time 0.86 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 195928 kb
Host smart-afc1406f-e1d1-4ce6-af3f-2100c6746864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473224766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2473224766
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.577216022
Short name T126
Test name
Test status
Simulation time 31510356 ps
CPU time 0.64 seconds
Started Apr 28 12:22:51 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 194112 kb
Host smart-e74b401d-d04c-42c2-ad84-d7f989ebe43e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577216022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.577216022
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1441400249
Short name T221
Test name
Test status
Simulation time 187851000 ps
CPU time 2.05 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 194400 kb
Host smart-f1a019bb-1aa8-494a-86e3-7a1bdb53fe86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441400249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1441400249
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1748559835
Short name T498
Test name
Test status
Simulation time 115603282 ps
CPU time 2.37 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196708 kb
Host smart-464d2ac4-9860-4768-b074-93af5e7f0f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748559835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1748559835
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3893671754
Short name T190
Test name
Test status
Simulation time 51501253 ps
CPU time 1.01 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:53 PM PDT 24
Peak memory 196568 kb
Host smart-f7107835-15e5-4cfa-9c1f-4fba432ffdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893671754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3893671754
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.77095843
Short name T129
Test name
Test status
Simulation time 98108601 ps
CPU time 0.79 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 196272 kb
Host smart-df5675ec-d869-4c02-9d79-1de7e8579c9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77095843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_p
ulldown.77095843
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.204638283
Short name T358
Test name
Test status
Simulation time 190158075 ps
CPU time 2.97 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 197404 kb
Host smart-dd135e9e-2847-423f-bfef-2f45ae419734
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204638283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.204638283
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1241226237
Short name T51
Test name
Test status
Simulation time 59737792 ps
CPU time 0.75 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 213120 kb
Host smart-f827f0ff-858a-4dd2-9f17-f8ada6ff6458
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241226237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1241226237
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3214871387
Short name T350
Test name
Test status
Simulation time 217858277 ps
CPU time 1.02 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 194372 kb
Host smart-bb9a3786-490f-4f02-aad3-e5debf45da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214871387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3214871387
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3128528354
Short name T491
Test name
Test status
Simulation time 187389737 ps
CPU time 1.15 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:53 PM PDT 24
Peak memory 196116 kb
Host smart-0340f97b-c934-4d00-999c-7ae617744234
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128528354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3128528354
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.803905039
Short name T639
Test name
Test status
Simulation time 211175556754 ps
CPU time 147.43 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 197804 kb
Host smart-03f76562-64ae-4bc0-858c-7076ba4bac81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803905039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.803905039
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1522199941
Short name T473
Test name
Test status
Simulation time 14182006 ps
CPU time 0.55 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 194712 kb
Host smart-838d58fe-7fc7-4cf1-9d56-df7c5c70d0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522199941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1522199941
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3657628247
Short name T413
Test name
Test status
Simulation time 21611585 ps
CPU time 0.65 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 194744 kb
Host smart-3d3b03e6-96cb-4e6d-984f-982a59afa269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657628247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3657628247
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.821656276
Short name T642
Test name
Test status
Simulation time 350843535 ps
CPU time 13.79 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 197832 kb
Host smart-cf091eac-b8d4-43e7-bd7d-058b64933f68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821656276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.821656276
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2285715623
Short name T456
Test name
Test status
Simulation time 64204529 ps
CPU time 0.69 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 195284 kb
Host smart-de8d97a6-d7cb-4841-b6ab-999888d71418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285715623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2285715623
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4194436464
Short name T262
Test name
Test status
Simulation time 27219340 ps
CPU time 0.82 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 195368 kb
Host smart-3e9cda0f-0f5a-4f85-a649-aa41547f9ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194436464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4194436464
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2232056297
Short name T697
Test name
Test status
Simulation time 59016911 ps
CPU time 0.99 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 195888 kb
Host smart-e6064cdc-f2c4-4d2f-aac0-e270a61912bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232056297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2232056297
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1336030125
Short name T174
Test name
Test status
Simulation time 77014895 ps
CPU time 2.18 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 195560 kb
Host smart-c22dac54-ae7e-4ccf-9a42-cb43451699f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336030125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1336030125
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2083932251
Short name T187
Test name
Test status
Simulation time 161715698 ps
CPU time 1.02 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:48 PM PDT 24
Peak memory 195648 kb
Host smart-feb9f247-296e-4efb-a95c-c0990b0a1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083932251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2083932251
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.766193834
Short name T709
Test name
Test status
Simulation time 70279696 ps
CPU time 0.78 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 196500 kb
Host smart-75159457-bed2-432e-9e32-f466ada4928f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766193834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.766193834
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.605561698
Short name T182
Test name
Test status
Simulation time 66913140 ps
CPU time 2.89 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 197824 kb
Host smart-2e413efb-8603-4003-9b33-51504ac2f7c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605561698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.605561698
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2335412778
Short name T57
Test name
Test status
Simulation time 83444115 ps
CPU time 1.35 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 196296 kb
Host smart-d0e9481a-c379-46d0-bf17-24e8765a8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335412778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2335412778
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1121454588
Short name T195
Test name
Test status
Simulation time 209747491 ps
CPU time 1.02 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 195456 kb
Host smart-86e2bb84-6be0-401e-bc7d-7b7b72ee849e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121454588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1121454588
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1039759366
Short name T286
Test name
Test status
Simulation time 22799900245 ps
CPU time 55.44 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 198056 kb
Host smart-9b9dd90c-4bc5-4036-8a3c-4c40c4146725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039759366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1039759366
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1976793295
Short name T33
Test name
Test status
Simulation time 15087208666 ps
CPU time 479.74 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:32:07 PM PDT 24
Peak memory 198108 kb
Host smart-e05b957a-18a3-4600-80b6-deb0aceb3d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1976793295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1976793295
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.226670363
Short name T278
Test name
Test status
Simulation time 11233397 ps
CPU time 0.57 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 194520 kb
Host smart-e6551180-5fe3-4955-8411-89d6b5ad018f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226670363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.226670363
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4241954585
Short name T189
Test name
Test status
Simulation time 71255933 ps
CPU time 0.81 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 196452 kb
Host smart-45c7c085-e113-418e-b546-82fb8c751858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241954585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4241954585
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2686216429
Short name T72
Test name
Test status
Simulation time 1924365025 ps
CPU time 25.55 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196740 kb
Host smart-daac4b36-adfa-4e23-87de-4c142bd1bec4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686216429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2686216429
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.164148686
Short name T316
Test name
Test status
Simulation time 41534270 ps
CPU time 0.67 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 194460 kb
Host smart-ba12d081-e4ff-4d69-b89b-1496586a760c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164148686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.164148686
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1245672075
Short name T148
Test name
Test status
Simulation time 87046380 ps
CPU time 1.35 seconds
Started Apr 28 12:23:49 PM PDT 24
Finished Apr 28 12:23:52 PM PDT 24
Peak memory 197920 kb
Host smart-c6f8cd2a-55bb-4db5-b1ac-1f22f255ce4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245672075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1245672075
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1500178785
Short name T496
Test name
Test status
Simulation time 26835634 ps
CPU time 1.12 seconds
Started Apr 28 12:24:34 PM PDT 24
Finished Apr 28 12:24:39 PM PDT 24
Peak memory 197888 kb
Host smart-c1355248-cddd-4a91-adae-c0b337433322
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500178785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1500178785
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1998471330
Short name T234
Test name
Test status
Simulation time 394575601 ps
CPU time 2.58 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 196940 kb
Host smart-14b796e3-fc04-4fcf-954b-49759cfb3e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998471330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1998471330
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3889806410
Short name T25
Test name
Test status
Simulation time 206197761 ps
CPU time 1.17 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196496 kb
Host smart-b47429a6-1f0a-4942-9601-8c017d1671c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889806410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3889806410
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1522935039
Short name T400
Test name
Test status
Simulation time 120160492 ps
CPU time 0.8 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 196984 kb
Host smart-1d78ea9a-7493-4b63-90ce-bde340f29f43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522935039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1522935039
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3160994365
Short name T8
Test name
Test status
Simulation time 456564187 ps
CPU time 4.86 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 197788 kb
Host smart-3a25aa9d-69b9-4f5f-98be-89c90fb78a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160994365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3160994365
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.814212756
Short name T313
Test name
Test status
Simulation time 424181388 ps
CPU time 1.34 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 195336 kb
Host smart-eb586493-3853-4157-85ea-7cf62a417c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814212756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.814212756
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2161028154
Short name T225
Test name
Test status
Simulation time 152091752 ps
CPU time 0.94 seconds
Started Apr 28 12:24:01 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 195628 kb
Host smart-516e34f3-005b-494f-872b-ca4c123e43a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161028154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2161028154
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.973376868
Short name T399
Test name
Test status
Simulation time 36539126007 ps
CPU time 131.34 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:26:12 PM PDT 24
Peak memory 198092 kb
Host smart-e10ea5aa-8ecc-499f-8ebf-51619142812d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973376868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.973376868
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3959101374
Short name T220
Test name
Test status
Simulation time 63461021 ps
CPU time 0.57 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 194560 kb
Host smart-f2771fd8-87d0-4bd2-ae78-0f0314d836de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959101374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3959101374
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3248940141
Short name T391
Test name
Test status
Simulation time 104092002 ps
CPU time 0.83 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 195672 kb
Host smart-b49e2fd6-b929-4e28-90c2-00be76c30317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248940141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3248940141
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.347539509
Short name T589
Test name
Test status
Simulation time 1275323203 ps
CPU time 10.65 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 197776 kb
Host smart-0e94a1af-77c1-4dc4-9c26-98ceea6599a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347539509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.347539509
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2696973958
Short name T576
Test name
Test status
Simulation time 52391110 ps
CPU time 0.81 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 196560 kb
Host smart-6e5150d4-a6a9-4509-a350-55edb420a1e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696973958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2696973958
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2779799526
Short name T533
Test name
Test status
Simulation time 108784866 ps
CPU time 0.7 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:24:13 PM PDT 24
Peak memory 196144 kb
Host smart-4b1150e3-3005-403e-a0cb-e8268140fb68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779799526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2779799526
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.879994790
Short name T401
Test name
Test status
Simulation time 85597571 ps
CPU time 3.32 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 197836 kb
Host smart-179dea7e-7d19-4704-870b-bf21cbdccf0f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879994790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.879994790
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2300040852
Short name T349
Test name
Test status
Simulation time 89922690 ps
CPU time 2.52 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 197924 kb
Host smart-e8c31eb0-c93b-44b6-8740-7f0951bf81b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300040852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2300040852
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.84284813
Short name T267
Test name
Test status
Simulation time 38445350 ps
CPU time 1.19 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 196456 kb
Host smart-bb50f9d2-619d-4dcd-bae7-8b3aa5de9f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84284813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.84284813
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2849596589
Short name T287
Test name
Test status
Simulation time 32923819 ps
CPU time 0.8 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 195412 kb
Host smart-9c8ac9e6-95de-4488-a17a-340e59d20a23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849596589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2849596589
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.284567777
Short name T65
Test name
Test status
Simulation time 555631026 ps
CPU time 4.1 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 197864 kb
Host smart-d192869e-b442-40c0-bea6-1c705653674f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284567777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.284567777
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1559384693
Short name T115
Test name
Test status
Simulation time 81141012 ps
CPU time 1.27 seconds
Started Apr 28 12:24:03 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 196580 kb
Host smart-208f3594-d71a-467c-9fc6-99e065b26ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559384693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1559384693
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3965819629
Short name T346
Test name
Test status
Simulation time 140460600 ps
CPU time 1.15 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 197884 kb
Host smart-86fc6012-8277-44ff-b4cd-9cada89a91e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965819629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3965819629
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.344869355
Short name T500
Test name
Test status
Simulation time 3100982159 ps
CPU time 19.16 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:25 PM PDT 24
Peak memory 198072 kb
Host smart-7be59809-be54-4c62-9fde-1c3b0366343c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344869355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.344869355
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.556955940
Short name T588
Test name
Test status
Simulation time 12234432 ps
CPU time 0.58 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 194564 kb
Host smart-b3c4145c-272b-45a1-a8fd-8c3c113425d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556955940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.556955940
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.633859876
Short name T186
Test name
Test status
Simulation time 25147069 ps
CPU time 0.71 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 194124 kb
Host smart-2ee1edae-8730-4e76-9b69-b2b642dd1bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633859876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.633859876
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.395461937
Short name T64
Test name
Test status
Simulation time 193970852 ps
CPU time 10.38 seconds
Started Apr 28 12:24:10 PM PDT 24
Finished Apr 28 12:24:22 PM PDT 24
Peak memory 197892 kb
Host smart-ffe7b373-6b2a-4fae-bd7c-fbf42192cc26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395461937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.395461937
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1109613414
Short name T333
Test name
Test status
Simulation time 41219073 ps
CPU time 0.7 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 195272 kb
Host smart-d4dd8f8c-d3fa-4534-8396-32e21d3f45c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109613414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1109613414
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1718500515
Short name T364
Test name
Test status
Simulation time 108751115 ps
CPU time 0.93 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196012 kb
Host smart-a56350e0-f636-4764-b05c-5381bd51a62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718500515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1718500515
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3865069242
Short name T392
Test name
Test status
Simulation time 233490403 ps
CPU time 1.83 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 197916 kb
Host smart-3529dca2-dab7-470d-99f4-291658869a9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865069242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3865069242
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2997015932
Short name T160
Test name
Test status
Simulation time 1027296938 ps
CPU time 2.89 seconds
Started Apr 28 12:24:03 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 197048 kb
Host smart-8785ec2e-211c-4beb-91af-718570ee1b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997015932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2997015932
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2099599664
Short name T280
Test name
Test status
Simulation time 31291127 ps
CPU time 0.7 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 195264 kb
Host smart-38da8162-9edc-4458-aaf8-b7dbea03b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099599664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2099599664
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2772284067
Short name T418
Test name
Test status
Simulation time 287618888 ps
CPU time 1.1 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 196912 kb
Host smart-59b3cda9-8f65-42e6-acbf-0ca59528919a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772284067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2772284067
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3360010286
Short name T4
Test name
Test status
Simulation time 1281506049 ps
CPU time 4.3 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:33 PM PDT 24
Peak memory 197784 kb
Host smart-f10d2c63-1072-4417-bbbe-b1996740e01c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360010286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3360010286
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3566449055
Short name T266
Test name
Test status
Simulation time 253922977 ps
CPU time 0.89 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 196036 kb
Host smart-f7673b51-603b-4c89-b374-3af930cd29ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566449055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3566449055
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1191851303
Short name T447
Test name
Test status
Simulation time 135982073 ps
CPU time 1.1 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:27 PM PDT 24
Peak memory 195692 kb
Host smart-ac27924b-8261-43cc-bc26-734c2307dcc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191851303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1191851303
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2737041850
Short name T303
Test name
Test status
Simulation time 11467476624 ps
CPU time 153.59 seconds
Started Apr 28 12:23:47 PM PDT 24
Finished Apr 28 12:26:23 PM PDT 24
Peak memory 198128 kb
Host smart-cb17ff9b-6771-4849-8177-5a045926de4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737041850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2737041850
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.4169869635
Short name T701
Test name
Test status
Simulation time 43102132086 ps
CPU time 314.05 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:29:15 PM PDT 24
Peak memory 198048 kb
Host smart-89d88eb6-ca52-4496-aacb-20c9b72e4724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4169869635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.4169869635
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4026625157
Short name T655
Test name
Test status
Simulation time 43330545 ps
CPU time 0.61 seconds
Started Apr 28 12:24:03 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 193780 kb
Host smart-c2c96beb-08e7-4a12-bb9b-faa15c2c2648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026625157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4026625157
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3723802057
Short name T427
Test name
Test status
Simulation time 19543066 ps
CPU time 0.69 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:00 PM PDT 24
Peak memory 194044 kb
Host smart-b9b35212-2945-4efe-a57e-6fe483d1b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723802057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3723802057
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1052405064
Short name T603
Test name
Test status
Simulation time 198423630 ps
CPU time 6.33 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 195976 kb
Host smart-f7ee2320-05c4-4d63-84c2-4c39bc2a094b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052405064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1052405064
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4169070971
Short name T70
Test name
Test status
Simulation time 45521182 ps
CPU time 0.85 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 197212 kb
Host smart-7f55b5ce-a3d8-4bf8-ad48-cc2df2e2bb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169070971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4169070971
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3874594766
Short name T525
Test name
Test status
Simulation time 76063208 ps
CPU time 1 seconds
Started Apr 28 12:23:49 PM PDT 24
Finished Apr 28 12:23:52 PM PDT 24
Peak memory 195704 kb
Host smart-c21b823e-3974-403d-aa51-5aedd5f598ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874594766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3874594766
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3025733517
Short name T518
Test name
Test status
Simulation time 65516249 ps
CPU time 1.35 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 196308 kb
Host smart-1b6825ec-f4ec-47c8-9546-9d60b5c9b7a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025733517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3025733517
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2203402709
Short name T345
Test name
Test status
Simulation time 313636362 ps
CPU time 1.72 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 195596 kb
Host smart-b11598ad-25f6-4db7-92f7-4225d0ef6caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203402709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2203402709
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.171907846
Short name T578
Test name
Test status
Simulation time 118349780 ps
CPU time 0.8 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 196348 kb
Host smart-5b3ae840-f853-4b0a-b940-afd824517e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171907846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.171907846
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3481493041
Short name T348
Test name
Test status
Simulation time 65452684 ps
CPU time 0.65 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 194960 kb
Host smart-32ebe99e-361f-4ba5-a415-f4df81e15ca6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481493041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3481493041
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4131418220
Short name T222
Test name
Test status
Simulation time 401039097 ps
CPU time 4.82 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 197924 kb
Host smart-96c893f9-778e-4562-9b5d-67f1ca7e8e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131418220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4131418220
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3885646869
Short name T461
Test name
Test status
Simulation time 136241988 ps
CPU time 0.96 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 195508 kb
Host smart-42f5e72c-c35c-4057-be06-09f91c8a0d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885646869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3885646869
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.644204360
Short name T295
Test name
Test status
Simulation time 165132511 ps
CPU time 1.34 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 196628 kb
Host smart-be79a4e9-4170-4f49-9717-f33fa593d79e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644204360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.644204360
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1119081035
Short name T429
Test name
Test status
Simulation time 2475485982 ps
CPU time 63.22 seconds
Started Apr 28 12:24:20 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 198052 kb
Host smart-216cc370-3f16-4d57-be44-d0f46a21eed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119081035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1119081035
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3222168679
Short name T494
Test name
Test status
Simulation time 253835051312 ps
CPU time 1318.24 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 198068 kb
Host smart-51b22526-22df-42e5-9039-5c1fb84d967a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3222168679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3222168679
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.632122999
Short name T680
Test name
Test status
Simulation time 27459369 ps
CPU time 0.52 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 192596 kb
Host smart-5b05b928-58ef-4282-9c09-cb881af3babc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632122999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.632122999
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.4199830068
Short name T416
Test name
Test status
Simulation time 44121714 ps
CPU time 0.6 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:00 PM PDT 24
Peak memory 193308 kb
Host smart-9b5b1cfa-6492-4b0f-9143-951133267c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199830068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.4199830068
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1314762326
Short name T376
Test name
Test status
Simulation time 516188088 ps
CPU time 3.36 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 195312 kb
Host smart-55662d0f-b908-4415-8530-0a9188b08598
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314762326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1314762326
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2536141806
Short name T513
Test name
Test status
Simulation time 200689123 ps
CPU time 0.83 seconds
Started Apr 28 12:24:17 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 195856 kb
Host smart-749a602d-dd1a-4c08-96dd-95bcdb1e18a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536141806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2536141806
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4013221784
Short name T633
Test name
Test status
Simulation time 29726775 ps
CPU time 0.72 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:14 PM PDT 24
Peak memory 195388 kb
Host smart-b36bc114-a960-4665-b314-d39fbf6d87de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013221784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4013221784
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2465793251
Short name T209
Test name
Test status
Simulation time 76748993 ps
CPU time 2.79 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 196180 kb
Host smart-de90f435-c539-4914-b9d0-33807bb52489
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465793251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2465793251
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3633056841
Short name T417
Test name
Test status
Simulation time 584322748 ps
CPU time 3.01 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 196900 kb
Host smart-44e71421-fac7-44c8-89a4-5c6e4ce3ed51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633056841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3633056841
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3083360055
Short name T273
Test name
Test status
Simulation time 42193605 ps
CPU time 0.95 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196368 kb
Host smart-bd6b22bf-3437-47a6-910b-ef874a396f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083360055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3083360055
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2327416493
Short name T568
Test name
Test status
Simulation time 33003333 ps
CPU time 0.76 seconds
Started Apr 28 12:24:08 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 196464 kb
Host smart-73046354-5125-469f-b24e-21fba7c8bad4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327416493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2327416493
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3567309864
Short name T610
Test name
Test status
Simulation time 165897766 ps
CPU time 3.53 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:39 PM PDT 24
Peak memory 197796 kb
Host smart-f3cf87fa-46bc-4b4f-bdfc-b7c0aeb4f1a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567309864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3567309864
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2112136605
Short name T180
Test name
Test status
Simulation time 23347835 ps
CPU time 0.71 seconds
Started Apr 28 12:23:51 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 195764 kb
Host smart-14be847b-2bad-49e8-8b48-0e891b56948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112136605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2112136605
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1430052277
Short name T244
Test name
Test status
Simulation time 87270175 ps
CPU time 1.34 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 197780 kb
Host smart-b3b4b9bf-0d87-4cd2-ae72-7edd422d5d06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430052277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1430052277
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1825336128
Short name T237
Test name
Test status
Simulation time 4216234281 ps
CPU time 104.41 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:25:47 PM PDT 24
Peak memory 198012 kb
Host smart-3c774dfa-c5ec-4098-82c9-1bbfbbdcd41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825336128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1825336128
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2651022984
Short name T28
Test name
Test status
Simulation time 13101962 ps
CPU time 0.58 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 194568 kb
Host smart-979136b1-5032-4b73-b54f-8cffebe7e24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651022984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2651022984
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1139079431
Short name T149
Test name
Test status
Simulation time 20057698 ps
CPU time 0.62 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 193884 kb
Host smart-5128d842-7369-4026-aa60-70e6b91998ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139079431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1139079431
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2707870633
Short name T248
Test name
Test status
Simulation time 3797028444 ps
CPU time 11.76 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 196640 kb
Host smart-fcc9b674-5cd6-4fd6-89ba-7d8c20a475b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707870633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2707870633
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.791883202
Short name T638
Test name
Test status
Simulation time 83635858 ps
CPU time 0.92 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 196196 kb
Host smart-26f4d5f0-3a0d-47c3-b4b9-187f101ec6db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791883202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.791883202
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.259485800
Short name T505
Test name
Test status
Simulation time 318051728 ps
CPU time 0.94 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196032 kb
Host smart-f37b98d4-494f-441d-8bdd-4175a4dccbbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259485800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.259485800
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2515773147
Short name T75
Test name
Test status
Simulation time 177248161 ps
CPU time 3.24 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 197960 kb
Host smart-b4be803f-9473-4c2c-80b8-db9800a78d1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515773147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2515773147
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.718270413
Short name T279
Test name
Test status
Simulation time 152911138 ps
CPU time 1.33 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 196660 kb
Host smart-b70e3727-4917-4dc1-ab85-37682fe5638c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718270413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
718270413
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2117595865
Short name T495
Test name
Test status
Simulation time 120367508 ps
CPU time 1.21 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 196684 kb
Host smart-8eae95b9-2450-4cdb-93a5-ad0193b3d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117595865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2117595865
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2739441708
Short name T76
Test name
Test status
Simulation time 380697935 ps
CPU time 1.24 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 195488 kb
Host smart-fd678860-3832-441b-b4ac-bb4020aa1dc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739441708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2739441708
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3628023977
Short name T302
Test name
Test status
Simulation time 183336140 ps
CPU time 3.51 seconds
Started Apr 28 12:24:21 PM PDT 24
Finished Apr 28 12:24:25 PM PDT 24
Peak memory 197764 kb
Host smart-54f044fc-c1c0-414e-9050-58691338c139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628023977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3628023977
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3992677231
Short name T707
Test name
Test status
Simulation time 137137306 ps
CPU time 0.91 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 196164 kb
Host smart-c8ff9c67-0d31-428c-bbcd-df1ea451e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992677231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3992677231
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4095874902
Short name T390
Test name
Test status
Simulation time 191254394 ps
CPU time 1.1 seconds
Started Apr 28 12:24:16 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 195436 kb
Host smart-3eb0e794-4e64-4945-bae9-04590c0f1d58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095874902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4095874902
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3398905930
Short name T516
Test name
Test status
Simulation time 21453488116 ps
CPU time 82.55 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 198016 kb
Host smart-7882cbda-16af-44bd-a75f-c98a2ad93efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398905930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3398905930
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3310391840
Short name T666
Test name
Test status
Simulation time 16090782 ps
CPU time 0.6 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:33 PM PDT 24
Peak memory 193932 kb
Host smart-38c185b7-6171-4db5-8408-8ad568678bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310391840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3310391840
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1639780198
Short name T277
Test name
Test status
Simulation time 32576669 ps
CPU time 0.65 seconds
Started Apr 28 12:24:02 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 194100 kb
Host smart-9d9c8693-4fe4-4551-b757-ca6484cc591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639780198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1639780198
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4053566421
Short name T161
Test name
Test status
Simulation time 591726484 ps
CPU time 2.95 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 196008 kb
Host smart-608a9d33-2a6a-42e2-9c2e-103f64264fc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053566421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4053566421
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1018062195
Short name T211
Test name
Test status
Simulation time 39683625 ps
CPU time 0.67 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 194380 kb
Host smart-302b3dc6-20f3-4eb6-84f8-473d48b59f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018062195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1018062195
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.605992377
Short name T29
Test name
Test status
Simulation time 51417374 ps
CPU time 1.27 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 197008 kb
Host smart-c8febdb8-0d4d-451f-9056-41e44bba5c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605992377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.605992377
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3131743044
Short name T415
Test name
Test status
Simulation time 23322323 ps
CPU time 0.91 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 196712 kb
Host smart-85146043-b05c-444f-9ef3-19dcdac9caea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131743044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3131743044
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.569850068
Short name T170
Test name
Test status
Simulation time 232003380 ps
CPU time 1.66 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 195884 kb
Host smart-28ac8433-d96d-4bb1-9126-57d882579773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569850068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
569850068
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.84584046
Short name T363
Test name
Test status
Simulation time 128009154 ps
CPU time 1.15 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 197808 kb
Host smart-102724f1-873b-4708-aae4-b7f6d064b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84584046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.84584046
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.699811341
Short name T245
Test name
Test status
Simulation time 53146433 ps
CPU time 0.96 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 195728 kb
Host smart-ad26088d-4273-420c-829b-314af9f028a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699811341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.699811341
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3606680379
Short name T510
Test name
Test status
Simulation time 710468522 ps
CPU time 4.28 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 197864 kb
Host smart-dfc6a63c-c319-49be-8838-547c4f0f2cb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606680379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3606680379
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2322121158
Short name T622
Test name
Test status
Simulation time 204988104 ps
CPU time 0.86 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 196064 kb
Host smart-1fc8d9de-6275-45f5-bdfd-e85bbdc92612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322121158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2322121158
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2339972813
Short name T55
Test name
Test status
Simulation time 162934181 ps
CPU time 0.74 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 195060 kb
Host smart-dbd8e322-61ea-4168-877b-464933712cb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339972813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2339972813
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2764306585
Short name T217
Test name
Test status
Simulation time 15639970088 ps
CPU time 99.99 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:25:32 PM PDT 24
Peak memory 198052 kb
Host smart-20bff7ef-0c0e-46a2-87ff-32ceffb75cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764306585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2764306585
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2832384010
Short name T437
Test name
Test status
Simulation time 425505037239 ps
CPU time 1794.54 seconds
Started Apr 28 12:24:20 PM PDT 24
Finished Apr 28 12:54:16 PM PDT 24
Peak memory 198104 kb
Host smart-1d536892-35cb-49f7-9e1b-3aa6500b8209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2832384010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2832384010
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1265657254
Short name T689
Test name
Test status
Simulation time 30303740 ps
CPU time 0.59 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 193816 kb
Host smart-424d7ef9-6972-4d83-b459-6f682f5cc6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265657254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1265657254
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.403220305
Short name T592
Test name
Test status
Simulation time 25859664 ps
CPU time 0.7 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 195892 kb
Host smart-f322fc68-8ac8-4aeb-a31b-2bdbbde43894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403220305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.403220305
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2234608805
Short name T229
Test name
Test status
Simulation time 1026014027 ps
CPU time 28.92 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 196580 kb
Host smart-61a31a05-9cbb-4a8e-ba52-b9f65c924a1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234608805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2234608805
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3554164483
Short name T631
Test name
Test status
Simulation time 23524475 ps
CPU time 0.7 seconds
Started Apr 28 12:24:23 PM PDT 24
Finished Apr 28 12:24:25 PM PDT 24
Peak memory 194816 kb
Host smart-5e81a109-d8e9-4a83-a4e9-7f624d780ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554164483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3554164483
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1644041067
Short name T564
Test name
Test status
Simulation time 63111716 ps
CPU time 1.05 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 195628 kb
Host smart-25ac0891-2a6b-4d2f-baac-1c90b7587273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644041067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1644041067
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1038338340
Short name T239
Test name
Test status
Simulation time 73777484 ps
CPU time 1.46 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 196156 kb
Host smart-2b5cddc9-085b-4620-affd-6846ac99ac0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038338340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1038338340
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3236127099
Short name T550
Test name
Test status
Simulation time 531085087 ps
CPU time 2.35 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 195652 kb
Host smart-1e98668f-9cf3-464d-aad5-1268841f1073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236127099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3236127099
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1734306308
Short name T675
Test name
Test status
Simulation time 38041202 ps
CPU time 0.81 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 196344 kb
Host smart-89d597b0-0afe-44c2-ba0b-aa8c0b0b3d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734306308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1734306308
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3127411295
Short name T600
Test name
Test status
Simulation time 74663320 ps
CPU time 1.16 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:17 PM PDT 24
Peak memory 196940 kb
Host smart-05f95a6f-6713-4d31-9ba5-00c7f5c68b4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127411295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3127411295
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1450324309
Short name T543
Test name
Test status
Simulation time 1745856642 ps
CPU time 4.83 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 197380 kb
Host smart-1e1cd7c9-1fa0-406e-b826-67f428e8528f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450324309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1450324309
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1003394569
Short name T118
Test name
Test status
Simulation time 218595212 ps
CPU time 1.16 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 196796 kb
Host smart-f7931289-b98e-43cf-9ad9-5f0854e5c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003394569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1003394569
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3443006247
Short name T458
Test name
Test status
Simulation time 53199149 ps
CPU time 0.88 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:17 PM PDT 24
Peak memory 195308 kb
Host smart-7be1d615-551c-4bd4-b2e5-c9534a54e1e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443006247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3443006247
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3399947732
Short name T432
Test name
Test status
Simulation time 54092259120 ps
CPU time 188.07 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:27:40 PM PDT 24
Peak memory 197996 kb
Host smart-9743f6a0-4034-4ab9-8ed5-e2c29aa40a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399947732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3399947732
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1136598873
Short name T555
Test name
Test status
Simulation time 10798176654 ps
CPU time 318.23 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:29:31 PM PDT 24
Peak memory 198208 kb
Host smart-3e6c6d9b-11c5-4a1d-a981-a10af1d9e375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1136598873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1136598873
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1871686733
Short name T133
Test name
Test status
Simulation time 11456993 ps
CPU time 0.55 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 193696 kb
Host smart-d9ff83e2-bc8a-4295-ab87-951b0cb95e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871686733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1871686733
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.495561091
Short name T687
Test name
Test status
Simulation time 23816087 ps
CPU time 0.63 seconds
Started Apr 28 12:24:08 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 193840 kb
Host smart-6dedd574-18d0-4952-ad76-0f33795c44bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495561091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.495561091
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.219930087
Short name T577
Test name
Test status
Simulation time 206506869 ps
CPU time 9.46 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:13 PM PDT 24
Peak memory 196592 kb
Host smart-4f957c63-f982-4a73-b434-5f9e994315f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219930087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.219930087
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.246712107
Short name T470
Test name
Test status
Simulation time 42266706 ps
CPU time 0.74 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 195568 kb
Host smart-f36dafa4-218a-4af4-8cc2-b65306eb8426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246712107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.246712107
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.292907516
Short name T68
Test name
Test status
Simulation time 33869017 ps
CPU time 0.91 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 195708 kb
Host smart-6bb26377-f121-4bb9-b782-a33c10700723
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292907516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.292907516
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2085220941
Short name T524
Test name
Test status
Simulation time 172350483 ps
CPU time 1.09 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 196984 kb
Host smart-54ed2ede-bb2f-4e8d-b509-0c2fcacefac3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085220941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2085220941
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3621041659
Short name T233
Test name
Test status
Simulation time 89921509 ps
CPU time 2.57 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 196864 kb
Host smart-ce66c724-5254-4c33-a5d2-d09ff6d8d254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621041659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3621041659
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1619155901
Short name T614
Test name
Test status
Simulation time 57154779 ps
CPU time 1.12 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 195672 kb
Host smart-baa12d9e-c635-4602-a2d4-a13bc05e5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619155901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1619155901
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2460605844
Short name T554
Test name
Test status
Simulation time 298001767 ps
CPU time 1.12 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 197060 kb
Host smart-ff6a54eb-42c4-4f3c-af9f-2e7a8b507bde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460605844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2460605844
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1041028512
Short name T681
Test name
Test status
Simulation time 290830367 ps
CPU time 3.34 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 197908 kb
Host smart-87c1e0eb-2427-435c-a1aa-8dc422255335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041028512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1041028512
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2538551991
Short name T127
Test name
Test status
Simulation time 116372554 ps
CPU time 0.83 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 195144 kb
Host smart-20e8ba30-ce7b-446a-94c1-3b36ba2cbcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538551991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2538551991
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.891327780
Short name T307
Test name
Test status
Simulation time 312269751 ps
CPU time 1.29 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 196708 kb
Host smart-9893cc59-fd27-4ca7-bb43-0e31a0ad6444
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891327780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.891327780
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3651268293
Short name T381
Test name
Test status
Simulation time 3000904351 ps
CPU time 38.32 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 197976 kb
Host smart-e72b2c40-55d9-4f11-9270-8d542e0365ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651268293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3651268293
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.752675122
Short name T630
Test name
Test status
Simulation time 27524063 ps
CPU time 0.58 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 192588 kb
Host smart-5f3d1897-0427-4378-a03d-f50fa07a21aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752675122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.752675122
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1774254097
Short name T559
Test name
Test status
Simulation time 21831265 ps
CPU time 0.69 seconds
Started Apr 28 12:20:21 PM PDT 24
Finished Apr 28 12:20:23 PM PDT 24
Peak memory 195812 kb
Host smart-3e9a5a4f-3983-4254-9b37-7206920693fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774254097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1774254097
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3815558213
Short name T590
Test name
Test status
Simulation time 298517598 ps
CPU time 10.16 seconds
Started Apr 28 12:18:43 PM PDT 24
Finished Apr 28 12:18:53 PM PDT 24
Peak memory 197008 kb
Host smart-a939daec-c702-4efa-8918-5b9fc1ee95cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815558213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3815558213
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3537013159
Short name T611
Test name
Test status
Simulation time 253507962 ps
CPU time 0.94 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:17:12 PM PDT 24
Peak memory 196356 kb
Host smart-bdcee2b1-ad34-4a55-b15a-f298a7edfffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537013159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3537013159
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3151654104
Short name T506
Test name
Test status
Simulation time 75605612 ps
CPU time 1.13 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:38 PM PDT 24
Peak memory 194768 kb
Host smart-a4b5de5e-5160-4f9e-a869-7672d846c895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151654104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3151654104
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2884814237
Short name T158
Test name
Test status
Simulation time 32271834 ps
CPU time 1.22 seconds
Started Apr 28 12:19:40 PM PDT 24
Finished Apr 28 12:19:42 PM PDT 24
Peak memory 196332 kb
Host smart-e8ebf509-2e77-4f58-b164-6179447a337c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884814237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2884814237
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.334035276
Short name T708
Test name
Test status
Simulation time 125211054 ps
CPU time 1.06 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:54 PM PDT 24
Peak memory 196056 kb
Host smart-4fd43562-189e-417a-9ad6-ef919e8b3698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334035276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.334035276
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.920085391
Short name T523
Test name
Test status
Simulation time 55731015 ps
CPU time 0.67 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 193932 kb
Host smart-67022d78-7037-4d8b-8535-eadfe26dc5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920085391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.920085391
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2954218467
Short name T111
Test name
Test status
Simulation time 114979733 ps
CPU time 1.01 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 194528 kb
Host smart-bc7923d8-6fa7-4f81-a21e-061b8d536b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954218467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2954218467
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1092438237
Short name T365
Test name
Test status
Simulation time 746078285 ps
CPU time 2.59 seconds
Started Apr 28 12:22:01 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 197260 kb
Host smart-f2a04215-d54b-4a81-bd96-21be7f890f0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092438237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1092438237
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3495630926
Short name T39
Test name
Test status
Simulation time 41160577 ps
CPU time 0.8 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:55 PM PDT 24
Peak memory 212288 kb
Host smart-ac30c9d8-0722-4dbd-8039-264cb4751775
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495630926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3495630926
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.608853439
Short name T710
Test name
Test status
Simulation time 69049952 ps
CPU time 0.73 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 195396 kb
Host smart-35859e3d-479a-4f3c-ae06-662331d2b29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608853439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.608853439
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4062632766
Short name T652
Test name
Test status
Simulation time 57999197 ps
CPU time 1.11 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196116 kb
Host smart-447d7935-480e-4f85-9f7f-af5ce9fb293f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062632766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4062632766
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1072819724
Short name T138
Test name
Test status
Simulation time 36194387 ps
CPU time 0.55 seconds
Started Apr 28 12:24:03 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 194012 kb
Host smart-f5a1e3b3-085a-4ae3-951c-43d8c941d8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072819724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1072819724
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4148406023
Short name T604
Test name
Test status
Simulation time 29864496 ps
CPU time 0.71 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 195084 kb
Host smart-0836a1ea-9a78-45b8-bb48-f1ebe0ac7008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148406023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4148406023
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.607028532
Short name T445
Test name
Test status
Simulation time 1511322690 ps
CPU time 21.31 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196628 kb
Host smart-aa51d22f-e7e8-4c9a-a017-ac89f33f8c30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607028532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.607028532
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3456322169
Short name T640
Test name
Test status
Simulation time 197691617 ps
CPU time 0.67 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 194484 kb
Host smart-c98cc149-6e87-40f5-aeae-b3e9cd010d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456322169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3456322169
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1901035284
Short name T508
Test name
Test status
Simulation time 176114662 ps
CPU time 1.22 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196712 kb
Host smart-64b128b3-61ef-42f2-8492-f3d84a89493b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901035284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1901035284
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1368133498
Short name T503
Test name
Test status
Simulation time 165443298 ps
CPU time 3.18 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 198000 kb
Host smart-4a92fd4d-8808-48c1-aa06-e4e9aca550d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368133498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1368133498
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2825018352
Short name T228
Test name
Test status
Simulation time 147544126 ps
CPU time 2.88 seconds
Started Apr 28 12:24:23 PM PDT 24
Finished Apr 28 12:24:27 PM PDT 24
Peak memory 195624 kb
Host smart-c34a526c-afda-4ca5-b3c1-70afa9471fe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825018352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2825018352
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.60853344
Short name T315
Test name
Test status
Simulation time 44606553 ps
CPU time 0.97 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 195896 kb
Host smart-57846e0c-ee59-4c3c-824e-f0ac3b62f94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60853344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.60853344
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3691691078
Short name T480
Test name
Test status
Simulation time 69201906 ps
CPU time 0.76 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 196340 kb
Host smart-0e65989c-d5be-4285-9a33-73df6192aa22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691691078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3691691078
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.648883280
Short name T3
Test name
Test status
Simulation time 141601291 ps
CPU time 1.19 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 196096 kb
Host smart-8935217d-60f1-4f5a-94cd-490efe5d80b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648883280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.648883280
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.156742031
Short name T648
Test name
Test status
Simulation time 120897671 ps
CPU time 1.2 seconds
Started Apr 28 12:24:05 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 195584 kb
Host smart-5e73b346-1584-4d04-b0c8-8c53d10ae301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156742031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.156742031
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.284614609
Short name T54
Test name
Test status
Simulation time 658735172 ps
CPU time 1.27 seconds
Started Apr 28 12:24:04 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 197852 kb
Host smart-2f70d26b-e6c5-4e85-bb2b-42dae44e5fa0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284614609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.284614609
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3902003527
Short name T556
Test name
Test status
Simulation time 33388418620 ps
CPU time 178.24 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:27:46 PM PDT 24
Peak memory 198020 kb
Host smart-91d7436d-ee7a-4398-92ba-17915d229e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902003527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3902003527
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3491355806
Short name T59
Test name
Test status
Simulation time 320142134225 ps
CPU time 1623.71 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:51:26 PM PDT 24
Peak memory 198140 kb
Host smart-c8689bfa-176f-43d0-be90-871f760d22e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3491355806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3491355806
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.362081768
Short name T566
Test name
Test status
Simulation time 14568965 ps
CPU time 0.58 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:17 PM PDT 24
Peak memory 194496 kb
Host smart-991f662a-26ba-4cd6-9296-cf06329ba8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362081768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.362081768
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3765306226
Short name T403
Test name
Test status
Simulation time 33239923 ps
CPU time 0.91 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 195704 kb
Host smart-26ddffdd-e5d1-4494-a697-9182cf2940ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765306226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3765306226
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2048643167
Short name T544
Test name
Test status
Simulation time 239022891 ps
CPU time 11.52 seconds
Started Apr 28 12:24:07 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 196784 kb
Host smart-8cdb5f57-f705-4cff-b95d-68f0c5747d4f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048643167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2048643167
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.669813658
Short name T579
Test name
Test status
Simulation time 238031918 ps
CPU time 0.87 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 195936 kb
Host smart-eeb04e4e-d0e2-4d81-9701-a178b721080f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669813658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.669813658
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1733095152
Short name T184
Test name
Test status
Simulation time 99915524 ps
CPU time 1.28 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 195624 kb
Host smart-31f63722-69e8-4a1e-83be-b36e4aafecee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733095152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1733095152
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1780828511
Short name T394
Test name
Test status
Simulation time 256057253 ps
CPU time 2.54 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 197856 kb
Host smart-8fdb6383-cbcd-4d2e-8a41-289343f7ed9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780828511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1780828511
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1192790252
Short name T593
Test name
Test status
Simulation time 270845903 ps
CPU time 1.49 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 195896 kb
Host smart-02f043b6-83cf-4bf6-9642-d1435c954cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192790252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1192790252
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1312762209
Short name T165
Test name
Test status
Simulation time 91699307 ps
CPU time 0.91 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:32 PM PDT 24
Peak memory 196660 kb
Host smart-c69ccb89-d983-4edd-814d-d88bd8c864ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312762209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1312762209
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3112816116
Short name T717
Test name
Test status
Simulation time 194535884 ps
CPU time 1.16 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 195764 kb
Host smart-72eff486-d656-418d-a6ec-534dde960e2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112816116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3112816116
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.707453523
Short name T660
Test name
Test status
Simulation time 160356781 ps
CPU time 3.29 seconds
Started Apr 28 12:24:07 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 197740 kb
Host smart-f77fd07a-d351-400b-8b5b-131c1b0236f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707453523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.707453523
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4276902582
Short name T507
Test name
Test status
Simulation time 248777345 ps
CPU time 1.05 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 195408 kb
Host smart-f1c3b04e-164b-4098-aed8-9d0fc944d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276902582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4276902582
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2524804293
Short name T618
Test name
Test status
Simulation time 140477066 ps
CPU time 0.89 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 196176 kb
Host smart-77ae09c1-fac8-44d9-8aa3-bc8d6d391033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524804293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2524804293
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.67279695
Short name T121
Test name
Test status
Simulation time 5538222418 ps
CPU time 138.82 seconds
Started Apr 28 12:24:34 PM PDT 24
Finished Apr 28 12:26:57 PM PDT 24
Peak memory 197968 kb
Host smart-5de173a3-868d-4941-8204-57da86f4c7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67279695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gp
io_stress_all.67279695
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3634511010
Short name T683
Test name
Test status
Simulation time 32245105 ps
CPU time 0.56 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 193864 kb
Host smart-cc396116-8685-47fc-8800-07729ef571b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634511010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3634511010
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1501020145
Short name T571
Test name
Test status
Simulation time 101107691 ps
CPU time 0.76 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 195108 kb
Host smart-645d2b1a-264b-4a1f-a9b1-961450e3cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501020145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1501020145
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1358819437
Short name T623
Test name
Test status
Simulation time 405269749 ps
CPU time 4.3 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 196824 kb
Host smart-38014e96-7fa7-4d1d-9545-05492267976e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358819437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1358819437
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3789323281
Short name T214
Test name
Test status
Simulation time 118409036 ps
CPU time 0.66 seconds
Started Apr 28 12:24:02 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 194464 kb
Host smart-3a34a28b-7050-4714-b060-8d6b4c4f4159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789323281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3789323281
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.867832619
Short name T713
Test name
Test status
Simulation time 53047459 ps
CPU time 0.87 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:33 PM PDT 24
Peak memory 195768 kb
Host smart-40730ad5-fc92-4506-8f8e-3393e5bb7aed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867832619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.867832619
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2863541487
Short name T260
Test name
Test status
Simulation time 32496005 ps
CPU time 1.22 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 196332 kb
Host smart-b38a5d10-b5a4-4080-89aa-4c2bf459623b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863541487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2863541487
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2116553232
Short name T378
Test name
Test status
Simulation time 1569300560 ps
CPU time 3.31 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 197860 kb
Host smart-9b0beffe-e7b2-4567-b736-14b0571990fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116553232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2116553232
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3908824695
Short name T615
Test name
Test status
Simulation time 37000937 ps
CPU time 0.83 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:24 PM PDT 24
Peak memory 197164 kb
Host smart-1e83e6d4-3e4d-4f8c-9de5-ddea24dfb65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908824695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3908824695
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1455993499
Short name T451
Test name
Test status
Simulation time 20596574 ps
CPU time 0.77 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 196104 kb
Host smart-5255ed26-dce9-4aa0-9ae4-c45ee496efee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455993499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1455993499
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3507772708
Short name T283
Test name
Test status
Simulation time 230471582 ps
CPU time 3.6 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 197908 kb
Host smart-887da75b-e5f8-402d-b9a5-30637702a88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507772708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3507772708
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3655519284
Short name T449
Test name
Test status
Simulation time 78599006 ps
CPU time 1.21 seconds
Started Apr 28 12:24:17 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 195688 kb
Host smart-566174f7-2902-4d76-9832-8b79c87636ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655519284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3655519284
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2158909126
Short name T490
Test name
Test status
Simulation time 48363031 ps
CPU time 0.96 seconds
Started Apr 28 12:24:17 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 196072 kb
Host smart-37dc1304-67d5-45ba-b2d7-87e236272e61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158909126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2158909126
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2249298050
Short name T637
Test name
Test status
Simulation time 33111094407 ps
CPU time 227.08 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:28:16 PM PDT 24
Peak memory 197244 kb
Host smart-12ad0bcd-8460-4236-ac68-bf6c442f83a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249298050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2249298050
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.415635613
Short name T296
Test name
Test status
Simulation time 31722229 ps
CPU time 0.58 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 194724 kb
Host smart-b5ae9d1b-cc93-4ed1-9b40-081f3e8a8ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415635613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.415635613
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3096675893
Short name T651
Test name
Test status
Simulation time 35816030 ps
CPU time 0.64 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 194688 kb
Host smart-6d530b91-0ab8-4875-bc18-99bce8fbcffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096675893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3096675893
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1014344242
Short name T151
Test name
Test status
Simulation time 1014822457 ps
CPU time 26.33 seconds
Started Apr 28 12:24:20 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 195384 kb
Host smart-688b6154-65d6-43b3-95d6-33e989557381
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014344242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1014344242
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3687107469
Short name T294
Test name
Test status
Simulation time 25615509 ps
CPU time 0.69 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:27 PM PDT 24
Peak memory 194532 kb
Host smart-efaba530-b9ab-4863-8ce7-dd2bf92473b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687107469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3687107469
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1688313771
Short name T422
Test name
Test status
Simulation time 36899745 ps
CPU time 0.78 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 196184 kb
Host smart-857c776c-8a5a-4bb4-a1c5-a98cb839dd00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688313771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1688313771
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.715582871
Short name T276
Test name
Test status
Simulation time 153862041 ps
CPU time 2.91 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 197800 kb
Host smart-06293b45-d242-4bbe-b93d-ba223e52da4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715582871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.715582871
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2610443392
Short name T659
Test name
Test status
Simulation time 89354531 ps
CPU time 1.47 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 195884 kb
Host smart-84b983fe-e827-44b6-9601-b5394055ffcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610443392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2610443392
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2655645017
Short name T26
Test name
Test status
Simulation time 158713117 ps
CPU time 1.03 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:32 PM PDT 24
Peak memory 195756 kb
Host smart-8bea3f37-fe9f-4803-a17c-c5c6501f4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655645017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2655645017
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4130204426
Short name T526
Test name
Test status
Simulation time 137461306 ps
CPU time 0.63 seconds
Started Apr 28 12:24:07 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 194848 kb
Host smart-b91b2e2e-441e-4912-8d28-ac670485b5c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130204426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4130204426
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.787282922
Short name T298
Test name
Test status
Simulation time 139686865 ps
CPU time 4.49 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 197840 kb
Host smart-1a56cd2d-1b87-49a1-b0d5-d564bbf9aa06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787282922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.787282922
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.4178048619
Short name T142
Test name
Test status
Simulation time 37531212 ps
CPU time 0.82 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:24 PM PDT 24
Peak memory 195184 kb
Host smart-2a37b1f0-acf5-468c-8da4-ace0aeafcdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178048619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.4178048619
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1144422129
Short name T132
Test name
Test status
Simulation time 37983214 ps
CPU time 0.69 seconds
Started Apr 28 12:24:09 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 193960 kb
Host smart-f9d1ee31-063c-4e2e-8093-ad2c4fc6d6ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144422129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1144422129
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3106795513
Short name T602
Test name
Test status
Simulation time 5326106251 ps
CPU time 72.77 seconds
Started Apr 28 12:24:23 PM PDT 24
Finished Apr 28 12:25:37 PM PDT 24
Peak memory 198000 kb
Host smart-778fa226-996c-417f-a312-0591fc1b798d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106795513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3106795513
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2037044845
Short name T411
Test name
Test status
Simulation time 11959007377 ps
CPU time 333.28 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:29:50 PM PDT 24
Peak memory 198200 kb
Host smart-16d48ec2-d3a7-4491-8022-6b24a5efea30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2037044845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2037044845
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2057479336
Short name T193
Test name
Test status
Simulation time 42712030 ps
CPU time 0.56 seconds
Started Apr 28 12:24:04 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 193788 kb
Host smart-72606500-974b-4514-9772-5138b827d9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057479336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2057479336
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.827084401
Short name T166
Test name
Test status
Simulation time 64555310 ps
CPU time 0.77 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 195716 kb
Host smart-787b9159-ebe0-480c-9bc1-9eab35770684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827084401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.827084401
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1321539525
Short name T606
Test name
Test status
Simulation time 739268745 ps
CPU time 13.35 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 196828 kb
Host smart-32b21cc9-53ed-4567-8d19-4c17fd889e12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321539525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1321539525
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1398482529
Short name T21
Test name
Test status
Simulation time 333912140 ps
CPU time 0.65 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 194528 kb
Host smart-e367e57a-e678-4003-a406-ccea9795f5d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398482529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1398482529
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1911643577
Short name T323
Test name
Test status
Simulation time 78823320 ps
CPU time 1.19 seconds
Started Apr 28 12:24:16 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 196840 kb
Host smart-b959a94f-0531-4808-92c0-6510d79629f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911643577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1911643577
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1693882917
Short name T617
Test name
Test status
Simulation time 1155910772 ps
CPU time 2.62 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 196332 kb
Host smart-bafbd994-4342-4b2b-8a89-71df808288e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693882917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1693882917
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1078019795
Short name T232
Test name
Test status
Simulation time 62005241 ps
CPU time 1.17 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 197016 kb
Host smart-80ec2092-40b4-4b80-b3ff-0c967a9e39bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078019795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1078019795
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.93225217
Short name T435
Test name
Test status
Simulation time 71548920 ps
CPU time 0.71 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 195888 kb
Host smart-e60e31e5-4520-44ff-9444-76ee4a68e05c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93225217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_
pulldown.93225217
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2339413668
Short name T467
Test name
Test status
Simulation time 2550458783 ps
CPU time 6.47 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 197968 kb
Host smart-18aed282-bd67-4b8f-b441-93061c9488fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339413668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2339413668
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2744146931
Short name T663
Test name
Test status
Simulation time 146741075 ps
CPU time 1.4 seconds
Started Apr 28 12:24:23 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 196088 kb
Host smart-4d29b09e-eece-4873-a6ba-8542a6badda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744146931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2744146931
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3864461711
Short name T430
Test name
Test status
Simulation time 36719647 ps
CPU time 1.05 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 195612 kb
Host smart-eee76e07-90b3-4e85-999d-45dfa6086516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864461711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3864461711
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3750932330
Short name T326
Test name
Test status
Simulation time 6500001576 ps
CPU time 40.27 seconds
Started Apr 28 12:24:10 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 197968 kb
Host smart-f54e6562-5c0f-44c4-a116-034297422679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750932330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3750932330
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4074832284
Short name T110
Test name
Test status
Simulation time 12859103 ps
CPU time 0.56 seconds
Started Apr 28 12:24:08 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 193804 kb
Host smart-29d682de-52c4-45a2-ab59-65b80d648f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074832284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4074832284
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3606084662
Short name T471
Test name
Test status
Simulation time 182079822 ps
CPU time 0.82 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 196460 kb
Host smart-bbe8c8a1-e078-407b-b899-b79f082e51f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606084662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3606084662
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2742974899
Short name T282
Test name
Test status
Simulation time 279083359 ps
CPU time 13.57 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196780 kb
Host smart-363e3c5d-8bbd-4604-bcd1-569092224bac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742974899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2742974899
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3468704136
Short name T702
Test name
Test status
Simulation time 19109148 ps
CPU time 0.62 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:39 PM PDT 24
Peak memory 194404 kb
Host smart-12ac2469-f477-4d50-a950-a8adb332ada8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468704136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3468704136
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3643630462
Short name T530
Test name
Test status
Simulation time 283975830 ps
CPU time 0.96 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 195908 kb
Host smart-5ed2cc52-1eae-4038-b7a0-9ebc36382362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643630462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3643630462
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3190481695
Short name T452
Test name
Test status
Simulation time 221461330 ps
CPU time 2.11 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:17 PM PDT 24
Peak memory 197864 kb
Host smart-a118156d-afa7-4c2d-8afa-a9c287842964
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190481695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3190481695
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1159038872
Short name T465
Test name
Test status
Simulation time 157688743 ps
CPU time 3.31 seconds
Started Apr 28 12:24:23 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 197868 kb
Host smart-2096705a-bac3-4e4c-8f0b-91aa4ea73f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159038872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1159038872
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3506862237
Short name T549
Test name
Test status
Simulation time 615717112 ps
CPU time 1.26 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:37 PM PDT 24
Peak memory 196872 kb
Host smart-54f27a23-5a70-4848-aaa4-2af940b351b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506862237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3506862237
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4023554133
Short name T30
Test name
Test status
Simulation time 27109580 ps
CPU time 0.91 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196588 kb
Host smart-a5c0b3cf-3c45-4032-ade9-f94742b42872
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023554133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4023554133
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2693000370
Short name T662
Test name
Test status
Simulation time 57993220 ps
CPU time 1.07 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:22 PM PDT 24
Peak memory 196756 kb
Host smart-c80fbd47-3659-42f4-a6f2-5205ecf26d94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693000370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2693000370
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.50875315
Short name T481
Test name
Test status
Simulation time 430149441 ps
CPU time 1.22 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 197860 kb
Host smart-b0a5e28b-8e02-4ab0-87b7-cf7448a90f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50875315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.50875315
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.147691073
Short name T594
Test name
Test status
Simulation time 57349312 ps
CPU time 1.02 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 195556 kb
Host smart-3b5b2613-de81-4d29-a149-aa79c2640f77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147691073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.147691073
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.981164319
Short name T608
Test name
Test status
Simulation time 14902854619 ps
CPU time 195.27 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:27:45 PM PDT 24
Peak memory 197916 kb
Host smart-03cb85d9-ba88-4fed-8b23-e737a642a5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981164319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.981164319
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.868123045
Short name T538
Test name
Test status
Simulation time 16330078 ps
CPU time 0.56 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 193736 kb
Host smart-b63356eb-c7c0-4f39-bff4-2bccd7bf8a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868123045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.868123045
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3171999580
Short name T67
Test name
Test status
Simulation time 19294358 ps
CPU time 0.63 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 193960 kb
Host smart-28f92604-2699-425c-9a81-ea749e7dae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171999580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3171999580
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3623271401
Short name T322
Test name
Test status
Simulation time 3392645632 ps
CPU time 27.43 seconds
Started Apr 28 12:24:02 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 197548 kb
Host smart-8060a536-49d2-4038-9e9e-c155df59d4d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623271401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3623271401
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1384017495
Short name T32
Test name
Test status
Simulation time 49844176 ps
CPU time 0.9 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 197736 kb
Host smart-2b6ba20a-566b-45cc-852c-751703d1e56c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384017495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1384017495
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3529527079
Short name T288
Test name
Test status
Simulation time 19478473 ps
CPU time 0.66 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 195048 kb
Host smart-f33735b6-68df-45a5-a0ca-78526a087a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529527079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3529527079
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1889522964
Short name T108
Test name
Test status
Simulation time 183554830 ps
CPU time 1.86 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 198044 kb
Host smart-430bce12-1074-4956-ba69-3cd6b92882be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889522964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1889522964
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1078872373
Short name T474
Test name
Test status
Simulation time 318758171 ps
CPU time 2.38 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 196448 kb
Host smart-fdaa7933-dd6e-4596-9d27-b556f1234515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078872373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1078872373
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2001130633
Short name T419
Test name
Test status
Simulation time 46867946 ps
CPU time 0.6 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 194192 kb
Host smart-0ca9fc70-b30e-4138-a407-980e0f1e13e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001130633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2001130633
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.640468776
Short name T629
Test name
Test status
Simulation time 230433599 ps
CPU time 1.2 seconds
Started Apr 28 12:24:10 PM PDT 24
Finished Apr 28 12:24:13 PM PDT 24
Peak memory 196652 kb
Host smart-37e5836f-4290-4501-b467-9a6d351603ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640468776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.640468776
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3644543021
Short name T259
Test name
Test status
Simulation time 1460202073 ps
CPU time 6.36 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 197824 kb
Host smart-17359705-2485-48a5-a69b-f04f0960cfa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644543021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3644543021
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1349534508
Short name T420
Test name
Test status
Simulation time 69433220 ps
CPU time 1.06 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:24:13 PM PDT 24
Peak memory 196156 kb
Host smart-e984d4fb-34e0-4987-b186-cd2662665b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349534508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1349534508
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1336867380
Short name T466
Test name
Test status
Simulation time 282185637 ps
CPU time 1.31 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 196424 kb
Host smart-f8bbfea3-3f23-4b61-9007-0a140b088bab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336867380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1336867380
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.852661058
Short name T703
Test name
Test status
Simulation time 1230028719 ps
CPU time 30.55 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:25:02 PM PDT 24
Peak memory 198036 kb
Host smart-8d450335-1966-4c38-9c22-ab261b49549a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852661058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.852661058
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.78970005
Short name T291
Test name
Test status
Simulation time 46292370029 ps
CPU time 880.38 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:38:57 PM PDT 24
Peak memory 198104 kb
Host smart-b63a9ac6-ffb3-4ecc-a8c3-c58bc80f100a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=78970005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.78970005
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.851972196
Short name T469
Test name
Test status
Simulation time 51589874 ps
CPU time 0.57 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 193964 kb
Host smart-19dca506-7edb-4818-903e-134b5b019f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851972196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.851972196
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4057670641
Short name T450
Test name
Test status
Simulation time 109566277 ps
CPU time 0.78 seconds
Started Apr 28 12:24:20 PM PDT 24
Finished Apr 28 12:24:22 PM PDT 24
Peak memory 195228 kb
Host smart-4247ac14-ef0b-4fd1-a7c8-07e0208ce1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057670641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4057670641
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3169989155
Short name T290
Test name
Test status
Simulation time 757444536 ps
CPU time 23.72 seconds
Started Apr 28 12:24:34 PM PDT 24
Finished Apr 28 12:25:02 PM PDT 24
Peak memory 195384 kb
Host smart-d1b89fbb-4911-4d6c-9850-9d013f159c20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169989155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3169989155
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2887376148
Short name T598
Test name
Test status
Simulation time 51434113 ps
CPU time 0.82 seconds
Started Apr 28 12:24:17 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 195956 kb
Host smart-f2d8c39e-3dd6-4c8a-bfaf-5b249ef5c602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887376148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2887376148
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3638346863
Short name T297
Test name
Test status
Simulation time 78671134 ps
CPU time 1.24 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 195740 kb
Host smart-afc64a8c-8a5e-461c-8313-2431f5f1777e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638346863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3638346863
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3531334951
Short name T341
Test name
Test status
Simulation time 176713551 ps
CPU time 1.11 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 197956 kb
Host smart-dd940ca7-4cdb-4d06-b039-0a67e3b28d0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531334951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3531334951
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2071675402
Short name T309
Test name
Test status
Simulation time 718417872 ps
CPU time 3.13 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 196716 kb
Host smart-89c8ef3d-9272-43fa-afe6-963b670d510a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071675402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2071675402
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.694902461
Short name T641
Test name
Test status
Simulation time 48366265 ps
CPU time 0.94 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 195792 kb
Host smart-cdcac9de-40b1-4f9c-a2d4-9e3022de287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694902461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.694902461
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1701504094
Short name T343
Test name
Test status
Simulation time 303387175 ps
CPU time 1.1 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 195832 kb
Host smart-0d12f51d-2447-4e01-a519-c6ead06ee910
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701504094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1701504094
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1951697981
Short name T155
Test name
Test status
Simulation time 98836598 ps
CPU time 1.81 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 197760 kb
Host smart-b94e9402-977f-427a-95cd-89e7d4c676cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951697981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1951697981
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.519649079
Short name T171
Test name
Test status
Simulation time 68367940 ps
CPU time 1.09 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 196048 kb
Host smart-9eaf8ad4-bd0b-4146-beda-ffbe6b622644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519649079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.519649079
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3391466696
Short name T656
Test name
Test status
Simulation time 36286432 ps
CPU time 0.94 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:27 PM PDT 24
Peak memory 195380 kb
Host smart-c745eecb-f6a7-43aa-a3a0-5235887d84bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391466696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3391466696
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2528857469
Short name T635
Test name
Test status
Simulation time 12226815374 ps
CPU time 63.67 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:25:23 PM PDT 24
Peak memory 198008 kb
Host smart-a1e571ac-c489-4b4f-89dc-c0e57c3db719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528857469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2528857469
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2134402118
Short name T15
Test name
Test status
Simulation time 212535756086 ps
CPU time 2037.75 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 198192 kb
Host smart-8bddd74b-e6c0-40f6-97d8-1a14bb7da02b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2134402118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2134402118
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2778839571
Short name T44
Test name
Test status
Simulation time 17019232 ps
CPU time 0.56 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 193788 kb
Host smart-4d553edf-bddb-4886-98c6-3a163088b422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778839571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2778839571
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3067711236
Short name T548
Test name
Test status
Simulation time 41871744 ps
CPU time 0.79 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 194008 kb
Host smart-4ce9f97c-3991-4e61-adfb-5e53fde0f4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067711236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3067711236
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.932274356
Short name T361
Test name
Test status
Simulation time 1007918283 ps
CPU time 19.7 seconds
Started Apr 28 12:24:07 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 197036 kb
Host smart-59807dc0-e6a3-435e-bd62-bac5b665face
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932274356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.932274356
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3272140931
Short name T716
Test name
Test status
Simulation time 62735282 ps
CPU time 0.86 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 197612 kb
Host smart-6a204760-e259-46ac-b2f9-6aced335ea0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272140931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3272140931
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.281761220
Short name T561
Test name
Test status
Simulation time 95666569 ps
CPU time 1.27 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 196552 kb
Host smart-af7742ad-3fb9-49a8-baa5-c2418a93d3f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281761220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.281761220
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2413713106
Short name T150
Test name
Test status
Simulation time 34431594 ps
CPU time 0.89 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 195912 kb
Host smart-cfd34900-3c77-4799-b457-0672bed70d11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413713106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2413713106
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1109107065
Short name T545
Test name
Test status
Simulation time 198986739 ps
CPU time 1.39 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 195756 kb
Host smart-fd364430-16a2-4b8d-b239-c7e2b645bbfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109107065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1109107065
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3532414153
Short name T320
Test name
Test status
Simulation time 61994530 ps
CPU time 1.08 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 195832 kb
Host smart-9185294a-b7a4-4ab4-b89f-1f3727df60c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532414153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3532414153
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.87584060
Short name T706
Test name
Test status
Simulation time 50951908 ps
CPU time 0.99 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 196480 kb
Host smart-a26502b0-fc75-4aa1-a5b3-a646694532d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87584060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup_
pulldown.87584060
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.867911758
Short name T9
Test name
Test status
Simulation time 78703094 ps
CPU time 1.23 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:26 PM PDT 24
Peak memory 196128 kb
Host smart-8b37fd2a-3346-43b5-85e2-68b0205fa650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867911758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.867911758
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1982489479
Short name T501
Test name
Test status
Simulation time 248213818 ps
CPU time 1.18 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196424 kb
Host smart-943b8919-2f2a-4a53-bb46-8f3b41f176b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982489479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1982489479
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.690765310
Short name T502
Test name
Test status
Simulation time 299532251 ps
CPU time 1.27 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 196600 kb
Host smart-a7e807d9-4089-412d-8860-f2015af5b145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690765310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.690765310
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2654037889
Short name T264
Test name
Test status
Simulation time 22019440243 ps
CPU time 45.31 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:25:18 PM PDT 24
Peak memory 198068 kb
Host smart-5af90fdd-b07f-4ca8-baa7-de34cc63fb60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654037889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2654037889
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.458079200
Short name T58
Test name
Test status
Simulation time 213398616767 ps
CPU time 1348.35 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:47:05 PM PDT 24
Peak memory 198128 kb
Host smart-a8f2f8bf-38c2-4408-afae-8abfa882533f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=458079200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.458079200
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4000591389
Short name T599
Test name
Test status
Simulation time 40269754 ps
CPU time 0.55 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 193840 kb
Host smart-95b086e5-60bd-4469-ae77-5e45cb62edee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000591389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4000591389
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3343412881
Short name T66
Test name
Test status
Simulation time 60156280 ps
CPU time 0.66 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 194052 kb
Host smart-7167ba79-4677-4b7a-bbdb-13de7cecfbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343412881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3343412881
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1057214335
Short name T522
Test name
Test status
Simulation time 810594637 ps
CPU time 25.47 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 197740 kb
Host smart-7643542c-2f60-49c7-8b12-932b0c6d5b09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057214335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1057214335
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2167814771
Short name T664
Test name
Test status
Simulation time 68722811 ps
CPU time 0.65 seconds
Started Apr 28 12:24:43 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 194876 kb
Host smart-a99af526-9e0e-45fc-babc-e64d6f82ca1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167814771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2167814771
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3019611353
Short name T163
Test name
Test status
Simulation time 62853722 ps
CPU time 0.63 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:14 PM PDT 24
Peak memory 194260 kb
Host smart-eb8fd2ae-f24c-4f7a-a980-1556a8ec796b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019611353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3019611353
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2082135346
Short name T116
Test name
Test status
Simulation time 117702037 ps
CPU time 2.31 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:39 PM PDT 24
Peak memory 197924 kb
Host smart-31c1b594-06ce-47d4-b580-6c803eb23fac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082135346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2082135346
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2666994371
Short name T704
Test name
Test status
Simulation time 66955102 ps
CPU time 1.18 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 196004 kb
Host smart-e8bc6d11-baff-41ac-b268-ea35abd2870d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666994371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2666994371
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2681070538
Short name T477
Test name
Test status
Simulation time 25268324 ps
CPU time 0.72 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 195376 kb
Host smart-4bb15054-5855-421c-b014-394dc130326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681070538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2681070538
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2811108954
Short name T424
Test name
Test status
Simulation time 31983174 ps
CPU time 1.08 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 197864 kb
Host smart-29e625ce-994a-4c7e-9995-f37c7dd6560e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811108954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2811108954
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3241875571
Short name T117
Test name
Test status
Simulation time 72474696 ps
CPU time 3.21 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 197820 kb
Host smart-c8c805aa-f979-4f43-9de6-6ed146f96ae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241875571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3241875571
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3607004122
Short name T382
Test name
Test status
Simulation time 64893858 ps
CPU time 1.22 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196416 kb
Host smart-835669b3-409e-4de7-9956-35bb8dcb8759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607004122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3607004122
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1280197275
Short name T621
Test name
Test status
Simulation time 105536961 ps
CPU time 1.08 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:24 PM PDT 24
Peak memory 195416 kb
Host smart-2ccfcb66-3e4c-4229-b6c0-4a4c94c76296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280197275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1280197275
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2688356359
Short name T658
Test name
Test status
Simulation time 8146382104 ps
CPU time 58.61 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:25:33 PM PDT 24
Peak memory 198056 kb
Host smart-d9e41592-32df-4508-9b19-c8c197a57b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688356359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2688356359
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2077812562
Short name T389
Test name
Test status
Simulation time 253843455837 ps
CPU time 1539.59 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:50:11 PM PDT 24
Peak memory 198136 kb
Host smart-3d924813-f15e-42d7-9cdf-7fcd705472ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2077812562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2077812562
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1000340366
Short name T479
Test name
Test status
Simulation time 22095251 ps
CPU time 0.55 seconds
Started Apr 28 12:20:57 PM PDT 24
Finished Apr 28 12:20:58 PM PDT 24
Peak memory 193868 kb
Host smart-7e735fa5-f845-4bd2-84e1-9498a7773d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000340366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1000340366
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4025650079
Short name T230
Test name
Test status
Simulation time 115721855 ps
CPU time 0.79 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 195140 kb
Host smart-3d86abec-0576-4f27-9b7b-3f6e977e3a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025650079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4025650079
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2404466236
Short name T327
Test name
Test status
Simulation time 333081385 ps
CPU time 4.07 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:55 PM PDT 24
Peak memory 195728 kb
Host smart-ea712ab6-cbff-4aaa-a9af-93762be7f41d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404466236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2404466236
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1093155633
Short name T306
Test name
Test status
Simulation time 25689135 ps
CPU time 0.65 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 193948 kb
Host smart-2b175aac-d186-4387-9948-183100b2ead1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093155633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1093155633
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.809569193
Short name T379
Test name
Test status
Simulation time 35777551 ps
CPU time 1.06 seconds
Started Apr 28 12:21:49 PM PDT 24
Finished Apr 28 12:21:51 PM PDT 24
Peak memory 195952 kb
Host smart-656a725e-f1c9-43a5-8fb8-3a72d7f820d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809569193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.809569193
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3296677376
Short name T169
Test name
Test status
Simulation time 32217495 ps
CPU time 1.34 seconds
Started Apr 28 12:18:56 PM PDT 24
Finished Apr 28 12:18:58 PM PDT 24
Peak memory 196776 kb
Host smart-aeeb9252-4167-498a-8ea6-d44849ad5693
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296677376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3296677376
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1162644066
Short name T572
Test name
Test status
Simulation time 97637432 ps
CPU time 1.35 seconds
Started Apr 28 12:20:35 PM PDT 24
Finished Apr 28 12:20:37 PM PDT 24
Peak memory 196416 kb
Host smart-a8a01ddc-8ceb-4567-809c-d9a80ee1dc0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162644066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1162644066
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2403681271
Short name T485
Test name
Test status
Simulation time 189511021 ps
CPU time 1.12 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 195688 kb
Host smart-b8db92d2-5fa2-4ce2-830b-5c8ea3da370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403681271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2403681271
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3607686566
Short name T583
Test name
Test status
Simulation time 50678243 ps
CPU time 1.04 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 195640 kb
Host smart-310f3ef5-39fc-4b79-8624-730c05319b81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607686566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3607686566
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1607764092
Short name T43
Test name
Test status
Simulation time 345812188 ps
CPU time 5.4 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 196228 kb
Host smart-b720c4fc-510e-410f-be67-1e664ed75105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607764092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1607764092
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1574991832
Short name T40
Test name
Test status
Simulation time 69313636 ps
CPU time 0.9 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 213412 kb
Host smart-82864864-a71b-40f2-b127-9f6af965ba66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574991832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1574991832
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3287559752
Short name T521
Test name
Test status
Simulation time 169301304 ps
CPU time 1.12 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 195548 kb
Host smart-2d2638a5-5124-459a-ab03-0da55d68b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287559752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3287559752
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2096577146
Short name T318
Test name
Test status
Simulation time 54059096 ps
CPU time 0.81 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:46 PM PDT 24
Peak memory 195160 kb
Host smart-94f8c5da-0c6f-4a54-9af6-59f59265d780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096577146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2096577146
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3856298600
Short name T520
Test name
Test status
Simulation time 4759708135 ps
CPU time 106.05 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 198016 kb
Host smart-9247e6c3-3fd1-414d-abfe-218dd2150e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856298600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3856298600
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.625461064
Short name T431
Test name
Test status
Simulation time 31781918 ps
CPU time 0.57 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 193780 kb
Host smart-84800d1f-18cf-4adb-b8ea-e55494562ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625461064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.625461064
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3971694649
Short name T321
Test name
Test status
Simulation time 98724509 ps
CPU time 0.74 seconds
Started Apr 28 12:24:43 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 195176 kb
Host smart-9a0279b2-c758-495d-9239-580bd185f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971694649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3971694649
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2132247933
Short name T16
Test name
Test status
Simulation time 1162737955 ps
CPU time 17.43 seconds
Started Apr 28 12:24:07 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 197784 kb
Host smart-5051d24b-2a5d-4f30-9c9b-e625d0d5aa62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132247933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2132247933
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1794457063
Short name T628
Test name
Test status
Simulation time 81074189 ps
CPU time 0.74 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 196376 kb
Host smart-6c979e1e-10a8-45ba-b85b-37b39dfd5ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794457063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1794457063
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3709859735
Short name T647
Test name
Test status
Simulation time 129804652 ps
CPU time 1.13 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 195760 kb
Host smart-da6accbf-68f6-4d35-9476-06b7457e005c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709859735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3709859735
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2115396583
Short name T423
Test name
Test status
Simulation time 179944099 ps
CPU time 1.92 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 197708 kb
Host smart-24936967-6775-42db-a5cc-5a9d43e04cef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115396583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2115396583
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2399266578
Short name T203
Test name
Test status
Simulation time 175174121 ps
CPU time 1.4 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 195640 kb
Host smart-38782f17-a932-4309-8a42-411bb22d8f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399266578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2399266578
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4222596350
Short name T206
Test name
Test status
Simulation time 55975778 ps
CPU time 0.79 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196480 kb
Host smart-5fb07faa-ea69-4a54-b48b-4d65a41e1aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222596350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4222596350
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2602646710
Short name T546
Test name
Test status
Simulation time 140133965 ps
CPU time 0.97 seconds
Started Apr 28 12:24:41 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 196524 kb
Host smart-9dfca88c-6580-4f4a-9295-b7d822b81a7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602646710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2602646710
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2098678340
Short name T442
Test name
Test status
Simulation time 499311689 ps
CPU time 3.34 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 197876 kb
Host smart-2e9722e5-71ab-4b20-969f-c522308a264d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098678340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2098678340
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3754573590
Short name T31
Test name
Test status
Simulation time 230014586 ps
CPU time 1.27 seconds
Started Apr 28 12:24:24 PM PDT 24
Finished Apr 28 12:24:27 PM PDT 24
Peak memory 197888 kb
Host smart-3638cc99-cbbe-405f-a8a5-6619dba4dcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754573590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3754573590
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2210817444
Short name T696
Test name
Test status
Simulation time 508617680 ps
CPU time 0.86 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 195272 kb
Host smart-3f811dbb-4709-456b-ac26-798e9dad21ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210817444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2210817444
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1805709612
Short name T366
Test name
Test status
Simulation time 12329830660 ps
CPU time 148.5 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:27:01 PM PDT 24
Peak memory 198128 kb
Host smart-e4db7d55-2c28-4985-9d76-e15a3cd25d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805709612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1805709612
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.897087950
Short name T188
Test name
Test status
Simulation time 23185233 ps
CPU time 0.56 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 193852 kb
Host smart-75dac844-2c25-405d-ad67-f19b65926b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897087950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.897087950
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.980859157
Short name T141
Test name
Test status
Simulation time 40050796 ps
CPU time 0.79 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 195136 kb
Host smart-c2582d3a-58cc-4bc2-9065-4d1a5345e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980859157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.980859157
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1642416478
Short name T678
Test name
Test status
Simulation time 610924389 ps
CPU time 5.23 seconds
Started Apr 28 12:24:27 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 197052 kb
Host smart-3f533c13-e2e9-4a3b-8ec0-1341aebf1c9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642416478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1642416478
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1826715375
Short name T139
Test name
Test status
Simulation time 65122604 ps
CPU time 0.96 seconds
Started Apr 28 12:24:43 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 196440 kb
Host smart-9b2b111e-3037-410a-ba35-ca9c5b41347b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826715375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1826715375
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3820394807
Short name T353
Test name
Test status
Simulation time 72146924 ps
CPU time 0.66 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 195012 kb
Host smart-08f36b5c-cf04-4df5-a9c5-f8d4b68de5a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820394807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3820394807
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1410182622
Short name T191
Test name
Test status
Simulation time 66043309 ps
CPU time 2.58 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196408 kb
Host smart-1f9c4c20-0842-4160-bf70-62372c8c78d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410182622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1410182622
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3340549547
Short name T289
Test name
Test status
Simulation time 142556974 ps
CPU time 2.71 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 196440 kb
Host smart-e53d69cb-17d2-4078-b7a3-43985d0cda3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340549547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3340549547
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3000372305
Short name T178
Test name
Test status
Simulation time 28014630 ps
CPU time 0.72 seconds
Started Apr 28 12:24:43 PM PDT 24
Finished Apr 28 12:24:45 PM PDT 24
Peak memory 195944 kb
Host smart-2bc2ec75-aac2-4b3c-a4e2-cdda7459e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000372305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3000372305
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.639172615
Short name T293
Test name
Test status
Simulation time 31728319 ps
CPU time 0.82 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 197136 kb
Host smart-9ef64d1e-e9db-427c-932e-ac3876b9af4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639172615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.639172615
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1613782659
Short name T560
Test name
Test status
Simulation time 245514521 ps
CPU time 5.04 seconds
Started Apr 28 12:24:14 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 197760 kb
Host smart-0df8b3b3-3bc3-4e07-9d7e-75e6b3ba63dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613782659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1613782659
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4023827514
Short name T198
Test name
Test status
Simulation time 82920039 ps
CPU time 0.9 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 196392 kb
Host smart-a5fdd1af-beec-4cee-914e-6ade2c180c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023827514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4023827514
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1755664387
Short name T383
Test name
Test status
Simulation time 48426837 ps
CPU time 0.89 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:33 PM PDT 24
Peak memory 195472 kb
Host smart-6121cf99-728a-47b7-b870-e527738bef56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755664387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1755664387
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2323193260
Short name T152
Test name
Test status
Simulation time 9679545832 ps
CPU time 32.66 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:25:06 PM PDT 24
Peak memory 197972 kb
Host smart-aba12e46-6ffa-4c4a-a26b-4b6c79e3869a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323193260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2323193260
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.477405727
Short name T60
Test name
Test status
Simulation time 289651504199 ps
CPU time 2338.99 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 01:03:46 PM PDT 24
Peak memory 198180 kb
Host smart-7b6df782-11a2-4cd5-9899-5ce5c228c69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=477405727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.477405727
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3622898995
Short name T515
Test name
Test status
Simulation time 13282190 ps
CPU time 0.57 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 193820 kb
Host smart-518b8829-be88-4af6-9df2-8fc03524ea38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622898995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3622898995
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2773568953
Short name T529
Test name
Test status
Simulation time 96126618 ps
CPU time 0.69 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:39 PM PDT 24
Peak memory 195244 kb
Host smart-a244c818-e698-4d75-8794-d4428f6396df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773568953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2773568953
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3994470490
Short name T537
Test name
Test status
Simulation time 207578694 ps
CPU time 10.29 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 196772 kb
Host smart-4455054b-809c-437c-953a-0444a38d8b75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994470490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3994470490
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1564936219
Short name T627
Test name
Test status
Simulation time 119127692 ps
CPU time 0.68 seconds
Started Apr 28 12:24:34 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 194560 kb
Host smart-9c965d9a-da02-487b-bf00-c45245a1aa96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564936219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1564936219
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3211026634
Short name T124
Test name
Test status
Simulation time 49610143 ps
CPU time 0.69 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 194324 kb
Host smart-acf20d60-794f-4060-8b91-3a02097e8c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211026634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3211026634
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2797085192
Short name T634
Test name
Test status
Simulation time 95593191 ps
CPU time 3.45 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 197876 kb
Host smart-c25a207c-f032-4901-8fc0-22977e14e767
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797085192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2797085192
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3551075386
Short name T374
Test name
Test status
Simulation time 70440689 ps
CPU time 1.71 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 196752 kb
Host smart-5cd1c147-4408-40a0-8f99-d37905e39028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551075386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3551075386
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.851184615
Short name T693
Test name
Test status
Simulation time 68081827 ps
CPU time 0.71 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 195188 kb
Host smart-80dc2845-9801-4145-97a0-69fd4803229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851184615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.851184615
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1281647920
Short name T204
Test name
Test status
Simulation time 64283973 ps
CPU time 0.78 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 195464 kb
Host smart-027e51dd-6229-419e-a5e9-94aa362e9543
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281647920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1281647920
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_smoke.3271052256
Short name T670
Test name
Test status
Simulation time 20010810 ps
CPU time 0.71 seconds
Started Apr 28 12:24:42 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 195024 kb
Host smart-92e43419-05e6-437b-b8b0-cbf98b2da0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271052256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3271052256
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2215614131
Short name T136
Test name
Test status
Simulation time 71567746 ps
CPU time 1.31 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 196560 kb
Host smart-df960fea-4ca5-4eb2-99ca-eb6f414221c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215614131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2215614131
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4224552338
Short name T612
Test name
Test status
Simulation time 179347711929 ps
CPU time 187.97 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:27:44 PM PDT 24
Peak memory 198000 kb
Host smart-54c0678b-fc68-4597-991a-714f41c61e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224552338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4224552338
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3621071180
Short name T69
Test name
Test status
Simulation time 67420183077 ps
CPU time 444.08 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:31:57 PM PDT 24
Peak memory 198068 kb
Host smart-9e9ffd2b-389f-4b01-a02e-39f79a9bbd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3621071180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3621071180
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1193675320
Short name T531
Test name
Test status
Simulation time 22050147 ps
CPU time 0.53 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 194472 kb
Host smart-54136742-0f77-4dea-92af-a59c19e14145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193675320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1193675320
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2683135145
Short name T185
Test name
Test status
Simulation time 61827957 ps
CPU time 0.78 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 195828 kb
Host smart-20a97ba2-d0d5-410b-b7b8-49b3c34896af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683135145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2683135145
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1342482690
Short name T175
Test name
Test status
Simulation time 2291218088 ps
CPU time 16.15 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 197948 kb
Host smart-cff8703e-8e43-4047-8b92-17034cff0a0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342482690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1342482690
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3689337939
Short name T487
Test name
Test status
Simulation time 159146761 ps
CPU time 1.05 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 197840 kb
Host smart-e716b0d9-5d89-4d70-8b58-c755f8376ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689337939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3689337939
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4163258797
Short name T269
Test name
Test status
Simulation time 269385616 ps
CPU time 1.07 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 196584 kb
Host smart-9a377f71-dbb8-4a33-95dc-028581045cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163258797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4163258797
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1196611436
Short name T489
Test name
Test status
Simulation time 48669247 ps
CPU time 1.26 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 196396 kb
Host smart-6186b9d7-c3a1-4fea-a588-a2e5e2da2ba5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196611436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1196611436
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.21222031
Short name T330
Test name
Test status
Simulation time 259206307 ps
CPU time 2.77 seconds
Started Apr 28 12:25:15 PM PDT 24
Finished Apr 28 12:25:19 PM PDT 24
Peak memory 197984 kb
Host smart-e857efcc-1147-4817-9fec-f596c333e8c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.21222031
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2906678022
Short name T607
Test name
Test status
Simulation time 24314786 ps
CPU time 0.86 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196408 kb
Host smart-afbdc3c3-7302-4be3-9dad-2e7e0f27e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906678022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2906678022
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4159862517
Short name T144
Test name
Test status
Simulation time 65069711 ps
CPU time 1.21 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 197072 kb
Host smart-32372dfb-1d0c-4125-a4df-7577884da4a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159862517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4159862517
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1619207557
Short name T352
Test name
Test status
Simulation time 1611495419 ps
CPU time 4.92 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 197884 kb
Host smart-774f1015-18ae-44b3-9f5b-0e68328f7767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619207557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1619207557
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3508174034
Short name T339
Test name
Test status
Simulation time 144011907 ps
CPU time 1.06 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 195540 kb
Host smart-1ad9f0bb-1532-4278-a6fe-cd7b7ef9528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508174034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3508174034
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2418637230
Short name T342
Test name
Test status
Simulation time 157890319 ps
CPU time 1.03 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 195636 kb
Host smart-cb450bbd-d01a-44dc-b92c-6cb5103cd4c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418637230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2418637230
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1041771441
Short name T440
Test name
Test status
Simulation time 67949853660 ps
CPU time 174.85 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:27:41 PM PDT 24
Peak memory 198032 kb
Host smart-30a0cf8d-9ec7-4a44-8007-7b7b82148309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041771441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1041771441
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2213762769
Short name T694
Test name
Test status
Simulation time 25399381 ps
CPU time 0.55 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 194444 kb
Host smart-a1858b32-ce8a-4013-9cfc-15c19620dcd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213762769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2213762769
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2388300827
Short name T434
Test name
Test status
Simulation time 140563003 ps
CPU time 0.62 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 193932 kb
Host smart-dcaadac1-acb9-455b-8748-312a1f4a5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388300827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2388300827
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3533079660
Short name T274
Test name
Test status
Simulation time 706425822 ps
CPU time 23.51 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:25:10 PM PDT 24
Peak memory 196452 kb
Host smart-9910e41b-a1c0-47e5-a82c-2c283910989b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533079660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3533079660
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.457701380
Short name T700
Test name
Test status
Simulation time 165272068 ps
CPU time 0.81 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196636 kb
Host smart-aca48742-a2a5-47c2-852e-864aa859ed3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457701380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.457701380
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1873997770
Short name T569
Test name
Test status
Simulation time 194718094 ps
CPU time 1.4 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 197096 kb
Host smart-fcc7db45-cdc0-4015-96e5-4229dc3eb466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873997770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1873997770
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.869363872
Short name T146
Test name
Test status
Simulation time 135918650 ps
CPU time 1.49 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 197784 kb
Host smart-16d6c475-a64a-4450-b9d0-623583a46678
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869363872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.869363872
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2941659694
Short name T398
Test name
Test status
Simulation time 637818317 ps
CPU time 2.77 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 196880 kb
Host smart-10f84559-022b-4845-be1b-1bd71a7ea9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941659694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2941659694
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3680414205
Short name T478
Test name
Test status
Simulation time 64494199 ps
CPU time 1.36 seconds
Started Apr 28 12:24:34 PM PDT 24
Finished Apr 28 12:24:40 PM PDT 24
Peak memory 196796 kb
Host smart-c1f95160-a7ab-4d3b-953f-c97eb31d3922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680414205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3680414205
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.458531254
Short name T595
Test name
Test status
Simulation time 29637463 ps
CPU time 0.64 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 194232 kb
Host smart-254b33d2-67b8-4ffb-a8ed-393f59cf31c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458531254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.458531254
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.598859917
Short name T488
Test name
Test status
Simulation time 92592993 ps
CPU time 4.36 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 197868 kb
Host smart-113e30b7-a3e7-4293-b85a-c8eeaf783caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598859917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.598859917
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1761275444
Short name T360
Test name
Test status
Simulation time 131736687 ps
CPU time 0.74 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 195040 kb
Host smart-19eb4517-8a91-42b2-a374-f2783ac69d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761275444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1761275444
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3577148614
Short name T78
Test name
Test status
Simulation time 158115339 ps
CPU time 1.26 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196588 kb
Host smart-1468b38e-27b3-4e76-9d6c-eefb6d56f55a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577148614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3577148614
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4199057298
Short name T243
Test name
Test status
Simulation time 124398414862 ps
CPU time 183.85 seconds
Started Apr 28 12:24:42 PM PDT 24
Finished Apr 28 12:27:47 PM PDT 24
Peak memory 198056 kb
Host smart-fdda114e-0c65-49d2-b468-191643d034f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199057298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4199057298
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1884303830
Short name T73
Test name
Test status
Simulation time 26229417 ps
CPU time 0.55 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 193996 kb
Host smart-1eece980-95fe-4ff9-8b03-57d9e4297b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884303830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1884303830
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3212475281
Short name T212
Test name
Test status
Simulation time 15242659 ps
CPU time 0.61 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 193984 kb
Host smart-aca39444-ab71-47a7-aaba-4e6510f46be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212475281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3212475281
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4285325325
Short name T567
Test name
Test status
Simulation time 84825473 ps
CPU time 3.66 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 195652 kb
Host smart-abf1b327-9e89-4333-8c18-3f4fcc842065
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285325325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4285325325
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3408798555
Short name T319
Test name
Test status
Simulation time 78740668 ps
CPU time 0.95 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 197728 kb
Host smart-ca497db6-0829-4bb3-8b06-ea6bf8de855e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408798555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3408798555
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.529740264
Short name T705
Test name
Test status
Simulation time 1050281872 ps
CPU time 1.37 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 196632 kb
Host smart-1c269499-2324-454d-aeca-f0bf392d67d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529740264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.529740264
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.194612950
Short name T250
Test name
Test status
Simulation time 50499174 ps
CPU time 2.02 seconds
Started Apr 28 12:25:20 PM PDT 24
Finished Apr 28 12:25:23 PM PDT 24
Peak memory 197976 kb
Host smart-f119443c-061e-4ee1-9f6d-6fd526709532
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194612950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.194612950
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.731619195
Short name T408
Test name
Test status
Simulation time 272277625 ps
CPU time 1.85 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 197140 kb
Host smart-16c478de-434a-4553-b9bb-b743f898f8a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731619195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
731619195
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.784063471
Short name T695
Test name
Test status
Simulation time 212999955 ps
CPU time 1.18 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 196312 kb
Host smart-71a30dd5-16bc-4ca0-98a4-b2cd103076e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784063471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.784063471
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2020771126
Short name T74
Test name
Test status
Simulation time 268883357 ps
CPU time 1.21 seconds
Started Apr 28 12:24:36 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 196900 kb
Host smart-c8ba02a4-a72f-455d-a9f0-d9a9ac3482f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020771126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2020771126
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.240350187
Short name T337
Test name
Test status
Simulation time 149428302 ps
CPU time 2.28 seconds
Started Apr 28 12:25:10 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 197816 kb
Host smart-b9771cbe-11c3-4519-adb4-88b5e107db64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240350187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.240350187
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3628079124
Short name T53
Test name
Test status
Simulation time 49226217 ps
CPU time 1.01 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 196224 kb
Host smart-1f3d4b6d-511b-46dd-ba2f-90fd8fed44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628079124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3628079124
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1561817733
Short name T292
Test name
Test status
Simulation time 335665928 ps
CPU time 1.36 seconds
Started Apr 28 12:24:41 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 197876 kb
Host smart-24d3effa-4eeb-46d6-8fa0-ec7d3e1f1b0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561817733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1561817733
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4259163902
Short name T17
Test name
Test status
Simulation time 33494295685 ps
CPU time 79.22 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:26:11 PM PDT 24
Peak memory 198032 kb
Host smart-f2579ea0-2ebf-4995-a960-15b804f91d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259163902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4259163902
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1237029676
Short name T272
Test name
Test status
Simulation time 44348660 ps
CPU time 0.52 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 192640 kb
Host smart-5a623dd5-7bb7-40aa-9627-d762886e2936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237029676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1237029676
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2882544614
Short name T197
Test name
Test status
Simulation time 41804649 ps
CPU time 0.86 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 195752 kb
Host smart-4b09a573-e414-4505-8a5e-3380d69b6e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882544614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2882544614
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3063347935
Short name T684
Test name
Test status
Simulation time 666643793 ps
CPU time 13.05 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 196080 kb
Host smart-2853f99d-870a-41ee-8a29-73e234576d18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063347935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3063347935
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1366426376
Short name T582
Test name
Test status
Simulation time 69817479 ps
CPU time 0.9 seconds
Started Apr 28 12:25:00 PM PDT 24
Finished Apr 28 12:25:02 PM PDT 24
Peak memory 197004 kb
Host smart-cb62f0b4-c490-4e90-823a-3c75a34dc83c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366426376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1366426376
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3864107248
Short name T246
Test name
Test status
Simulation time 50323287 ps
CPU time 0.89 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 196640 kb
Host smart-cce36c7e-5347-4aca-9557-3b1d0a33d071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864107248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3864107248
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1587512358
Short name T238
Test name
Test status
Simulation time 70454489 ps
CPU time 2.61 seconds
Started Apr 28 12:25:00 PM PDT 24
Finished Apr 28 12:25:04 PM PDT 24
Peak memory 197884 kb
Host smart-d9168885-298d-4289-9701-ed3e591b4254
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587512358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1587512358
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2011450238
Short name T653
Test name
Test status
Simulation time 457576814 ps
CPU time 2.71 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 197844 kb
Host smart-a6faa6d4-0f94-44a9-909e-048d14b9142f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011450238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2011450238
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3880107708
Short name T673
Test name
Test status
Simulation time 43146368 ps
CPU time 0.72 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 195416 kb
Host smart-3a65deae-9dac-42e0-b898-fb914475af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880107708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3880107708
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3614551402
Short name T677
Test name
Test status
Simulation time 99907805 ps
CPU time 1.01 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 195876 kb
Host smart-7744e3b2-35bc-49d1-8acb-aa68e863ed95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614551402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3614551402
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.802318538
Short name T380
Test name
Test status
Simulation time 200716116 ps
CPU time 4.22 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:45 PM PDT 24
Peak memory 197792 kb
Host smart-82819e8c-a033-4627-88f7-e9defc8db9df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802318538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.802318538
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.581000820
Short name T134
Test name
Test status
Simulation time 96245183 ps
CPU time 1.19 seconds
Started Apr 28 12:24:39 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 196776 kb
Host smart-5abbfc6e-878c-495f-abb6-374514d05566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581000820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.581000820
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.592614073
Short name T386
Test name
Test status
Simulation time 42376764 ps
CPU time 0.86 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:03 PM PDT 24
Peak memory 195836 kb
Host smart-2b9299d0-599b-47e0-aed3-cdc5be04a9c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592614073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.592614073
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2423004831
Short name T563
Test name
Test status
Simulation time 29501441191 ps
CPU time 185.87 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:28:02 PM PDT 24
Peak memory 198060 kb
Host smart-fb7494b4-d4bc-4e6a-a10a-f6f81f8d3607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423004831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2423004831
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3859570800
Short name T393
Test name
Test status
Simulation time 27057932 ps
CPU time 0.57 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 194488 kb
Host smart-f572ce27-ad37-4c26-a135-ce9758dae7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859570800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3859570800
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4004711669
Short name T668
Test name
Test status
Simulation time 25664498 ps
CPU time 0.72 seconds
Started Apr 28 12:24:32 PM PDT 24
Finished Apr 28 12:24:36 PM PDT 24
Peak memory 194100 kb
Host smart-597cc830-fb36-42a1-bd5d-6443bb9b6c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004711669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4004711669
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1678516155
Short name T459
Test name
Test status
Simulation time 1022102062 ps
CPU time 13.26 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 197856 kb
Host smart-50a4a017-dc88-424c-b20c-10cf6cdea219
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678516155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1678516155
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.920175280
Short name T626
Test name
Test status
Simulation time 34384118 ps
CPU time 0.69 seconds
Started Apr 28 12:24:33 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 195356 kb
Host smart-0eefa246-8b7d-46a2-8210-60ff874586b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920175280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.920175280
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2771155928
Short name T674
Test name
Test status
Simulation time 1187948352 ps
CPU time 1.3 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 195664 kb
Host smart-8e77ced0-493a-4464-bb41-1a748c1bd554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771155928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2771155928
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2802914272
Short name T310
Test name
Test status
Simulation time 81754134 ps
CPU time 3.09 seconds
Started Apr 28 12:24:53 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 197912 kb
Host smart-5b42f127-0a51-47cc-9faf-5f133d6301db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802914272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2802914272
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.415263093
Short name T421
Test name
Test status
Simulation time 771785071 ps
CPU time 3.2 seconds
Started Apr 28 12:24:35 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 195632 kb
Host smart-4e245584-b382-4eb2-b4eb-2f555f203020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415263093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
415263093
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3073470859
Short name T71
Test name
Test status
Simulation time 234753497 ps
CPU time 1.1 seconds
Started Apr 28 12:25:21 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 195956 kb
Host smart-bb7a7d01-fcff-4530-ad3c-2961e0e3121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073470859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3073470859
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.64870942
Short name T519
Test name
Test status
Simulation time 290577544 ps
CPU time 1.32 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 196360 kb
Host smart-fabddb88-bfe4-4412-a458-ea117af4924f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64870942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup_
pulldown.64870942
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.402386986
Short name T1
Test name
Test status
Simulation time 1526510658 ps
CPU time 4.37 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 197756 kb
Host smart-38506898-9383-4175-baac-058aa77b288d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402386986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.402386986
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.613660217
Short name T300
Test name
Test status
Simulation time 987159695 ps
CPU time 1.04 seconds
Started Apr 28 12:25:22 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 196220 kb
Host smart-6de79942-5163-4c32-a5e2-43dd5743cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613660217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.613660217
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3074009
Short name T154
Test name
Test status
Simulation time 139403159 ps
CPU time 1.1 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 195736 kb
Host smart-9187e872-830f-42d9-b356-40b62f0c2275
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3074009
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1994952732
Short name T441
Test name
Test status
Simulation time 78720867233 ps
CPU time 201.42 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:28:10 PM PDT 24
Peak memory 198060 kb
Host smart-add34ed2-33db-49f3-bb44-ba6170d2012a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994952732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1994952732
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2747403314
Short name T385
Test name
Test status
Simulation time 56638226152 ps
CPU time 1072.54 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:42:32 PM PDT 24
Peak memory 198048 kb
Host smart-3ab1feac-d9e7-424a-8726-b865ca2233e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2747403314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2747403314
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3293655406
Short name T325
Test name
Test status
Simulation time 33940443 ps
CPU time 0.53 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 193840 kb
Host smart-6da0955f-d5d3-4c1a-9f0b-a9c3d0303077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293655406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3293655406
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2237201026
Short name T135
Test name
Test status
Simulation time 14970690 ps
CPU time 0.58 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 193736 kb
Host smart-47fb0a23-dfb2-4817-a214-25d10bf103bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237201026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2237201026
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3229556607
Short name T255
Test name
Test status
Simulation time 929134186 ps
CPU time 4.92 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 196360 kb
Host smart-3c290b19-5aeb-4e91-ae53-4c86add4d0e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229556607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3229556607
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2753283821
Short name T20
Test name
Test status
Simulation time 50749526 ps
CPU time 0.83 seconds
Started Apr 28 12:24:54 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 195960 kb
Host smart-ee35919c-3fec-49af-ba8b-e3ee768c6e49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753283821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2753283821
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2944924509
Short name T216
Test name
Test status
Simulation time 40176186 ps
CPU time 1.08 seconds
Started Apr 28 12:24:41 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 196708 kb
Host smart-710f1452-d509-4148-90fc-c03a1e6fe817
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944924509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2944924509
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.952480922
Short name T699
Test name
Test status
Simulation time 36932993 ps
CPU time 1.39 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 196660 kb
Host smart-e660146d-934a-458d-80b9-a71cfcd5b6e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952480922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.952480922
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.878840529
Short name T367
Test name
Test status
Simulation time 107471627 ps
CPU time 2.34 seconds
Started Apr 28 12:24:42 PM PDT 24
Finished Apr 28 12:24:45 PM PDT 24
Peak memory 195676 kb
Host smart-cb6ce97d-5c66-470d-be26-37b0a8621046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878840529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
878840529
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2256206663
Short name T574
Test name
Test status
Simulation time 25792546 ps
CPU time 0.8 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 195976 kb
Host smart-354b207f-bfb2-47bb-95f6-caf7e4b2da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256206663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2256206663
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.115503747
Short name T153
Test name
Test status
Simulation time 35214623 ps
CPU time 0.84 seconds
Started Apr 28 12:25:03 PM PDT 24
Finished Apr 28 12:25:05 PM PDT 24
Peak memory 195588 kb
Host smart-eb0f5b5d-daf8-431b-aa98-51b901f6272c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115503747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.115503747
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3709977988
Short name T173
Test name
Test status
Simulation time 65649034 ps
CPU time 1.5 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 197864 kb
Host smart-a5a41c1b-b58a-4355-9e80-9531118ad910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709977988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3709977988
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3545202527
Short name T688
Test name
Test status
Simulation time 39430175 ps
CPU time 0.96 seconds
Started Apr 28 12:24:53 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 195644 kb
Host smart-2a4ac31c-1cfc-4d5d-b207-75114f5bd756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545202527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3545202527
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2652629855
Short name T109
Test name
Test status
Simulation time 68411973 ps
CPU time 1.11 seconds
Started Apr 28 12:24:40 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 195680 kb
Host smart-a0c3af14-a6c7-4812-ad7f-0568a9f98729
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652629855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2652629855
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4043630999
Short name T686
Test name
Test status
Simulation time 77866776720 ps
CPU time 215.44 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:28:54 PM PDT 24
Peak memory 198052 kb
Host smart-462c0250-4d9a-4a16-94e9-20f6d0afdfb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043630999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4043630999
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2557713753
Short name T62
Test name
Test status
Simulation time 117574640422 ps
CPU time 1471.4 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:49:18 PM PDT 24
Peak memory 198052 kb
Host smart-7692499d-30a6-4b6d-bd1e-563626a40767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2557713753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2557713753
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1151351578
Short name T23
Test name
Test status
Simulation time 30150158 ps
CPU time 0.56 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 194004 kb
Host smart-5f7cd3c0-4171-47ef-8e14-21e5026044f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151351578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1151351578
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3833012978
Short name T168
Test name
Test status
Simulation time 25050838 ps
CPU time 0.83 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 196328 kb
Host smart-31b6e85b-7fce-4e95-b82e-f07bb7df98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833012978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3833012978
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3040573601
Short name T541
Test name
Test status
Simulation time 299225023 ps
CPU time 14.23 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 196616 kb
Host smart-e7a31971-3916-4a58-bdd4-57ca696ed543
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040573601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3040573601
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.314297346
Short name T5
Test name
Test status
Simulation time 387331264 ps
CPU time 1.06 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 196388 kb
Host smart-88b75094-e6de-421b-8f9f-ad1fabe5a550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314297346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.314297346
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3875913477
Short name T285
Test name
Test status
Simulation time 173794718 ps
CPU time 1.32 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 197860 kb
Host smart-ef3f08af-0c15-4f92-bec0-6116bafb1412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875913477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3875913477
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1412619822
Short name T698
Test name
Test status
Simulation time 399077754 ps
CPU time 3.3 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 197940 kb
Host smart-2a5450cb-c11c-4831-af9f-88335b834444
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412619822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1412619822
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2696999558
Short name T443
Test name
Test status
Simulation time 80441585 ps
CPU time 1.73 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 195904 kb
Host smart-8d6ded16-e710-4ba7-8263-374c19b877e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696999558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2696999558
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.487856909
Short name T270
Test name
Test status
Simulation time 118773437 ps
CPU time 0.95 seconds
Started Apr 28 12:24:38 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 195856 kb
Host smart-6a40e107-0809-4a11-ab88-c304c0ea4809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487856909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.487856909
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3821923770
Short name T372
Test name
Test status
Simulation time 86465747 ps
CPU time 0.68 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 195892 kb
Host smart-6fed6730-c4fd-49a8-b279-2f1259e08e16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821923770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3821923770
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1707607964
Short name T235
Test name
Test status
Simulation time 1446416013 ps
CPU time 3.04 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 197848 kb
Host smart-42a9d2fa-53d2-4e8c-a399-8a1ecb376ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707607964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1707607964
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3750763202
Short name T317
Test name
Test status
Simulation time 364654920 ps
CPU time 1.37 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 196560 kb
Host smart-005a7b82-ba16-4cf7-bfb4-babb605df1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750763202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3750763202
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3031610032
Short name T682
Test name
Test status
Simulation time 80817239 ps
CPU time 1.39 seconds
Started Apr 28 12:24:53 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 197912 kb
Host smart-304cbb85-13a1-4090-a32d-0debe6a9bb94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031610032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3031610032
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2052863604
Short name T536
Test name
Test status
Simulation time 51571642607 ps
CPU time 33.8 seconds
Started Apr 28 12:24:41 PM PDT 24
Finished Apr 28 12:25:16 PM PDT 24
Peak memory 198084 kb
Host smart-b66ec0c1-f46b-41e3-b488-05b59028fc27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052863604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2052863604
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4217087383
Short name T34
Test name
Test status
Simulation time 76003195689 ps
CPU time 1985.81 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:57:55 PM PDT 24
Peak memory 198172 kb
Host smart-83d9e311-6690-4cba-ab35-fcefda1d8556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4217087383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4217087383
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3960298272
Short name T649
Test name
Test status
Simulation time 21365669 ps
CPU time 0.58 seconds
Started Apr 28 12:24:04 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 192708 kb
Host smart-f7f7c55e-a47e-4267-b51c-94738ee07581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960298272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3960298272
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3126678872
Short name T414
Test name
Test status
Simulation time 44654111 ps
CPU time 0.72 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 195132 kb
Host smart-d7c06d47-5e1e-46f5-91e1-15e848e3d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126678872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3126678872
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1337574039
Short name T331
Test name
Test status
Simulation time 760909126 ps
CPU time 6 seconds
Started Apr 28 12:23:41 PM PDT 24
Finished Apr 28 12:23:49 PM PDT 24
Peak memory 197808 kb
Host smart-c67d17d7-4097-42fd-b2ca-7a2653bc1424
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337574039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1337574039
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3891156130
Short name T462
Test name
Test status
Simulation time 45537762 ps
CPU time 0.7 seconds
Started Apr 28 12:23:47 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 195044 kb
Host smart-fdc34b69-3647-493f-a088-e89363f92f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891156130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3891156130
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3329806901
Short name T388
Test name
Test status
Simulation time 59111016 ps
CPU time 0.97 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 195932 kb
Host smart-9b96ea59-869a-47a1-9e49-f679f5f79614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329806901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3329806901
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.498471384
Short name T542
Test name
Test status
Simulation time 46340457 ps
CPU time 1.1 seconds
Started Apr 28 12:23:30 PM PDT 24
Finished Apr 28 12:23:32 PM PDT 24
Peak memory 197476 kb
Host smart-852d9637-ceef-42bd-88fd-c774c955a538
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498471384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.498471384
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.420158666
Short name T486
Test name
Test status
Simulation time 116568960 ps
CPU time 3.14 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:52 PM PDT 24
Peak memory 197796 kb
Host smart-131fd740-24d1-46ef-b6c6-a74654c8129c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420158666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.420158666
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.40067823
Short name T183
Test name
Test status
Simulation time 60289210 ps
CPU time 1.09 seconds
Started Apr 28 12:24:05 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 196724 kb
Host smart-998eeb4a-233a-426a-91b7-1259cc7c9ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40067823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.40067823
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.323421036
Short name T338
Test name
Test status
Simulation time 28108945 ps
CPU time 0.99 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 195336 kb
Host smart-9279e01a-0774-46e4-973b-5eff5a005ab7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323421036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.323421036
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4020171191
Short name T672
Test name
Test status
Simulation time 95278730 ps
CPU time 4.68 seconds
Started Apr 28 12:23:41 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 197888 kb
Host smart-fe33395e-d50f-46ee-971f-cfe69458bb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020171191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4020171191
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.900366850
Short name T328
Test name
Test status
Simulation time 48760390 ps
CPU time 1.16 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 196028 kb
Host smart-794b42d6-dcb5-46f3-8bb4-a072804ca892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900366850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.900366850
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1822726878
Short name T305
Test name
Test status
Simulation time 58735360 ps
CPU time 0.94 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 195588 kb
Host smart-d6fa92b4-9ba4-42ca-9d76-ebb7ded680b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822726878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1822726878
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1913800260
Short name T373
Test name
Test status
Simulation time 5895517399 ps
CPU time 147.66 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:26:13 PM PDT 24
Peak memory 198080 kb
Host smart-37cd6a53-241d-41a0-876f-a1cc16745676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913800260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1913800260
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.361006066
Short name T219
Test name
Test status
Simulation time 32281802 ps
CPU time 0.54 seconds
Started Apr 28 12:24:59 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 193764 kb
Host smart-ac43e08b-eefd-4d24-85dc-0742e74615d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361006066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.361006066
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1079930457
Short name T493
Test name
Test status
Simulation time 37431832 ps
CPU time 0.69 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 195104 kb
Host smart-8e4aa513-7bac-4af9-aa71-761b066fb16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079930457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1079930457
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2559169479
Short name T669
Test name
Test status
Simulation time 1612779679 ps
CPU time 20.37 seconds
Started Apr 28 12:24:56 PM PDT 24
Finished Apr 28 12:25:18 PM PDT 24
Peak memory 197848 kb
Host smart-daa8a0a4-1450-44b0-91ca-f7723d06a032
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559169479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2559169479
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2640503837
Short name T177
Test name
Test status
Simulation time 51981140 ps
CPU time 0.84 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:13 PM PDT 24
Peak memory 195852 kb
Host smart-f47d4098-2301-4ae7-8b02-596edc24e3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640503837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2640503837
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1448916938
Short name T41
Test name
Test status
Simulation time 34864655 ps
CPU time 0.92 seconds
Started Apr 28 12:24:54 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 196412 kb
Host smart-40ebe326-3f49-4b49-a6ef-894884fa9d23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448916938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1448916938
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1852377131
Short name T547
Test name
Test status
Simulation time 78950235 ps
CPU time 3.01 seconds
Started Apr 28 12:25:00 PM PDT 24
Finished Apr 28 12:25:04 PM PDT 24
Peak memory 197812 kb
Host smart-4c8d178a-c22e-4256-b5bf-2fd7144b0686
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852377131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1852377131
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1606722840
Short name T196
Test name
Test status
Simulation time 460079035 ps
CPU time 2.6 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 196732 kb
Host smart-bb210a1e-b776-4da3-abc6-5dfa764ec804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606722840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1606722840
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2008364160
Short name T257
Test name
Test status
Simulation time 121739556 ps
CPU time 1.23 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 196840 kb
Host smart-519fcc80-6955-4811-89d1-4b180424274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008364160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2008364160
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.782548766
Short name T113
Test name
Test status
Simulation time 120947580 ps
CPU time 1.06 seconds
Started Apr 28 12:25:29 PM PDT 24
Finished Apr 28 12:25:30 PM PDT 24
Peak memory 195912 kb
Host smart-cbe54229-8433-46cb-9b2c-372ea36f1504
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782548766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.782548766
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.927429690
Short name T314
Test name
Test status
Simulation time 1573289382 ps
CPU time 4.78 seconds
Started Apr 28 12:25:08 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 197848 kb
Host smart-519786cb-45cf-4b75-9ce6-29e83ce2542e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927429690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.927429690
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2931529459
Short name T714
Test name
Test status
Simulation time 39869052 ps
CPU time 1.05 seconds
Started Apr 28 12:24:46 PM PDT 24
Finished Apr 28 12:24:48 PM PDT 24
Peak memory 196312 kb
Host smart-9b5d35e4-360f-4161-ab0a-6640f9f78770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931529459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2931529459
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3602266875
Short name T137
Test name
Test status
Simulation time 73255894 ps
CPU time 1.19 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 197788 kb
Host smart-dc1093b3-f290-466f-98c5-7237f54e314b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602266875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3602266875
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3914092697
Short name T534
Test name
Test status
Simulation time 5895996314 ps
CPU time 79.57 seconds
Started Apr 28 12:25:18 PM PDT 24
Finished Apr 28 12:26:39 PM PDT 24
Peak memory 197948 kb
Host smart-90875a85-5fe6-42ac-b766-8bfde30dab6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914092697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3914092697
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.716717420
Short name T344
Test name
Test status
Simulation time 35395846 ps
CPU time 0.62 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 194536 kb
Host smart-92e15748-714f-46af-b06a-337ddcce30af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716717420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.716717420
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1598273303
Short name T354
Test name
Test status
Simulation time 31370627 ps
CPU time 0.92 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 195808 kb
Host smart-96a8b7d5-dee9-4760-a8a1-51ae4066b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598273303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1598273303
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3940169882
Short name T497
Test name
Test status
Simulation time 1058632816 ps
CPU time 16.43 seconds
Started Apr 28 12:25:22 PM PDT 24
Finished Apr 28 12:25:40 PM PDT 24
Peak memory 196064 kb
Host smart-92fd1a98-9904-405f-a985-2a1357bfaddc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940169882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3940169882
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3542520467
Short name T482
Test name
Test status
Simulation time 93478488 ps
CPU time 1.03 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:25:20 PM PDT 24
Peak memory 197852 kb
Host smart-08f9906a-7580-473d-95fa-38238a980e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542520467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3542520467
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.938281229
Short name T377
Test name
Test status
Simulation time 64103327 ps
CPU time 1.04 seconds
Started Apr 28 12:25:15 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 195640 kb
Host smart-26f93aa0-4881-4efa-a43c-9891a8699e9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938281229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.938281229
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1214652959
Short name T370
Test name
Test status
Simulation time 62590598 ps
CPU time 2.33 seconds
Started Apr 28 12:25:23 PM PDT 24
Finished Apr 28 12:25:26 PM PDT 24
Peak memory 197868 kb
Host smart-7daa7e6e-84e1-45bf-9798-6e838d664618
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214652959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1214652959
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1659766862
Short name T324
Test name
Test status
Simulation time 129101176 ps
CPU time 1.01 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:25:20 PM PDT 24
Peak memory 195448 kb
Host smart-4d3bd743-d0de-4b50-a1e7-afcf0c64b30e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659766862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1659766862
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4202653931
Short name T625
Test name
Test status
Simulation time 524617518 ps
CPU time 0.98 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:03 PM PDT 24
Peak memory 195804 kb
Host smart-b9cc07a4-c693-49f3-86cb-27a98ec97b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202653931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4202653931
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.4105656723
Short name T268
Test name
Test status
Simulation time 57279785 ps
CPU time 1.03 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195896 kb
Host smart-f2301926-6d6b-4e1a-978b-e32d6443c60b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105656723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.4105656723
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2193400739
Short name T162
Test name
Test status
Simulation time 317598092 ps
CPU time 5.03 seconds
Started Apr 28 12:25:22 PM PDT 24
Finished Apr 28 12:25:28 PM PDT 24
Peak memory 197792 kb
Host smart-e332c258-8669-4609-9e55-2a93cc39bee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193400739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2193400739
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4091160765
Short name T241
Test name
Test status
Simulation time 119122860 ps
CPU time 0.91 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 196100 kb
Host smart-bcbca5c1-f6a4-4046-93ac-27d61e3fb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091160765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4091160765
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.588848717
Short name T179
Test name
Test status
Simulation time 226585505 ps
CPU time 1.19 seconds
Started Apr 28 12:24:37 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 196280 kb
Host smart-2562686d-4b1d-4f00-8421-adfe96212e7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588848717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.588848717
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.139593984
Short name T263
Test name
Test status
Simulation time 12610712095 ps
CPU time 174.42 seconds
Started Apr 28 12:25:22 PM PDT 24
Finished Apr 28 12:28:18 PM PDT 24
Peak memory 197868 kb
Host smart-8d21979c-603b-447f-b3f7-6c4142c579a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139593984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.139593984
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1726005352
Short name T61
Test name
Test status
Simulation time 1071699896309 ps
CPU time 1109.45 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 206284 kb
Host smart-3232f267-9a20-43ab-9e9d-b7c8d72d54c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1726005352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1726005352
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1235137249
Short name T312
Test name
Test status
Simulation time 107500706 ps
CPU time 0.55 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 193796 kb
Host smart-4bb1c0c1-37df-4adc-a685-d05c9ecdd63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235137249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1235137249
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.768261499
Short name T271
Test name
Test status
Simulation time 76922612 ps
CPU time 0.7 seconds
Started Apr 28 12:25:28 PM PDT 24
Finished Apr 28 12:25:29 PM PDT 24
Peak memory 195008 kb
Host smart-e0176816-c551-44a3-ba87-cd7998d7eeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768261499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.768261499
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1882154368
Short name T356
Test name
Test status
Simulation time 661816279 ps
CPU time 21.7 seconds
Started Apr 28 12:25:04 PM PDT 24
Finished Apr 28 12:25:27 PM PDT 24
Peak memory 196516 kb
Host smart-18dc452d-49ce-4a33-a2a0-da40590687cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882154368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1882154368
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1180938867
Short name T231
Test name
Test status
Simulation time 27299240 ps
CPU time 0.6 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:03 PM PDT 24
Peak memory 194380 kb
Host smart-55b1053f-a284-41d8-b770-1cee16400d70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180938867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1180938867
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2179342483
Short name T412
Test name
Test status
Simulation time 176293360 ps
CPU time 0.9 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:05 PM PDT 24
Peak memory 197088 kb
Host smart-a0c23e45-8088-47e3-ba05-0de9a0f2763e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179342483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2179342483
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3356884081
Short name T712
Test name
Test status
Simulation time 117109737 ps
CPU time 2.11 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 197816 kb
Host smart-abcc5d54-7cd5-4ce2-8310-cf674d9e48a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356884081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3356884081
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3279914589
Short name T438
Test name
Test status
Simulation time 86109242 ps
CPU time 2.54 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 197876 kb
Host smart-396b3ff4-4032-48dc-812b-75313e439f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279914589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3279914589
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.852929876
Short name T202
Test name
Test status
Simulation time 25842037 ps
CPU time 0.91 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:03 PM PDT 24
Peak memory 196432 kb
Host smart-f6994566-ab01-4f80-b924-22ec972ab518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852929876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.852929876
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3001007687
Short name T11
Test name
Test status
Simulation time 35478902 ps
CPU time 0.63 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 194872 kb
Host smart-9fcce542-3e9a-4940-9660-70422ae68911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001007687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3001007687
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2536937966
Short name T7
Test name
Test status
Simulation time 254656587 ps
CPU time 3.04 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 197712 kb
Host smart-77f41336-5a99-426f-9977-ddf6841407c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536937966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2536937966
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2487168958
Short name T557
Test name
Test status
Simulation time 58617513 ps
CPU time 1.13 seconds
Started Apr 28 12:25:06 PM PDT 24
Finished Apr 28 12:25:09 PM PDT 24
Peak memory 195364 kb
Host smart-44a805af-9b4e-43b4-a200-7a60e74eb278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487168958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2487168958
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4125532392
Short name T397
Test name
Test status
Simulation time 255616028 ps
CPU time 1.16 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195628 kb
Host smart-7aef3ed9-ab87-4955-b7b2-9750ba5dfb39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125532392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4125532392
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1496251321
Short name T661
Test name
Test status
Simulation time 3026526029 ps
CPU time 35.75 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:45 PM PDT 24
Peak memory 198008 kb
Host smart-b7b388c2-5c43-47dc-9778-98318dcfc15f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496251321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1496251321
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.103577864
Short name T336
Test name
Test status
Simulation time 86836395048 ps
CPU time 2178.79 seconds
Started Apr 28 12:25:02 PM PDT 24
Finished Apr 28 01:01:22 PM PDT 24
Peak memory 198084 kb
Host smart-180b781c-e6b0-40d5-92e4-46f0078c7df3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=103577864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.103577864
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1129073188
Short name T426
Test name
Test status
Simulation time 84927915 ps
CPU time 0.55 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 194420 kb
Host smart-17f43697-731d-43ac-816f-be09e031b549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129073188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1129073188
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.610888986
Short name T463
Test name
Test status
Simulation time 138078159 ps
CPU time 0.75 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 195072 kb
Host smart-a0fb1a1f-f672-4b38-9330-aecf49f71f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610888986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.610888986
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.653131522
Short name T123
Test name
Test status
Simulation time 2362659680 ps
CPU time 16.58 seconds
Started Apr 28 12:25:04 PM PDT 24
Finished Apr 28 12:25:21 PM PDT 24
Peak memory 196964 kb
Host smart-757c845b-1ec2-4145-b74a-03595a570fa1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653131522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.653131522
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2439304712
Short name T240
Test name
Test status
Simulation time 169075125 ps
CPU time 0.82 seconds
Started Apr 28 12:25:19 PM PDT 24
Finished Apr 28 12:25:21 PM PDT 24
Peak memory 195772 kb
Host smart-4ea5b33c-b326-4b36-bc01-900b52036109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439304712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2439304712
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2094769810
Short name T444
Test name
Test status
Simulation time 61147382 ps
CPU time 0.96 seconds
Started Apr 28 12:25:09 PM PDT 24
Finished Apr 28 12:25:11 PM PDT 24
Peak memory 195892 kb
Host smart-9c6ae948-2241-443f-9877-2c281b1278c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094769810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2094769810
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3974651106
Short name T685
Test name
Test status
Simulation time 159744455 ps
CPU time 1.77 seconds
Started Apr 28 12:25:18 PM PDT 24
Finished Apr 28 12:25:21 PM PDT 24
Peak memory 198004 kb
Host smart-bd048682-7f4d-4d7e-8d04-d961818af7bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974651106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3974651106
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2427899599
Short name T384
Test name
Test status
Simulation time 65355418 ps
CPU time 1.71 seconds
Started Apr 28 12:25:03 PM PDT 24
Finished Apr 28 12:25:05 PM PDT 24
Peak memory 195848 kb
Host smart-3f1a3d61-b78b-4314-9c1d-578448a1aeb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427899599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2427899599
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2966413438
Short name T200
Test name
Test status
Simulation time 212008795 ps
CPU time 1.14 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 196808 kb
Host smart-fc540b14-c53e-40bd-ac3f-b3090a81c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966413438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2966413438
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3570145106
Short name T514
Test name
Test status
Simulation time 213797131 ps
CPU time 1.18 seconds
Started Apr 28 12:25:02 PM PDT 24
Finished Apr 28 12:25:04 PM PDT 24
Peak memory 195636 kb
Host smart-684ff007-cf70-482f-9077-e63c6f01eed7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570145106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3570145106
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1528270981
Short name T436
Test name
Test status
Simulation time 573594798 ps
CPU time 5.91 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:25:02 PM PDT 24
Peak memory 197868 kb
Host smart-56db5cad-06a6-4ea2-b4fd-3c444ce162be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528270981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1528270981
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.691902530
Short name T679
Test name
Test status
Simulation time 24656296 ps
CPU time 0.76 seconds
Started Apr 28 12:25:16 PM PDT 24
Finished Apr 28 12:25:19 PM PDT 24
Peak memory 195808 kb
Host smart-f77ab697-bb45-4cd2-acda-d235302ed71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691902530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.691902530
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2710754482
Short name T252
Test name
Test status
Simulation time 61333876 ps
CPU time 0.91 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 195484 kb
Host smart-6038ad33-2fce-4c9e-b8d9-3883fe8fc717
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710754482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2710754482
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.606332998
Short name T448
Test name
Test status
Simulation time 5029921861 ps
CPU time 138.34 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:27:08 PM PDT 24
Peak memory 198004 kb
Host smart-d843602a-2aa5-4c8e-92e4-c5d1ab7a6efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606332998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.606332998
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.516828699
Short name T387
Test name
Test status
Simulation time 51433666795 ps
CPU time 621.38 seconds
Started Apr 28 12:25:08 PM PDT 24
Finished Apr 28 12:35:31 PM PDT 24
Peak memory 198112 kb
Host smart-0afb9745-cc44-4865-83dd-ebe0d586a0b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=516828699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.516828699
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3436526975
Short name T375
Test name
Test status
Simulation time 30386084 ps
CPU time 0.54 seconds
Started Apr 28 12:25:13 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 193808 kb
Host smart-d80a909e-aaca-43a7-934e-8845bc91c078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436526975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3436526975
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4090035291
Short name T236
Test name
Test status
Simulation time 55515654 ps
CPU time 0.65 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 193964 kb
Host smart-4e09b295-43f6-4e2e-8565-8e2d0bafbc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090035291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4090035291
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2682929443
Short name T218
Test name
Test status
Simulation time 1416749826 ps
CPU time 17.64 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:25:08 PM PDT 24
Peak memory 196772 kb
Host smart-a6656cb6-8871-49a1-9907-b2b811dcee98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682929443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2682929443
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.578241609
Short name T215
Test name
Test status
Simulation time 586561604 ps
CPU time 0.87 seconds
Started Apr 28 12:24:54 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 197116 kb
Host smart-ab833937-0c09-401b-85b2-2ae29a382da4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578241609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.578241609
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3268851150
Short name T157
Test name
Test status
Simulation time 412706867 ps
CPU time 1.04 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195884 kb
Host smart-48a5a4a1-48f7-421b-8fd0-10763579e13c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268851150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3268851150
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3038739162
Short name T527
Test name
Test status
Simulation time 288931145 ps
CPU time 2.61 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:04 PM PDT 24
Peak memory 197888 kb
Host smart-82fb4033-b588-4fff-808a-2c968b37aa04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038739162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3038739162
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.317781468
Short name T573
Test name
Test status
Simulation time 58597128 ps
CPU time 1.79 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 195948 kb
Host smart-259f8367-0c28-4981-84c9-965943b5c0fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317781468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
317781468
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4123071563
Short name T511
Test name
Test status
Simulation time 46440037 ps
CPU time 0.61 seconds
Started Apr 28 12:25:15 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 194200 kb
Host smart-60ecc730-1e7a-454a-b7a0-23adf71d655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123071563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4123071563
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1443253222
Short name T562
Test name
Test status
Simulation time 443132075 ps
CPU time 0.97 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 195884 kb
Host smart-03b3e043-de3b-4eaa-a2ed-39e9588b6083
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443253222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1443253222
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.718988886
Short name T371
Test name
Test status
Simulation time 609727335 ps
CPU time 5.25 seconds
Started Apr 28 12:25:06 PM PDT 24
Finished Apr 28 12:25:13 PM PDT 24
Peak memory 197800 kb
Host smart-c4560ad5-88ef-468f-ad17-8b1c85d17ecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718988886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.718988886
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1429224982
Short name T690
Test name
Test status
Simulation time 237700865 ps
CPU time 1.2 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195628 kb
Host smart-072a968c-4a42-47b3-8105-d6d49c9911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429224982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1429224982
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1865475012
Short name T425
Test name
Test status
Simulation time 312102288 ps
CPU time 1.25 seconds
Started Apr 28 12:25:05 PM PDT 24
Finished Apr 28 12:25:07 PM PDT 24
Peak memory 196592 kb
Host smart-c8f470b4-220f-4470-8831-f8953e37065f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865475012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1865475012
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.711187072
Short name T676
Test name
Test status
Simulation time 12479762962 ps
CPU time 172.49 seconds
Started Apr 28 12:25:18 PM PDT 24
Finished Apr 28 12:28:12 PM PDT 24
Peak memory 197908 kb
Host smart-173de109-bccd-45f0-9308-133d95f8503d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711187072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.711187072
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2033341208
Short name T335
Test name
Test status
Simulation time 55378593268 ps
CPU time 950.63 seconds
Started Apr 28 12:25:03 PM PDT 24
Finished Apr 28 12:40:55 PM PDT 24
Peak memory 198108 kb
Host smart-5a377828-afef-4d6f-a263-2d0d6d774f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2033341208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2033341208
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3815741119
Short name T332
Test name
Test status
Simulation time 46603489 ps
CPU time 0.56 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:25:19 PM PDT 24
Peak memory 193828 kb
Host smart-6c401818-3670-451c-b6fb-0fbf13feb74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815741119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3815741119
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2048735371
Short name T304
Test name
Test status
Simulation time 19907568 ps
CPU time 0.68 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:24:52 PM PDT 24
Peak memory 194060 kb
Host smart-65709c0b-08fc-4abd-bbad-23a6012655c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048735371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2048735371
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.996060412
Short name T405
Test name
Test status
Simulation time 838848939 ps
CPU time 24.54 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:25:18 PM PDT 24
Peak memory 197800 kb
Host smart-11fc40f5-2e94-436a-936c-099a9e67440e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996060412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.996060412
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2676892167
Short name T454
Test name
Test status
Simulation time 315808917 ps
CPU time 1.07 seconds
Started Apr 28 12:24:53 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 196276 kb
Host smart-d693fc4e-eb1a-4b78-aa64-705946a29677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676892167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2676892167
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.679010120
Short name T528
Test name
Test status
Simulation time 418007038 ps
CPU time 1.41 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 196792 kb
Host smart-80b84435-1439-41ff-9803-5812c39d9f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679010120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.679010120
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3991305259
Short name T119
Test name
Test status
Simulation time 53974404 ps
CPU time 2.09 seconds
Started Apr 28 12:25:22 PM PDT 24
Finished Apr 28 12:25:25 PM PDT 24
Peak memory 197940 kb
Host smart-b11205aa-7612-402a-b1b9-19fdfe7c43b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991305259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3991305259
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.140834699
Short name T359
Test name
Test status
Simulation time 172860489 ps
CPU time 1.96 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 196496 kb
Host smart-1eca90d6-256c-4ed2-947b-f6d651f0e8ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140834699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
140834699
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3099523415
Short name T492
Test name
Test status
Simulation time 50439138 ps
CPU time 1.18 seconds
Started Apr 28 12:25:21 PM PDT 24
Finished Apr 28 12:25:23 PM PDT 24
Peak memory 197932 kb
Host smart-b2f50369-841a-4770-9b35-0f8aabc33c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099523415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3099523415
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3567153168
Short name T13
Test name
Test status
Simulation time 33421367 ps
CPU time 0.73 seconds
Started Apr 28 12:25:25 PM PDT 24
Finished Apr 28 12:25:28 PM PDT 24
Peak memory 196120 kb
Host smart-5f8dc317-e9c4-4b34-a10f-d8f793d728ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567153168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3567153168
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2376819193
Short name T539
Test name
Test status
Simulation time 72921142 ps
CPU time 1.21 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 197772 kb
Host smart-62c4aac5-172d-46dc-b582-bcfbf54e2978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376819193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2376819193
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.120531468
Short name T347
Test name
Test status
Simulation time 41531088 ps
CPU time 0.96 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 195204 kb
Host smart-3f2a01d6-9a99-4f78-8ddc-3815173a2723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120531468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.120531468
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2813360859
Short name T311
Test name
Test status
Simulation time 939742375 ps
CPU time 1.29 seconds
Started Apr 28 12:25:10 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 196332 kb
Host smart-617969bc-5a9e-423f-b032-6c02be8955e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813360859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2813360859
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3958241815
Short name T406
Test name
Test status
Simulation time 10477767123 ps
CPU time 111.5 seconds
Started Apr 28 12:25:35 PM PDT 24
Finished Apr 28 12:27:28 PM PDT 24
Peak memory 198048 kb
Host smart-620cb662-65d7-4266-8bf5-227452def196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958241815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3958241815
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1037798369
Short name T509
Test name
Test status
Simulation time 104154289923 ps
CPU time 1194.17 seconds
Started Apr 28 12:24:48 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 198104 kb
Host smart-f27f779c-02ba-4ecb-b86c-9c8b25b39161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1037798369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1037798369
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.604810290
Short name T457
Test name
Test status
Simulation time 13390474 ps
CPU time 0.56 seconds
Started Apr 28 12:25:06 PM PDT 24
Finished Apr 28 12:25:07 PM PDT 24
Peak memory 193700 kb
Host smart-933b723e-bdd1-4891-8b35-12960a2e3338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604810290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.604810290
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1565157556
Short name T468
Test name
Test status
Simulation time 39175135 ps
CPU time 0.79 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 195212 kb
Host smart-b893c6c6-ebeb-4fc3-b3ef-eed3b7193a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565157556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1565157556
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.603105755
Short name T194
Test name
Test status
Simulation time 117305856 ps
CPU time 5.73 seconds
Started Apr 28 12:25:06 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 195376 kb
Host smart-01ec242b-8c6f-4f07-973b-54f5ff29bcc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603105755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.603105755
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.806893155
Short name T181
Test name
Test status
Simulation time 32514557 ps
CPU time 0.63 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195060 kb
Host smart-bca5bc3b-f491-4136-bef8-58cb983c0369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806893155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.806893155
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2610808485
Short name T619
Test name
Test status
Simulation time 39824625 ps
CPU time 1.06 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 195904 kb
Host smart-9e2bb946-9453-4c82-99cb-fd395a0eed38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610808485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2610808485
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.939192386
Short name T407
Test name
Test status
Simulation time 150073135 ps
CPU time 1.58 seconds
Started Apr 28 12:25:04 PM PDT 24
Finished Apr 28 12:25:06 PM PDT 24
Peak memory 196156 kb
Host smart-5665100c-8a8f-40be-a3e7-edd7c3f3a395
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939192386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.939192386
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3499635252
Short name T410
Test name
Test status
Simulation time 126065692 ps
CPU time 3.6 seconds
Started Apr 28 12:24:59 PM PDT 24
Finished Apr 28 12:25:04 PM PDT 24
Peak memory 196960 kb
Host smart-611f40ea-95a7-4c2b-8958-e3ccb9189959
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499635252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3499635252
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.416844157
Short name T247
Test name
Test status
Simulation time 123072099 ps
CPU time 1.11 seconds
Started Apr 28 12:25:16 PM PDT 24
Finished Apr 28 12:25:18 PM PDT 24
Peak memory 196500 kb
Host smart-4fd88271-7e14-4ee0-98ac-572095a1dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416844157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.416844157
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3031244198
Short name T597
Test name
Test status
Simulation time 599786980 ps
CPU time 0.9 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195772 kb
Host smart-c9235950-5d79-4c92-86dc-76df470f24f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031244198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3031244198
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2421631632
Short name T654
Test name
Test status
Simulation time 196167819 ps
CPU time 4.31 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:58 PM PDT 24
Peak memory 197772 kb
Host smart-7551cbad-67d2-4828-bb7a-cb9578c95e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421631632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2421631632
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1057176006
Short name T199
Test name
Test status
Simulation time 178981846 ps
CPU time 0.91 seconds
Started Apr 28 12:25:08 PM PDT 24
Finished Apr 28 12:25:10 PM PDT 24
Peak memory 195120 kb
Host smart-d64905fe-2aab-4640-bb62-5bee8512de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057176006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1057176006
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1804948109
Short name T428
Test name
Test status
Simulation time 581132873 ps
CPU time 0.96 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195408 kb
Host smart-02b6c7af-6858-481a-acf5-5a8daca8325c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804948109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1804948109
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.105131520
Short name T553
Test name
Test status
Simulation time 3002840675 ps
CPU time 74.45 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:26:33 PM PDT 24
Peak memory 198068 kb
Host smart-c7501c0f-79d6-4732-b3ce-d90c3bdf5428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105131520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.105131520
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3422432640
Short name T644
Test name
Test status
Simulation time 19084769 ps
CPU time 0.55 seconds
Started Apr 28 12:24:47 PM PDT 24
Finished Apr 28 12:24:49 PM PDT 24
Peak memory 193736 kb
Host smart-e52fe95f-6437-4a50-b93c-655553f953a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422432640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3422432640
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3306984177
Short name T692
Test name
Test status
Simulation time 70013509 ps
CPU time 0.78 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195220 kb
Host smart-af64ae19-117d-47cb-a1ae-9c713a57ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306984177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3306984177
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.156993589
Short name T587
Test name
Test status
Simulation time 14129696036 ps
CPU time 24.33 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:38 PM PDT 24
Peak memory 197220 kb
Host smart-53597fe8-be88-47a7-b3e8-1b5b6f1955f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156993589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.156993589
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1804506725
Short name T176
Test name
Test status
Simulation time 227369624 ps
CPU time 0.91 seconds
Started Apr 28 12:24:58 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 195784 kb
Host smart-405f7ce5-e16b-4ea3-ae65-bac4d8401443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804506725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1804506725
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2299428649
Short name T535
Test name
Test status
Simulation time 55391542 ps
CPU time 0.98 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 195804 kb
Host smart-0a040e70-840b-496c-a3da-58e3b8de3e48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299428649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2299428649
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1514430889
Short name T355
Test name
Test status
Simulation time 127312044 ps
CPU time 2.55 seconds
Started Apr 28 12:25:10 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 197944 kb
Host smart-957a5d98-9bcc-453d-b8b9-72fb718820e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514430889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1514430889
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3323724804
Short name T227
Test name
Test status
Simulation time 329965199 ps
CPU time 1.21 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 195680 kb
Host smart-a1e14b5b-86b1-4cea-8d30-58dfd9069a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323724804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3323724804
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1590376228
Short name T650
Test name
Test status
Simulation time 967900987 ps
CPU time 1.25 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 196680 kb
Host smart-fc20fbd9-c7e1-4a0e-ac83-8c1a0bf526f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590376228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1590376228
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2265182416
Short name T172
Test name
Test status
Simulation time 35894387 ps
CPU time 0.85 seconds
Started Apr 28 12:25:03 PM PDT 24
Finished Apr 28 12:25:05 PM PDT 24
Peak memory 196588 kb
Host smart-47027b23-d793-4f08-b45d-c57873b9ff03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265182416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2265182416
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2029453309
Short name T329
Test name
Test status
Simulation time 3286778785 ps
CPU time 5.3 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 197944 kb
Host smart-f89df44a-1109-4968-8261-cf7a4ba531ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029453309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2029453309
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1191370279
Short name T616
Test name
Test status
Simulation time 201667632 ps
CPU time 1.04 seconds
Started Apr 28 12:25:06 PM PDT 24
Finished Apr 28 12:25:08 PM PDT 24
Peak memory 195632 kb
Host smart-4adea378-8e4c-431e-9611-681dc0f86487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191370279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1191370279
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1816305624
Short name T512
Test name
Test status
Simulation time 119257105 ps
CPU time 1.03 seconds
Started Apr 28 12:25:01 PM PDT 24
Finished Apr 28 12:25:03 PM PDT 24
Peak memory 196208 kb
Host smart-76da3531-d353-49f1-9f0b-03afb061d45a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816305624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1816305624
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3219867556
Short name T140
Test name
Test status
Simulation time 2701585647 ps
CPU time 16.02 seconds
Started Apr 28 12:25:30 PM PDT 24
Finished Apr 28 12:25:46 PM PDT 24
Peak memory 198048 kb
Host smart-754b664d-7757-4e29-b451-b0beb13d1b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219867556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3219867556
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3136605188
Short name T601
Test name
Test status
Simulation time 24536773 ps
CPU time 0.58 seconds
Started Apr 28 12:25:20 PM PDT 24
Finished Apr 28 12:25:22 PM PDT 24
Peak memory 193980 kb
Host smart-c695bfcb-9dd1-43a4-aebd-a6f18f30505a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136605188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3136605188
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.496446397
Short name T201
Test name
Test status
Simulation time 53569803 ps
CPU time 0.92 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 195564 kb
Host smart-3712d688-fc90-43a2-9a72-31d92319caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496446397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.496446397
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2689116494
Short name T210
Test name
Test status
Simulation time 202076774 ps
CPU time 6.81 seconds
Started Apr 28 12:24:50 PM PDT 24
Finished Apr 28 12:25:01 PM PDT 24
Peak memory 196856 kb
Host smart-94399f93-01b2-4381-b3e6-bfe63d8be706
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689116494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2689116494
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1158101446
Short name T552
Test name
Test status
Simulation time 334261999 ps
CPU time 0.95 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 196612 kb
Host smart-5ae89520-ce47-4992-a7e6-dc1978ad3038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158101446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1158101446
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2070881110
Short name T402
Test name
Test status
Simulation time 52305771 ps
CPU time 0.94 seconds
Started Apr 28 12:25:13 PM PDT 24
Finished Apr 28 12:25:16 PM PDT 24
Peak memory 196516 kb
Host smart-e506ad0c-0ea1-4bad-aa21-f69908dc7a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070881110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2070881110
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1930371041
Short name T120
Test name
Test status
Simulation time 196831594 ps
CPU time 2.19 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:25:20 PM PDT 24
Peak memory 197900 kb
Host smart-0464e6eb-6e5a-498c-976c-e8a52e84758c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930371041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1930371041
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1176316517
Short name T585
Test name
Test status
Simulation time 177209427 ps
CPU time 1.49 seconds
Started Apr 28 12:24:54 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 195944 kb
Host smart-23436297-20e4-43c2-84df-a41e5c3b0db7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176316517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1176316517
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.210634749
Short name T504
Test name
Test status
Simulation time 270719430 ps
CPU time 0.74 seconds
Started Apr 28 12:24:57 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 196460 kb
Host smart-f8decf16-16f0-4508-a419-13cfac1a1bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210634749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.210634749
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3137912125
Short name T404
Test name
Test status
Simulation time 103609502 ps
CPU time 1.2 seconds
Started Apr 28 12:25:19 PM PDT 24
Finished Apr 28 12:25:21 PM PDT 24
Peak memory 196752 kb
Host smart-7d2be853-3252-4321-9fd4-fe9f36cafab6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137912125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3137912125
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1100739789
Short name T114
Test name
Test status
Simulation time 761380282 ps
CPU time 4.55 seconds
Started Apr 28 12:24:52 PM PDT 24
Finished Apr 28 12:25:01 PM PDT 24
Peak memory 197848 kb
Host smart-f2ff0758-73b7-47e2-848d-b222bd018e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100739789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1100739789
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2055503189
Short name T261
Test name
Test status
Simulation time 143714630 ps
CPU time 1.12 seconds
Started Apr 28 12:25:00 PM PDT 24
Finished Apr 28 12:25:02 PM PDT 24
Peak memory 195524 kb
Host smart-180be397-2c26-4ef7-b847-0ba4740bf7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055503189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2055503189
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.543799833
Short name T657
Test name
Test status
Simulation time 125796260 ps
CPU time 1 seconds
Started Apr 28 12:24:49 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 195748 kb
Host smart-ad9e895a-a3f0-4cbf-9ddf-252484eff226
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543799833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.543799833
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1944051161
Short name T122
Test name
Test status
Simulation time 32511877614 ps
CPU time 191.5 seconds
Started Apr 28 12:25:15 PM PDT 24
Finished Apr 28 12:28:28 PM PDT 24
Peak memory 198024 kb
Host smart-52b55607-0f65-49e3-b271-e5d7252347b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944051161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1944051161
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.564084755
Short name T192
Test name
Test status
Simulation time 14827061 ps
CPU time 0.56 seconds
Started Apr 28 12:25:15 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 194040 kb
Host smart-44e4dec5-1062-4bdc-9419-bdf603be2f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564084755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.564084755
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3539371985
Short name T275
Test name
Test status
Simulation time 23952031 ps
CPU time 0.69 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 194764 kb
Host smart-c37cef14-83d9-463d-853d-be8f061868ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539371985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3539371985
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1199027621
Short name T532
Test name
Test status
Simulation time 157226429 ps
CPU time 4.37 seconds
Started Apr 28 12:26:13 PM PDT 24
Finished Apr 28 12:26:18 PM PDT 24
Peak memory 195136 kb
Host smart-f66ca8a8-3c30-4f14-897c-9610498467b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199027621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1199027621
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.346697072
Short name T205
Test name
Test status
Simulation time 39786208 ps
CPU time 0.75 seconds
Started Apr 28 12:25:17 PM PDT 24
Finished Apr 28 12:25:19 PM PDT 24
Peak memory 195760 kb
Host smart-1f6ba55c-8c93-4344-8311-07376c9e1cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346697072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.346697072
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2649991708
Short name T253
Test name
Test status
Simulation time 84842745 ps
CPU time 0.87 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 196516 kb
Host smart-82483b4d-7014-4074-8feb-22b016dbc2d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649991708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2649991708
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2966665238
Short name T691
Test name
Test status
Simulation time 204784170 ps
CPU time 2.13 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:15 PM PDT 24
Peak memory 196156 kb
Host smart-28161228-189e-4743-b82d-e64548f6a2b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966665238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2966665238
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3842814330
Short name T711
Test name
Test status
Simulation time 272752557 ps
CPU time 3 seconds
Started Apr 28 12:25:09 PM PDT 24
Finished Apr 28 12:25:13 PM PDT 24
Peak memory 197920 kb
Host smart-9f202409-de54-4b56-a6fa-30336eb052f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842814330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3842814330
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1573029720
Short name T251
Test name
Test status
Simulation time 24860360 ps
CPU time 0.92 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 195676 kb
Host smart-9d4314b0-a31c-421f-9e83-5932118629c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573029720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1573029720
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2489482937
Short name T575
Test name
Test status
Simulation time 35044854 ps
CPU time 1.15 seconds
Started Apr 28 12:25:09 PM PDT 24
Finished Apr 28 12:25:11 PM PDT 24
Peak memory 195748 kb
Host smart-b68b34cd-427e-465a-a56a-02c2ee2f9a74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489482937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2489482937
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1344501611
Short name T131
Test name
Test status
Simulation time 779700907 ps
CPU time 3.59 seconds
Started Apr 28 12:25:11 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 197916 kb
Host smart-f6e1bc04-5a47-442f-acf9-06b3dfdf91f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344501611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1344501611
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1166351558
Short name T164
Test name
Test status
Simulation time 1545920967 ps
CPU time 1.29 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 195412 kb
Host smart-6c6523ff-7e2c-4a8b-b04f-2dfb441ef01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166351558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1166351558
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2025825252
Short name T362
Test name
Test status
Simulation time 97976860 ps
CPU time 1.16 seconds
Started Apr 28 12:24:51 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 195592 kb
Host smart-8567741d-6d00-44b3-b3d0-45a91fe3c5ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025825252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2025825252
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3606336022
Short name T249
Test name
Test status
Simulation time 1996154289 ps
CPU time 38.47 seconds
Started Apr 28 12:24:53 PM PDT 24
Finished Apr 28 12:25:35 PM PDT 24
Peak memory 197864 kb
Host smart-d6b4dc32-b074-4cd3-878b-680f74c2729b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606336022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3606336022
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3635383555
Short name T340
Test name
Test status
Simulation time 57988242 ps
CPU time 0.53 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 194552 kb
Host smart-4e2be5c9-22c8-41b4-a235-e8fb83c570b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635383555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3635383555
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4167606439
Short name T596
Test name
Test status
Simulation time 85524488 ps
CPU time 0.68 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 194856 kb
Host smart-6e175c12-be91-4ef0-abe9-1fc37ba3468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167606439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4167606439
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2964116353
Short name T455
Test name
Test status
Simulation time 639822998 ps
CPU time 20.83 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196740 kb
Host smart-3f6ae6f3-68b7-47cd-a373-1978f5a1de80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964116353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2964116353
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4080737268
Short name T476
Test name
Test status
Simulation time 25232037 ps
CPU time 0.74 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:00 PM PDT 24
Peak memory 195660 kb
Host smart-10d1b07c-b50d-4f1e-8f68-6d1d181196f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080737268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4080737268
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3156913485
Short name T265
Test name
Test status
Simulation time 152968066 ps
CPU time 1.22 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 196068 kb
Host smart-258aa1cd-3fd6-4f05-96af-0cf605aed209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156913485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3156913485
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4061148857
Short name T256
Test name
Test status
Simulation time 196868982 ps
CPU time 3.47 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 197592 kb
Host smart-8b188ba0-e0ab-47cb-bcfe-6d4b0a7c3554
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061148857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4061148857
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4007924599
Short name T281
Test name
Test status
Simulation time 246598791 ps
CPU time 1.95 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 196988 kb
Host smart-946c6c22-318c-44f0-a216-21549b0978ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007924599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4007924599
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2354191458
Short name T143
Test name
Test status
Simulation time 71800428 ps
CPU time 0.69 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 195180 kb
Host smart-97d29d55-8b8f-42d2-8c4a-c7abfb2a9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354191458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2354191458
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4206787743
Short name T540
Test name
Test status
Simulation time 145925020 ps
CPU time 0.69 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 194192 kb
Host smart-194597f3-de71-4266-b4fe-e81ec2f33570
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206787743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4206787743
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3426640390
Short name T208
Test name
Test status
Simulation time 296216069 ps
CPU time 4.62 seconds
Started Apr 28 12:23:49 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 197844 kb
Host smart-bf77978b-a497-4bcb-b4e3-6f5001bec260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426640390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3426640390
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3479937094
Short name T299
Test name
Test status
Simulation time 60213245 ps
CPU time 1.06 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 195032 kb
Host smart-0cf24b9c-b0f2-49b7-b90c-9d7eca9cd3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479937094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3479937094
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3460912164
Short name T643
Test name
Test status
Simulation time 192754976 ps
CPU time 1.13 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 195576 kb
Host smart-743c8880-ced6-4da5-a023-d6db646d22a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460912164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3460912164
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.4037750652
Short name T570
Test name
Test status
Simulation time 19909127191 ps
CPU time 69.25 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:25:12 PM PDT 24
Peak memory 197984 kb
Host smart-b479de96-cd07-4ba5-ac52-d66f8df2fc1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037750652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.4037750652
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3236918978
Short name T156
Test name
Test status
Simulation time 15303981 ps
CPU time 0.55 seconds
Started Apr 28 12:23:40 PM PDT 24
Finished Apr 28 12:23:48 PM PDT 24
Peak memory 194488 kb
Host smart-69a5601d-b237-43f9-9780-2c2b93f120b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236918978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3236918978
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2429179815
Short name T671
Test name
Test status
Simulation time 71475557 ps
CPU time 0.67 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 194740 kb
Host smart-367335dd-ef57-4d83-946a-b6f0e37459d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429179815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2429179815
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3148176927
Short name T446
Test name
Test status
Simulation time 738188389 ps
CPU time 18.65 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 195380 kb
Host smart-ee7ccb92-7016-4ee3-a6bd-584715d5c719
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148176927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3148176927
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1283999192
Short name T18
Test name
Test status
Simulation time 124543856 ps
CPU time 0.86 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 197164 kb
Host smart-c94fb8c7-2e17-4ee7-9115-2ef0f744b8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283999192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1283999192
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2080001704
Short name T624
Test name
Test status
Simulation time 553496008 ps
CPU time 0.88 seconds
Started Apr 28 12:24:02 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 195820 kb
Host smart-b3c1738e-bfc3-43ef-aa61-884bb6d7604a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080001704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2080001704
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1790307450
Short name T213
Test name
Test status
Simulation time 117298216 ps
CPU time 2.71 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 198012 kb
Host smart-7193bf72-d35b-455a-8ddd-2eb15030681e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790307450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1790307450
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3692043880
Short name T558
Test name
Test status
Simulation time 401449467 ps
CPU time 2.21 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 196140 kb
Host smart-2628033b-631e-401c-b277-bbd0a8eca823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692043880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3692043880
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.103470862
Short name T613
Test name
Test status
Simulation time 42443694 ps
CPU time 0.82 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 195696 kb
Host smart-a9c41752-f66c-4059-b929-2aabf2c8db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103470862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.103470862
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.572802068
Short name T242
Test name
Test status
Simulation time 20900222 ps
CPU time 0.74 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 195352 kb
Host smart-33e55d6e-b75e-4e4e-8b74-229f4681f545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572802068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.572802068
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.76693706
Short name T223
Test name
Test status
Simulation time 2114759684 ps
CPU time 4.11 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 197808 kb
Host smart-d021b90b-085a-481a-a760-38c4b5811ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76693706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rando
m_long_reg_writes_reg_reads.76693706
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1223954651
Short name T369
Test name
Test status
Simulation time 39803396 ps
CPU time 0.8 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:00 PM PDT 24
Peak memory 195956 kb
Host smart-b1d417dc-4298-49fe-b3f8-a4cf5efb6bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223954651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1223954651
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3094513576
Short name T12
Test name
Test status
Simulation time 52837297 ps
CPU time 0.91 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 196104 kb
Host smart-8846ec4f-736e-486f-864e-6e27757652dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094513576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3094513576
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2638946312
Short name T6
Test name
Test status
Simulation time 82165996902 ps
CPU time 245.9 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:28:10 PM PDT 24
Peak memory 197920 kb
Host smart-1161d613-e9b6-4a67-b752-67a69e270cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638946312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2638946312
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4182000686
Short name T460
Test name
Test status
Simulation time 23717975 ps
CPU time 0.54 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 193732 kb
Host smart-73fcbcd5-de53-43ba-8a3b-f73ba4977b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182000686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4182000686
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2318431104
Short name T464
Test name
Test status
Simulation time 35524924 ps
CPU time 0.69 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 195168 kb
Host smart-fbbf05b5-5780-4c78-a204-132ece1514b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318431104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2318431104
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2250610392
Short name T27
Test name
Test status
Simulation time 1144678201 ps
CPU time 13.36 seconds
Started Apr 28 12:24:04 PM PDT 24
Finished Apr 28 12:24:20 PM PDT 24
Peak memory 196388 kb
Host smart-399ad497-dd61-47b0-849a-c995de4d8a23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250610392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2250610392
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2441816942
Short name T591
Test name
Test status
Simulation time 70612809 ps
CPU time 1 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 196272 kb
Host smart-45635a4b-ca15-4586-ac55-b101210410e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441816942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2441816942
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.623009714
Short name T130
Test name
Test status
Simulation time 127330610 ps
CPU time 0.72 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 195380 kb
Host smart-1831b4cd-4612-4924-84a6-c002d9c9fdcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623009714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.623009714
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3009285931
Short name T395
Test name
Test status
Simulation time 294707907 ps
CPU time 2.37 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 197860 kb
Host smart-a61a9135-f2d9-4c18-92ea-07bb1002f038
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009285931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3009285931
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.132551639
Short name T551
Test name
Test status
Simulation time 121804434 ps
CPU time 3.3 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 197004 kb
Host smart-e2e7309b-3760-4979-9a8d-7c4e4ddbe324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132551639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.132551639
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3377189116
Short name T620
Test name
Test status
Simulation time 326986955 ps
CPU time 0.87 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 195808 kb
Host smart-d25925d4-bf51-4ab2-99ea-f635be21afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377189116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3377189116
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.651464847
Short name T667
Test name
Test status
Simulation time 71634642 ps
CPU time 0.82 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 196448 kb
Host smart-91c0f53d-d5bd-466c-9d8c-056baa900d2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651464847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.651464847
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2182925084
Short name T19
Test name
Test status
Simulation time 49843795 ps
CPU time 2.23 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 197836 kb
Host smart-6ebd365e-7c71-42f1-8190-9a8e8c730186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182925084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2182925084
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.105030471
Short name T22
Test name
Test status
Simulation time 63721079 ps
CPU time 1.17 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:55 PM PDT 24
Peak memory 195736 kb
Host smart-88fa71b8-7d14-4f93-ae52-d3c1ab9736f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105030471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.105030471
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1264268908
Short name T226
Test name
Test status
Simulation time 636373014 ps
CPU time 1.16 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 195784 kb
Host smart-162f338d-047a-4716-8b37-fc27087df063
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264268908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1264268908
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1601080622
Short name T715
Test name
Test status
Simulation time 3635340776 ps
CPU time 84.69 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 198036 kb
Host smart-f4d6ff66-a246-4e41-8726-8c51964b234e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601080622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1601080622
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3952613973
Short name T334
Test name
Test status
Simulation time 12019683 ps
CPU time 0.53 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:23:47 PM PDT 24
Peak memory 193760 kb
Host smart-9e268649-6aa2-4d3b-9433-48c8700dc6d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952613973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3952613973
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4176899704
Short name T646
Test name
Test status
Simulation time 165328012 ps
CPU time 0.9 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:45 PM PDT 24
Peak memory 196460 kb
Host smart-fc74a8a6-3de4-4ed4-a552-456587ff0287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176899704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4176899704
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2388272412
Short name T351
Test name
Test status
Simulation time 6679991188 ps
CPU time 23.57 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 197328 kb
Host smart-7776a753-4f70-4b84-ae54-afa3c6317df7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388272412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2388272412
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2142156261
Short name T565
Test name
Test status
Simulation time 87550061 ps
CPU time 0.75 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:44 PM PDT 24
Peak memory 196548 kb
Host smart-5a80e3f1-9526-4c15-9f13-fee8d8ec657d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142156261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2142156261
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2884496691
Short name T159
Test name
Test status
Simulation time 104950065 ps
CPU time 0.74 seconds
Started Apr 28 12:23:47 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 196228 kb
Host smart-7eefedfe-6354-40a5-b8ea-248c8f57f193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884496691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2884496691
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1355503155
Short name T368
Test name
Test status
Simulation time 1552523839 ps
CPU time 2.98 seconds
Started Apr 28 12:24:01 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 197812 kb
Host smart-3887f5ec-b373-4fc9-84be-7a1210efa8e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355503155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1355503155
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1356333125
Short name T605
Test name
Test status
Simulation time 87677388 ps
CPU time 1.76 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 196704 kb
Host smart-65ade01d-c721-44ca-8d0e-d3fbbf81fecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356333125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1356333125
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.883994334
Short name T584
Test name
Test status
Simulation time 252427060 ps
CPU time 1.1 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 195988 kb
Host smart-0f3b4ce7-4acc-48c5-8ddf-5d8b33746b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883994334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.883994334
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1547721632
Short name T472
Test name
Test status
Simulation time 52258051 ps
CPU time 1.13 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 196452 kb
Host smart-c0b2a705-f2f7-4f2e-b195-82b14f8a490f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547721632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1547721632
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3967261656
Short name T14
Test name
Test status
Simulation time 342026374 ps
CPU time 4.02 seconds
Started Apr 28 12:24:01 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 197700 kb
Host smart-300c3dce-f17f-4408-89a0-4db3af35db08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967261656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3967261656
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2720028993
Short name T258
Test name
Test status
Simulation time 67583111 ps
CPU time 1.22 seconds
Started Apr 28 12:24:15 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 195388 kb
Host smart-c8f06982-2986-467d-9619-aa7c594517a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720028993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2720028993
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3181689298
Short name T77
Test name
Test status
Simulation time 55489373 ps
CPU time 1.02 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 196324 kb
Host smart-2aa356bd-012e-4876-b2a0-fd85540c00a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181689298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3181689298
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3382481170
Short name T224
Test name
Test status
Simulation time 83112052033 ps
CPU time 126.73 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:26:07 PM PDT 24
Peak memory 198008 kb
Host smart-42921746-2912-4e97-8f77-de4c93a93acc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382481170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3382481170
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1720438691
Short name T63
Test name
Test status
Simulation time 723192416335 ps
CPU time 1485.34 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:48:33 PM PDT 24
Peak memory 206232 kb
Host smart-1f6c9979-2247-4f33-947f-8c7bf8278d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1720438691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1720438691
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3683689860
Short name T475
Test name
Test status
Simulation time 15417675 ps
CPU time 0.57 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:45 PM PDT 24
Peak memory 193824 kb
Host smart-9cf8d1b2-2ec1-4b0f-9d28-4cacbf37b1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683689860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3683689860
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2754106781
Short name T145
Test name
Test status
Simulation time 30838544 ps
CPU time 0.69 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 194780 kb
Host smart-8ece7a44-06db-42ab-948d-888af7c4b360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754106781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2754106781
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2030709192
Short name T665
Test name
Test status
Simulation time 1023508229 ps
CPU time 18.76 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:53 PM PDT 24
Peak memory 196004 kb
Host smart-457ddc42-cbe0-4c84-a8bc-8fe0386a16c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030709192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2030709192
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2148786360
Short name T284
Test name
Test status
Simulation time 46166917 ps
CPU time 0.8 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 195868 kb
Host smart-36d147af-eb87-4f1a-92bd-2671b27ce3d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148786360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2148786360
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4149639349
Short name T609
Test name
Test status
Simulation time 88660077 ps
CPU time 1.25 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 197184 kb
Host smart-0a5e800f-f3b5-4b0a-b035-de4954f646b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149639349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4149639349
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2397322883
Short name T56
Test name
Test status
Simulation time 226714526 ps
CPU time 1.59 seconds
Started Apr 28 12:24:08 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 196120 kb
Host smart-b6e106fc-4a84-4e85-884a-fa325a8d8300
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397322883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2397322883
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.412572544
Short name T517
Test name
Test status
Simulation time 599841523 ps
CPU time 2.89 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:57 PM PDT 24
Peak memory 196896 kb
Host smart-949ee327-2030-4c46-873a-f942bea317cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412572544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.412572544
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3493948114
Short name T439
Test name
Test status
Simulation time 253740778 ps
CPU time 1.08 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 196336 kb
Host smart-46ba89c3-5718-4a4e-9fb1-68a4a59c8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493948114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3493948114
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2905109015
Short name T128
Test name
Test status
Simulation time 151126249 ps
CPU time 1.16 seconds
Started Apr 28 12:24:13 PM PDT 24
Finished Apr 28 12:24:16 PM PDT 24
Peak memory 196756 kb
Host smart-717cefa1-6727-4402-b60e-986b179193a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905109015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2905109015
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2326407689
Short name T254
Test name
Test status
Simulation time 342575431 ps
CPU time 5.48 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 197844 kb
Host smart-766e2451-34d4-4fae-bf76-b6db00eaaf86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326407689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2326407689
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.79686494
Short name T580
Test name
Test status
Simulation time 38471091 ps
CPU time 0.82 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 195204 kb
Host smart-81c9ef68-613f-4882-afa8-7a15a2559c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79686494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.79686494
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1783420813
Short name T586
Test name
Test status
Simulation time 173643363 ps
CPU time 0.82 seconds
Started Apr 28 12:24:11 PM PDT 24
Finished Apr 28 12:24:14 PM PDT 24
Peak memory 196096 kb
Host smart-1229a31d-0adb-4a17-b518-6a68a9044811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783420813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1783420813
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.905047531
Short name T357
Test name
Test status
Simulation time 13513133041 ps
CPU time 162.07 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:26:39 PM PDT 24
Peak memory 197908 kb
Host smart-1cb1547b-449d-4fee-8d50-f3daff9966ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905047531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.905047531
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3370833224
Short name T484
Test name
Test status
Simulation time 56353180206 ps
CPU time 693.84 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:35:35 PM PDT 24
Peak memory 198016 kb
Host smart-7cae7a5e-df16-47c1-aa9e-db2846e68a0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3370833224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3370833224
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.41898553
Short name T896
Test name
Test status
Simulation time 249982589 ps
CPU time 1.14 seconds
Started Apr 28 12:19:43 PM PDT 24
Finished Apr 28 12:19:45 PM PDT 24
Peak memory 196664 kb
Host smart-d2ba90b2-9f9b-408b-9c1a-24af3c875c44
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=41898553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.41898553
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.442035537
Short name T877
Test name
Test status
Simulation time 62515517 ps
CPU time 0.97 seconds
Started Apr 28 12:19:35 PM PDT 24
Finished Apr 28 12:19:36 PM PDT 24
Peak memory 195984 kb
Host smart-6ecf6247-b624-44b0-a9be-841d9393475c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442035537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.442035537
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.664675440
Short name T936
Test name
Test status
Simulation time 156248829 ps
CPU time 1.47 seconds
Started Apr 28 12:20:17 PM PDT 24
Finished Apr 28 12:20:19 PM PDT 24
Peak memory 197940 kb
Host smart-aeb97260-3d89-4142-a334-859725b31ae6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=664675440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.664675440
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3736791101
Short name T944
Test name
Test status
Simulation time 57827831 ps
CPU time 0.88 seconds
Started Apr 28 12:19:02 PM PDT 24
Finished Apr 28 12:19:03 PM PDT 24
Peak memory 196720 kb
Host smart-97f45ee3-a4ed-48c2-b663-b4e564e375b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736791101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3736791101
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3695506304
Short name T880
Test name
Test status
Simulation time 85855563 ps
CPU time 1.31 seconds
Started Apr 28 12:18:08 PM PDT 24
Finished Apr 28 12:18:10 PM PDT 24
Peak memory 196852 kb
Host smart-0bcd988c-27db-4a4e-a6a0-cead128f5795
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3695506304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3695506304
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3938239543
Short name T881
Test name
Test status
Simulation time 253542138 ps
CPU time 1.21 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 197916 kb
Host smart-4eed015d-9b8d-4095-906c-3059b736e25f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938239543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3938239543
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3498334906
Short name T922
Test name
Test status
Simulation time 79347784 ps
CPU time 1.5 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:48 PM PDT 24
Peak memory 196608 kb
Host smart-9839fd7f-fd68-43dc-94ae-cc07559541b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3498334906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3498334906
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164549106
Short name T940
Test name
Test status
Simulation time 240664404 ps
CPU time 1.14 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 196460 kb
Host smart-613f66b2-921c-459d-9ba3-df5d6a603e33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164549106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1164549106
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1835526758
Short name T924
Test name
Test status
Simulation time 58569019 ps
CPU time 1.2 seconds
Started Apr 28 12:19:01 PM PDT 24
Finished Apr 28 12:19:02 PM PDT 24
Peak memory 198048 kb
Host smart-04e9852c-de0d-4460-a5d1-b141f4a2b832
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1835526758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1835526758
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3602352257
Short name T863
Test name
Test status
Simulation time 44571547 ps
CPU time 1.08 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 197728 kb
Host smart-6f11a286-9c3d-4e92-b248-ef9a2cc6a8dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602352257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3602352257
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2628157451
Short name T894
Test name
Test status
Simulation time 110060186 ps
CPU time 1.24 seconds
Started Apr 28 12:21:09 PM PDT 24
Finished Apr 28 12:21:11 PM PDT 24
Peak memory 196680 kb
Host smart-5afe2e2c-5012-4140-b938-33c3a59801f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2628157451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2628157451
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2375510159
Short name T923
Test name
Test status
Simulation time 35129377 ps
CPU time 0.97 seconds
Started Apr 28 12:18:58 PM PDT 24
Finished Apr 28 12:18:59 PM PDT 24
Peak memory 196004 kb
Host smart-f0133717-276c-4e68-9a60-0ffb578a23bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375510159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2375510159
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3643612556
Short name T867
Test name
Test status
Simulation time 73064717 ps
CPU time 1.26 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 195604 kb
Host smart-864f4552-f360-44ee-a2ef-7d1cf4b5aa43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3643612556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3643612556
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1557082369
Short name T937
Test name
Test status
Simulation time 44463161 ps
CPU time 1.2 seconds
Started Apr 28 12:18:03 PM PDT 24
Finished Apr 28 12:18:05 PM PDT 24
Peak memory 197176 kb
Host smart-7d81ab38-e06f-4fcd-a948-f957f32797a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557082369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1557082369
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1429400720
Short name T914
Test name
Test status
Simulation time 120104433 ps
CPU time 1 seconds
Started Apr 28 12:21:06 PM PDT 24
Finished Apr 28 12:21:08 PM PDT 24
Peak memory 196556 kb
Host smart-55891e64-b9c3-47aa-bff0-85f8694f6add
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1429400720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1429400720
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2618054728
Short name T846
Test name
Test status
Simulation time 60429553 ps
CPU time 1.21 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:53 PM PDT 24
Peak memory 197076 kb
Host smart-075e53ad-fbf4-4ee1-a107-1ee09e0d8f9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618054728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2618054728
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2927744556
Short name T926
Test name
Test status
Simulation time 31672015 ps
CPU time 0.92 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 196744 kb
Host smart-279b4420-aded-4d90-9e29-80de8861451c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2927744556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2927744556
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3974094115
Short name T861
Test name
Test status
Simulation time 74635557 ps
CPU time 1.11 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 194492 kb
Host smart-d95094ff-b8ab-4ab4-8bf1-451c418e0c3c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974094115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3974094115
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1843519255
Short name T845
Test name
Test status
Simulation time 47780492 ps
CPU time 0.95 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 196044 kb
Host smart-275e9c28-00cc-4fad-870a-d0b5dda82516
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1843519255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1843519255
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3078793544
Short name T885
Test name
Test status
Simulation time 79476761 ps
CPU time 1.57 seconds
Started Apr 28 12:18:42 PM PDT 24
Finished Apr 28 12:18:44 PM PDT 24
Peak memory 198112 kb
Host smart-dbe86189-389c-486a-a6e7-7f712810b0ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078793544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3078793544
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.291150441
Short name T847
Test name
Test status
Simulation time 161666672 ps
CPU time 1.14 seconds
Started Apr 28 12:18:42 PM PDT 24
Finished Apr 28 12:18:43 PM PDT 24
Peak memory 196776 kb
Host smart-2d68cb35-153d-4a11-b355-b779a7de82eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=291150441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.291150441
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2815697295
Short name T900
Test name
Test status
Simulation time 240050828 ps
CPU time 0.99 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 196440 kb
Host smart-51e51e68-8c53-4756-87b7-1cacac9aac42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815697295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2815697295
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.903393081
Short name T928
Test name
Test status
Simulation time 208577451 ps
CPU time 1.07 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 197996 kb
Host smart-2999f10f-f14d-47b8-ad0b-397b6f0a081f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=903393081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.903393081
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376936415
Short name T883
Test name
Test status
Simulation time 628279003 ps
CPU time 0.81 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 194796 kb
Host smart-78e77bbc-18a3-4992-985f-b392968a4152
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376936415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2376936415
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3698608056
Short name T872
Test name
Test status
Simulation time 310802978 ps
CPU time 1.15 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 196016 kb
Host smart-8ec3621a-6b31-42ae-af57-87d42e47c7bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3698608056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3698608056
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122731774
Short name T933
Test name
Test status
Simulation time 205912811 ps
CPU time 1.03 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 196488 kb
Host smart-988accbe-58de-46da-ad25-c8c0316209fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122731774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1122731774
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1634312726
Short name T942
Test name
Test status
Simulation time 59753463 ps
CPU time 1.17 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 197468 kb
Host smart-3ce53e39-4ca6-4cd2-bffd-06fc923a1444
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1634312726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1634312726
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3197271163
Short name T902
Test name
Test status
Simulation time 205482168 ps
CPU time 0.93 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 195536 kb
Host smart-e4540f9b-bdcc-413b-9889-97e07d76aae9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197271163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3197271163
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1461310524
Short name T929
Test name
Test status
Simulation time 98395007 ps
CPU time 1.25 seconds
Started Apr 28 12:20:25 PM PDT 24
Finished Apr 28 12:20:27 PM PDT 24
Peak memory 196980 kb
Host smart-1c558278-a6bb-4fc4-a366-e9cb25dd0e65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1461310524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1461310524
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2816304400
Short name T938
Test name
Test status
Simulation time 46745447 ps
CPU time 0.97 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196232 kb
Host smart-39efb162-3f0e-44a3-a4bb-76ffb67e0cc6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816304400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2816304400
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3124746347
Short name T868
Test name
Test status
Simulation time 170726241 ps
CPU time 0.91 seconds
Started Apr 28 12:17:46 PM PDT 24
Finished Apr 28 12:17:47 PM PDT 24
Peak memory 196464 kb
Host smart-a6b845f0-3d0b-447a-ad34-5ce776dea56f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3124746347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3124746347
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2453720879
Short name T874
Test name
Test status
Simulation time 853122640 ps
CPU time 1.25 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 195076 kb
Host smart-b5f5b5f8-2d75-4ab6-b9ef-0db29a0674dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453720879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2453720879
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2413959916
Short name T851
Test name
Test status
Simulation time 52688341 ps
CPU time 1.32 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 196412 kb
Host smart-1a0c9899-b186-433c-90b0-43f0e721815d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2413959916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2413959916
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043530022
Short name T918
Test name
Test status
Simulation time 77911167 ps
CPU time 1.24 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 195824 kb
Host smart-48d6481d-513d-43e9-91a5-8ccbb0f3d920
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043530022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3043530022
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1661063613
Short name T875
Test name
Test status
Simulation time 72560252 ps
CPU time 1.33 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:18:11 PM PDT 24
Peak memory 196868 kb
Host smart-1f630a78-7269-460a-bd48-010ccb79cade
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1661063613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1661063613
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3727061040
Short name T849
Test name
Test status
Simulation time 145017669 ps
CPU time 1.05 seconds
Started Apr 28 12:18:06 PM PDT 24
Finished Apr 28 12:18:07 PM PDT 24
Peak memory 196588 kb
Host smart-c8f7836c-58b1-45ca-b0dc-aa4372b7459e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727061040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3727061040
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2405327276
Short name T943
Test name
Test status
Simulation time 68173950 ps
CPU time 1.04 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:54 PM PDT 24
Peak memory 196576 kb
Host smart-6257baca-2c50-4b16-910d-96acdcc041e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2405327276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2405327276
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573744868
Short name T930
Test name
Test status
Simulation time 420675356 ps
CPU time 0.91 seconds
Started Apr 28 12:18:04 PM PDT 24
Finished Apr 28 12:18:05 PM PDT 24
Peak memory 196800 kb
Host smart-2a88214f-e275-4e71-bc33-015646e2844f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573744868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1573744868
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.655690786
Short name T876
Test name
Test status
Simulation time 27410471 ps
CPU time 0.84 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 196404 kb
Host smart-1509c5b3-60f4-43b9-8be5-2bc9f7a66888
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=655690786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.655690786
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3187970557
Short name T921
Test name
Test status
Simulation time 39399581 ps
CPU time 1.04 seconds
Started Apr 28 12:18:00 PM PDT 24
Finished Apr 28 12:18:01 PM PDT 24
Peak memory 196000 kb
Host smart-060229f8-1e06-4a8e-9024-3875d06e1e46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187970557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3187970557
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3367777697
Short name T859
Test name
Test status
Simulation time 81754297 ps
CPU time 1.12 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:37 PM PDT 24
Peak memory 194620 kb
Host smart-581eb138-01e9-42fd-88f9-8e90110cdb91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3367777697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3367777697
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.107632154
Short name T899
Test name
Test status
Simulation time 31075938 ps
CPU time 0.92 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:56 PM PDT 24
Peak memory 194388 kb
Host smart-8248f086-4166-4538-bf30-425e9d897663
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107632154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.107632154
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2605007974
Short name T886
Test name
Test status
Simulation time 51276440 ps
CPU time 1.29 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:38 PM PDT 24
Peak memory 194628 kb
Host smart-b2dd0fa6-ad6b-4494-be79-d1abf236090c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2605007974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2605007974
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3863682687
Short name T906
Test name
Test status
Simulation time 43343744 ps
CPU time 1.24 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 196600 kb
Host smart-7d9667a9-d815-4b74-97ec-7dfd7a0b3f5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863682687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3863682687
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2162049935
Short name T887
Test name
Test status
Simulation time 321239439 ps
CPU time 1.26 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 195284 kb
Host smart-e2a0dc22-e9a2-4799-bc99-5c1ae4120eb1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2162049935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2162049935
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3283648494
Short name T909
Test name
Test status
Simulation time 94047703 ps
CPU time 1.25 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 195708 kb
Host smart-c23733cf-2ef0-4a7a-83dd-c8d91ec7208a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283648494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3283648494
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.753311920
Short name T941
Test name
Test status
Simulation time 950545639 ps
CPU time 1.29 seconds
Started Apr 28 12:20:33 PM PDT 24
Finished Apr 28 12:20:35 PM PDT 24
Peak memory 196784 kb
Host smart-7ab3f0c1-5e8a-4483-9145-9e20780f3c9e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=753311920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.753311920
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.895915322
Short name T919
Test name
Test status
Simulation time 66782751 ps
CPU time 1.05 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 195544 kb
Host smart-7d76e654-2148-4096-ac0d-169d450de10a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895915322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.895915322
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2061982699
Short name T878
Test name
Test status
Simulation time 240814623 ps
CPU time 0.98 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 195716 kb
Host smart-14aba033-cb71-4a0a-89a3-599bf6096306
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2061982699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2061982699
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195353727
Short name T905
Test name
Test status
Simulation time 137151090 ps
CPU time 1.17 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 196580 kb
Host smart-0d3d86fa-7c41-430b-be81-8a5037fbca0a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195353727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.195353727
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.186091692
Short name T873
Test name
Test status
Simulation time 56179216 ps
CPU time 0.95 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 196544 kb
Host smart-bdc364f3-36c6-4089-94d3-2b0e7e2d336d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=186091692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.186091692
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2553487560
Short name T855
Test name
Test status
Simulation time 51323443 ps
CPU time 1.01 seconds
Started Apr 28 12:22:59 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 195740 kb
Host smart-8ceea21c-c8ce-4980-9b80-697f7045abbd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553487560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2553487560
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1448188076
Short name T897
Test name
Test status
Simulation time 50419857 ps
CPU time 1.03 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 196584 kb
Host smart-71965920-dc68-4bf5-8bc0-74379adb8b00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1448188076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1448188076
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1386494831
Short name T866
Test name
Test status
Simulation time 53219901 ps
CPU time 1.4 seconds
Started Apr 28 12:20:03 PM PDT 24
Finished Apr 28 12:20:05 PM PDT 24
Peak memory 196824 kb
Host smart-2b3d1e1d-8319-4fa1-837a-3b6e2f3322e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386494831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1386494831
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.41797701
Short name T884
Test name
Test status
Simulation time 86543251 ps
CPU time 1.24 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 197032 kb
Host smart-de64b668-499b-4abe-bc4d-03699a746dc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=41797701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.41797701
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2338093063
Short name T860
Test name
Test status
Simulation time 48965673 ps
CPU time 0.98 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 195932 kb
Host smart-a260a665-833d-4c6e-8029-9c665dfc849e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338093063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2338093063
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1233554265
Short name T916
Test name
Test status
Simulation time 49425119 ps
CPU time 0.94 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:47 PM PDT 24
Peak memory 195548 kb
Host smart-94662328-412a-4066-a6ac-6ec8b74344b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1233554265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1233554265
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572661844
Short name T848
Test name
Test status
Simulation time 29529411 ps
CPU time 0.87 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 196764 kb
Host smart-6914cce3-8e78-4325-b3a3-cba1c9ad05c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572661844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.572661844
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3264560148
Short name T864
Test name
Test status
Simulation time 44033060 ps
CPU time 0.93 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 195704 kb
Host smart-2c3a65e2-b120-4e52-b4c3-94e573f571ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3264560148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3264560148
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1415621198
Short name T856
Test name
Test status
Simulation time 45074250 ps
CPU time 0.87 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 196360 kb
Host smart-4f3263dd-fd81-4988-b012-b0217791cd48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415621198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1415621198
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1151529245
Short name T939
Test name
Test status
Simulation time 204960139 ps
CPU time 1.21 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 196628 kb
Host smart-386f6bea-b951-4f48-84b8-fe445eecb2ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1151529245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1151529245
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4284563509
Short name T871
Test name
Test status
Simulation time 67517105 ps
CPU time 1.27 seconds
Started Apr 28 12:23:01 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 197080 kb
Host smart-34af0c5a-8d32-4df1-b3b1-ec7a812462fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284563509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4284563509
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.717224757
Short name T865
Test name
Test status
Simulation time 158654543 ps
CPU time 1.03 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 196616 kb
Host smart-c5ba5ad6-9465-4d88-8656-a4ec50e99d91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=717224757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.717224757
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585065756
Short name T890
Test name
Test status
Simulation time 51015575 ps
CPU time 1.32 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 197328 kb
Host smart-e984928c-ebf1-4cc8-98be-b2267f7de713
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585065756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1585065756
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3498528345
Short name T862
Test name
Test status
Simulation time 139747265 ps
CPU time 0.91 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 196268 kb
Host smart-dde87cef-82a8-456a-b53e-28b51e9904a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3498528345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3498528345
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3165126157
Short name T920
Test name
Test status
Simulation time 267647546 ps
CPU time 1.49 seconds
Started Apr 28 12:20:41 PM PDT 24
Finished Apr 28 12:20:43 PM PDT 24
Peak memory 198116 kb
Host smart-27b6790e-9f17-4515-9e73-79cc6219e772
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165126157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3165126157
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2126600236
Short name T853
Test name
Test status
Simulation time 262268563 ps
CPU time 1.15 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 195924 kb
Host smart-0432e523-0ac9-4ecb-aba1-793f96c27583
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2126600236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2126600236
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.839279868
Short name T892
Test name
Test status
Simulation time 46775506 ps
CPU time 1.15 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 196196 kb
Host smart-f2eec38c-9440-4498-9c54-768526cec141
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839279868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.839279868
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3415164553
Short name T858
Test name
Test status
Simulation time 38321402 ps
CPU time 0.97 seconds
Started Apr 28 12:17:58 PM PDT 24
Finished Apr 28 12:17:59 PM PDT 24
Peak memory 195516 kb
Host smart-bbdcc3cc-35e9-44b0-ac02-a7896b6cdd75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3415164553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3415164553
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486328459
Short name T901
Test name
Test status
Simulation time 105544795 ps
CPU time 1.12 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:41 PM PDT 24
Peak memory 196608 kb
Host smart-cfff7d95-4043-4500-82e6-954977c72ff5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486328459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1486328459
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3117666776
Short name T898
Test name
Test status
Simulation time 19059101 ps
CPU time 0.72 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 195384 kb
Host smart-40e02d3a-7126-4b5e-8e1e-367973aeb4ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3117666776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3117666776
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.935373594
Short name T904
Test name
Test status
Simulation time 74308612 ps
CPU time 1.26 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 195116 kb
Host smart-5a14ccbb-7443-44fe-bc65-9e185f8524eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935373594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.935373594
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2506400731
Short name T910
Test name
Test status
Simulation time 81749455 ps
CPU time 0.94 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 198072 kb
Host smart-5da28f72-f5fa-4f88-bd87-6bdfc93b50de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2506400731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2506400731
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1687124474
Short name T915
Test name
Test status
Simulation time 303868291 ps
CPU time 1.14 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 196564 kb
Host smart-813ef9bc-2fa7-4f84-aa68-e6ce492a8f90
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687124474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1687124474
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1782754960
Short name T870
Test name
Test status
Simulation time 97370871 ps
CPU time 1.27 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 196364 kb
Host smart-d94a7d13-c650-4728-a13a-28577c72dc46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1782754960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1782754960
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2862480335
Short name T869
Test name
Test status
Simulation time 55406585 ps
CPU time 1.12 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 196216 kb
Host smart-43efe426-fdd6-4555-95b7-eedf782a4c33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862480335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2862480335
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2382629170
Short name T912
Test name
Test status
Simulation time 136304884 ps
CPU time 0.94 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 197340 kb
Host smart-d58231f4-58e1-4bf2-86fe-e5e31fdc0659
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2382629170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2382629170
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3945812813
Short name T891
Test name
Test status
Simulation time 43497878 ps
CPU time 1.24 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 196376 kb
Host smart-92b36ffc-ca04-41d9-b4c7-a72e6f3bd12c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945812813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3945812813
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3490783467
Short name T911
Test name
Test status
Simulation time 196632316 ps
CPU time 1.13 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 196372 kb
Host smart-10f793cd-66f9-44bf-abd6-1514745febf8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3490783467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3490783467
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.808156749
Short name T895
Test name
Test status
Simulation time 65083923 ps
CPU time 1.26 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196440 kb
Host smart-5ad74cb0-0d69-4a9c-839e-d4e25447cac8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808156749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.808156749
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.680193703
Short name T925
Test name
Test status
Simulation time 324105677 ps
CPU time 1 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 195932 kb
Host smart-7b22e495-82ce-4f61-8c6a-d62ab203b044
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=680193703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.680193703
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.622606449
Short name T907
Test name
Test status
Simulation time 203049242 ps
CPU time 0.96 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196448 kb
Host smart-ba278239-3ebc-4983-a78d-913de5bfd14b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622606449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.622606449
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.517449384
Short name T854
Test name
Test status
Simulation time 72096008 ps
CPU time 1.33 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 197768 kb
Host smart-18098fb8-6932-4393-b194-dfd451a583ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=517449384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.517449384
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3769951145
Short name T850
Test name
Test status
Simulation time 95780180 ps
CPU time 1.32 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 195652 kb
Host smart-2e681c8b-77ce-4aca-8fb2-c301a49e850c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769951145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3769951145
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1375373231
Short name T913
Test name
Test status
Simulation time 75209830 ps
CPU time 1.07 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 195728 kb
Host smart-fd8dc719-6eea-42c6-bf0e-b65d5ddcaaf7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1375373231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1375373231
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.892294234
Short name T857
Test name
Test status
Simulation time 64217528 ps
CPU time 1 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:37 PM PDT 24
Peak memory 194464 kb
Host smart-0a361443-0ebb-4305-bee8-fef367626b79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892294234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.892294234
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1759113197
Short name T879
Test name
Test status
Simulation time 54381374 ps
CPU time 1.08 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 196464 kb
Host smart-347e1e9a-dada-4b8e-9fe9-9badfac2cf73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1759113197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1759113197
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4163058648
Short name T927
Test name
Test status
Simulation time 62293074 ps
CPU time 0.96 seconds
Started Apr 28 12:18:41 PM PDT 24
Finished Apr 28 12:18:42 PM PDT 24
Peak memory 196732 kb
Host smart-a90ba7bd-59c6-4b59-a345-67019c7e85de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163058648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4163058648
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.646798523
Short name T934
Test name
Test status
Simulation time 94038490 ps
CPU time 1.52 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:19:53 PM PDT 24
Peak memory 196984 kb
Host smart-df1f84bd-9f98-433b-af04-89abac72b4f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=646798523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.646798523
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1242436033
Short name T882
Test name
Test status
Simulation time 130488388 ps
CPU time 0.95 seconds
Started Apr 28 12:22:00 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 195596 kb
Host smart-63c43fbc-1730-4741-b919-818aaf0d3c4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242436033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1242436033
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2245096820
Short name T889
Test name
Test status
Simulation time 165927561 ps
CPU time 0.87 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 196608 kb
Host smart-0a699405-0d16-4f3e-b29f-a72f71970e4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2245096820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2245096820
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.882284317
Short name T852
Test name
Test status
Simulation time 403932007 ps
CPU time 1.29 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 196884 kb
Host smart-fee2da9e-ea1f-4e0d-bc6b-a35673d82840
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882284317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.882284317
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3064449996
Short name T893
Test name
Test status
Simulation time 28967484 ps
CPU time 0.99 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 197648 kb
Host smart-b6863dde-243f-476b-a7d3-b6f46898c612
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3064449996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3064449996
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1283944615
Short name T931
Test name
Test status
Simulation time 161033580 ps
CPU time 1.25 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 195644 kb
Host smart-dbfc74b3-489f-4f4f-9370-754ba7a0810e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283944615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1283944615
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2012935472
Short name T917
Test name
Test status
Simulation time 102918289 ps
CPU time 1.11 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 197872 kb
Host smart-472a8fdf-01bb-4289-922e-123b1bb76aee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2012935472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2012935472
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3863732710
Short name T903
Test name
Test status
Simulation time 118885732 ps
CPU time 0.9 seconds
Started Apr 28 12:17:40 PM PDT 24
Finished Apr 28 12:17:41 PM PDT 24
Peak memory 196376 kb
Host smart-2bc18eea-8592-4217-9c23-6ae819f6818b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863732710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3863732710
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1258410973
Short name T888
Test name
Test status
Simulation time 120992619 ps
CPU time 1.33 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 197916 kb
Host smart-36939d46-2965-4c54-9059-12622d58305a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258410973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1258410973
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2830543252
Short name T935
Test name
Test status
Simulation time 120541271 ps
CPU time 1.04 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 196800 kb
Host smart-35d742b8-3c61-4f49-b8e4-eaef71f17c4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830543252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2830543252
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.183017289
Short name T908
Test name
Test status
Simulation time 213772363 ps
CPU time 0.95 seconds
Started Apr 28 12:18:08 PM PDT 24
Finished Apr 28 12:18:09 PM PDT 24
Peak memory 195868 kb
Host smart-0896a679-9732-4e87-a209-52ab397e03bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=183017289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.183017289
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4130936726
Short name T932
Test name
Test status
Simulation time 52160784 ps
CPU time 1.32 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 194068 kb
Host smart-0d7bd6c6-6c0b-442f-840c-96131a40f356
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130936726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4130936726
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%