Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[1]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[2]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[3]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[4]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[5]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[6]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[7]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[8]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[9]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[10]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[11]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[12]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[13]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[14]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[15]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[16]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[17]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[18]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[19]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[20]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[21]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[22]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[23]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[24]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[25]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[26]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[27]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[28]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[29]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[30]	4469243	1			T21	43244		T22	38159		T23	1
all_pins[31]	4469243	1			T21	43244		T22	38159		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88839052	1			T21	860394		T22	756450		T23	32
values[0x1]	54176724	1			T21	523414		T22	464638		T24	2813
transitions[0x0=>0x1]	32461190	1			T21	314173		T22	278850		T24	1595
transitions[0x1=>0x0]	32461048	1			T21	314173		T22	278850		T24	1595

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2776176	1			T21	27412		T22	23671		T23	1
all_pins[0]	values[0x1]	1693067	1			T21	15832		T22	14488		T24	90
all_pins[0]	transitions[0x0=>0x1]	1046605	1			T21	9595		T22	8951		T24	64
all_pins[0]	transitions[0x1=>0x0]	1047532	1			T21	10032		T22	8720		T24	54
all_pins[1]	values[0x0]	2773134	1			T21	26467		T22	23435		T23	1
all_pins[1]	values[0x1]	1696109	1			T21	16777		T22	14724		T24	111
all_pins[1]	transitions[0x0=>0x1]	1016916	1			T21	10200		T22	8949		T24	72
all_pins[1]	transitions[0x1=>0x0]	1013874	1			T21	9255		T22	8713		T24	51
all_pins[2]	values[0x0]	2774955	1			T21	27956		T22	23486		T23	1
all_pins[2]	values[0x1]	1694288	1			T21	15288		T22	14673		T24	80
all_pins[2]	transitions[0x0=>0x1]	1012738	1			T21	8998		T22	8641		T24	39
all_pins[2]	transitions[0x1=>0x0]	1014559	1			T21	10487		T22	8692		T24	70
all_pins[3]	values[0x0]	2781342	1			T21	27020		T22	23178		T23	1
all_pins[3]	values[0x1]	1687901	1			T21	16224		T22	14981		T24	115
all_pins[3]	transitions[0x0=>0x1]	1010663	1			T21	10098		T22	8642		T24	83
all_pins[3]	transitions[0x1=>0x0]	1017050	1			T21	9162		T22	8334		T24	48
all_pins[4]	values[0x0]	2776854	1			T21	27366		T22	23725		T23	1
all_pins[4]	values[0x1]	1692389	1			T21	15878		T22	14434		T24	90
all_pins[4]	transitions[0x0=>0x1]	1012985	1			T21	9495		T22	8311		T24	45
all_pins[4]	transitions[0x1=>0x0]	1008497	1			T21	9841		T22	8858		T24	70
all_pins[5]	values[0x0]	2775163	1			T21	26889		T22	24233		T23	1
all_pins[5]	values[0x1]	1694080	1			T21	16355		T22	13926		T24	120
all_pins[5]	transitions[0x0=>0x1]	1015991	1			T21	9970		T22	8512		T24	51
all_pins[5]	transitions[0x1=>0x0]	1014300	1			T21	9493		T22	9020		T24	21
all_pins[6]	values[0x0]	2777081	1			T21	26543		T22	22988		T23	1
all_pins[6]	values[0x1]	1692162	1			T21	16701		T22	15171		T24	86
all_pins[6]	transitions[0x0=>0x1]	1015476	1			T21	10211		T22	9291		T24	35
all_pins[6]	transitions[0x1=>0x0]	1017394	1			T21	9865		T22	8046		T24	69
all_pins[7]	values[0x0]	2783970	1			T21	26987		T22	23882		T23	1
all_pins[7]	values[0x1]	1685273	1			T21	16257		T22	14277		T24	74
all_pins[7]	transitions[0x0=>0x1]	1008332	1			T21	9652		T22	8411		T24	43
all_pins[7]	transitions[0x1=>0x0]	1015221	1			T21	10096		T22	9305		T24	55
all_pins[8]	values[0x0]	2777399	1			T21	26879		T22	23489		T23	1
all_pins[8]	values[0x1]	1691844	1			T21	16365		T22	14670		T24	66
all_pins[8]	transitions[0x0=>0x1]	1016276	1			T21	9858		T22	8835		T24	34
all_pins[8]	transitions[0x1=>0x0]	1009705	1			T21	9750		T22	8442		T24	42
all_pins[9]	values[0x0]	2778357	1			T21	26552		T22	24213		T23	1
all_pins[9]	values[0x1]	1690886	1			T21	16692		T22	13946		T24	104
all_pins[9]	transitions[0x0=>0x1]	1012437	1			T21	10006		T22	8491		T24	72
all_pins[9]	transitions[0x1=>0x0]	1013395	1			T21	9679		T22	9215		T24	34
all_pins[10]	values[0x0]	2771276	1			T21	26322		T22	23552		T23	1
all_pins[10]	values[0x1]	1697967	1			T21	16922		T22	14607		T24	86
all_pins[10]	transitions[0x0=>0x1]	1016575	1			T21	9990		T22	9176		T24	27
all_pins[10]	transitions[0x1=>0x0]	1009494	1			T21	9760		T22	8515		T24	45
all_pins[11]	values[0x0]	2774861	1			T21	27217		T22	23410		T23	1
all_pins[11]	values[0x1]	1694382	1			T21	16027		T22	14749		T24	89
all_pins[11]	transitions[0x0=>0x1]	1010069	1			T21	9382		T22	8928		T24	54
all_pins[11]	transitions[0x1=>0x0]	1013654	1			T21	10277		T22	8786		T24	51
all_pins[12]	values[0x0]	2776226	1			T21	26420		T22	24190		T23	1
all_pins[12]	values[0x1]	1693017	1			T21	16824		T22	13969		T24	89
all_pins[12]	transitions[0x0=>0x1]	1014139	1			T21	10226		T22	8410		T24	46
all_pins[12]	transitions[0x1=>0x0]	1015504	1			T21	9429		T22	9190		T24	46
all_pins[13]	values[0x0]	2778500	1			T21	27721		T22	23626		T23	1
all_pins[13]	values[0x1]	1690743	1			T21	15523		T22	14533		T24	84
all_pins[13]	transitions[0x0=>0x1]	1013531	1			T21	9153		T22	8793		T24	51
all_pins[13]	transitions[0x1=>0x0]	1015805	1			T21	10454		T22	8229		T24	56
all_pins[14]	values[0x0]	2775340	1			T21	26521		T22	23433		T23	1
all_pins[14]	values[0x1]	1693903	1			T21	16723		T22	14726		T24	70
all_pins[14]	transitions[0x0=>0x1]	1015229	1			T21	10353		T22	8734		T24	38
all_pins[14]	transitions[0x1=>0x0]	1012069	1			T21	9153		T22	8541		T24	52
all_pins[15]	values[0x0]	2777861	1			T21	26577		T22	23409		T23	1
all_pins[15]	values[0x1]	1691382	1			T21	16667		T22	14750		T24	74
all_pins[15]	transitions[0x0=>0x1]	1012337	1			T21	9782		T22	9010		T24	47
all_pins[15]	transitions[0x1=>0x0]	1014858	1			T21	9838		T22	8986		T24	43
all_pins[16]	values[0x0]	2772721	1			T21	26821		T22	23751		T23	1
all_pins[16]	values[0x1]	1696522	1			T21	16423		T22	14408		T24	73
all_pins[16]	transitions[0x0=>0x1]	1014414	1			T21	9745		T22	8492		T24	54
all_pins[16]	transitions[0x1=>0x0]	1009274	1			T21	9989		T22	8834		T24	55
all_pins[17]	values[0x0]	2776192	1			T21	26806		T22	23375		T23	1
all_pins[17]	values[0x1]	1693051	1			T21	16438		T22	14784		T24	86
all_pins[17]	transitions[0x0=>0x1]	1011937	1			T21	9619		T22	8876		T24	58
all_pins[17]	transitions[0x1=>0x0]	1015408	1			T21	9604		T22	8500		T24	45
all_pins[18]	values[0x0]	2777701	1			T21	26920		T22	23591		T23	1
all_pins[18]	values[0x1]	1691542	1			T21	16324		T22	14568		T24	84
all_pins[18]	transitions[0x0=>0x1]	1010439	1			T21	9739		T22	8664		T24	57
all_pins[18]	transitions[0x1=>0x0]	1011948	1			T21	9853		T22	8880		T24	59
all_pins[19]	values[0x0]	2779238	1			T21	26716		T22	22809		T23	1
all_pins[19]	values[0x1]	1690005	1			T21	16528		T22	15350		T24	81
all_pins[19]	transitions[0x0=>0x1]	1014384	1			T21	10033		T22	9021		T24	48
all_pins[19]	transitions[0x1=>0x0]	1015921	1			T21	9829		T22	8239		T24	51
all_pins[20]	values[0x0]	2779481	1			T21	27150		T22	22934		T23	1
all_pins[20]	values[0x1]	1689762	1			T21	16094		T22	15225		T24	86
all_pins[20]	transitions[0x0=>0x1]	1012191	1			T21	9728		T22	8886		T24	55
all_pins[20]	transitions[0x1=>0x0]	1012434	1			T21	10162		T22	9011		T24	50
all_pins[21]	values[0x0]	2774840	1			T21	26676		T22	23776		T23	1
all_pins[21]	values[0x1]	1694403	1			T21	16568		T22	14383		T24	87
all_pins[21]	transitions[0x0=>0x1]	1013685	1			T21	9997		T22	8316		T24	46
all_pins[21]	transitions[0x1=>0x0]	1009044	1			T21	9523		T22	9158		T24	45
all_pins[22]	values[0x0]	2772162	1			T21	26967		T22	24251		T23	1
all_pins[22]	values[0x1]	1697081	1			T21	16277		T22	13908		T24	96
all_pins[22]	transitions[0x0=>0x1]	1013737	1			T21	9926		T22	8431		T24	52
all_pins[22]	transitions[0x1=>0x0]	1011059	1			T21	10217		T22	8906		T24	43
all_pins[23]	values[0x0]	2775205	1			T21	27413		T22	23844		T23	1
all_pins[23]	values[0x1]	1694038	1			T21	15831		T22	14315		T24	96
all_pins[23]	transitions[0x0=>0x1]	1009767	1			T21	9748		T22	8696		T24	44
all_pins[23]	transitions[0x1=>0x0]	1012810	1			T21	10194		T22	8289		T24	44
all_pins[24]	values[0x0]	2774739	1			T21	26863		T22	23999		T23	1
all_pins[24]	values[0x1]	1694504	1			T21	16381		T22	14160		T24	88
all_pins[24]	transitions[0x0=>0x1]	1012493	1			T21	10044		T22	8687		T24	44
all_pins[24]	transitions[0x1=>0x0]	1012027	1			T21	9494		T22	8842		T24	52
all_pins[25]	values[0x0]	2776818	1			T21	26726		T22	23806		T23	1
all_pins[25]	values[0x1]	1692425	1			T21	16518		T22	14353		T24	64
all_pins[25]	transitions[0x0=>0x1]	1011919	1			T21	9946		T22	8658		T24	39
all_pins[25]	transitions[0x1=>0x0]	1013998	1			T21	9809		T22	8465		T24	63
all_pins[26]	values[0x0]	2774554	1			T21	26809		T22	23658		T23	1
all_pins[26]	values[0x1]	1694689	1			T21	16435		T22	14501		T24	77
all_pins[26]	transitions[0x0=>0x1]	1014079	1			T21	9667		T22	8550		T24	48
all_pins[26]	transitions[0x1=>0x0]	1011815	1			T21	9750		T22	8402		T24	35
all_pins[27]	values[0x0]	2771959	1			T21	26305		T22	23405		T23	1
all_pins[27]	values[0x1]	1697284	1			T21	16939		T22	14754		T24	94
all_pins[27]	transitions[0x0=>0x1]	1016964	1			T21	9942		T22	8752		T24	63
all_pins[27]	transitions[0x1=>0x0]	1014369	1			T21	9438		T22	8499		T24	46
all_pins[28]	values[0x0]	2775538	1			T21	26769		T22	23824		T23	1
all_pins[28]	values[0x1]	1693705	1			T21	16475		T22	14335		T24	98
all_pins[28]	transitions[0x0=>0x1]	1011783	1			T21	9620		T22	8643		T24	50
all_pins[28]	transitions[0x1=>0x0]	1015362	1			T21	10084		T22	9062		T24	46
all_pins[29]	values[0x0]	2773507	1			T21	26810		T22	23835		T23	1
all_pins[29]	values[0x1]	1695736	1			T21	16434		T22	14324		T24	104
all_pins[29]	transitions[0x0=>0x1]	1015825	1			T21	9680		T22	8575		T24	57
all_pins[29]	transitions[0x1=>0x0]	1013794	1			T21	9721		T22	8586		T24	51
all_pins[30]	values[0x0]	2780795	1			T21	26819		T22	23770		T23	1
all_pins[30]	values[0x1]	1688448	1			T21	16425		T22	14389		T24	91
all_pins[30]	transitions[0x0=>0x1]	1009971	1			T21	9902		T22	8814		T24	30
all_pins[30]	transitions[0x1=>0x0]	1017259	1			T21	9911		T22	8749		T24	43
all_pins[31]	values[0x0]	2775107	1			T21	26975		T22	23902		T23	1
all_pins[31]	values[0x1]	1694136	1			T21	16269		T22	14257		T24	80
all_pins[31]	transitions[0x0=>0x1]	1017303	1			T21	9868		T22	8704		T24	49
all_pins[31]	transitions[0x1=>0x0]	1011615	1			T21	10024		T22	8836		T24	60