Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[1]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[2]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[3]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[4]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[5]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[6]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[7]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[8]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[9]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[10]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[11]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[12]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[13]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[14]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[15]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[16]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[17]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[18]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[19]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[20]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[21]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[22]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[23]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[24]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[25]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[26]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[27]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[28]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[29]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[30]	14604595	1			T21	111212		T22	123833		T23	792
bins_for_gpio_bits[31]	14604595	1			T21	111212		T22	123833		T23	792

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

277213936

1

T21

127017

T22

137418

T23

19420

auto[1]

190133104

1

T21

228861

T22

258847

T23

5924

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

372943600

1

T21

283823

T22

310673

T23

18051

auto[1]

94403440

1

T21

720550

T22

855922

T23

7293

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345889295

1

T21

261878

T22

284064

T23

12162

auto[1]

121457745

1

T21

940003

T22

112200

T23

13182

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5341587	1			T21	26948		T22	27878		T23	227
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3992286	1			T21	43476		T22	47202		T23	23
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1482612	1			T21	11442		T22	13433		T23	107
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1824887	1			T21	1278		T22	1584		T23	266
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	493851	1			T21	16704		T22	20402		T23	39
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1469372	1			T21	11364		T22	13334		T23	130
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5353806	1			T21	27006		T22	27780		T23	333
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3970196	1			T21	43131		T22	47250		T23	45
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1485011	1			T21	11632		T22	13711		T23	122
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1829379	1			T21	1266		T22	1544		T23	181
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	497654	1			T21	16879		T22	20318		T23	28
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1468549	1			T21	11298		T22	13230		T23	83
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5352580	1			T21	27188		T22	27906		T23	243
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3976298	1			T21	43007		T22	47581		T23	47
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1485437	1			T21	10821		T22	13312		T23	133
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1821148	1			T21	1291		T22	1610		T23	229
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	496323	1			T21	17479		T22	20242		T23	24
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1472809	1			T21	11426		T22	13182		T23	116
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5338177	1			T21	27083		T22	28059		T23	310
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3986233	1			T21	44112		T22	47216		T23	44
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1485842	1			T21	10903		T22	13677		T23	141
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1830064	1			T21	1144		T22	1657		T23	163
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	493639	1			T21	17136		T22	19965		T23	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1470640	1			T21	10834		T22	13259		T23	117
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5346926	1			T21	27111		T22	27832		T23	276
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3984001	1			T21	43917		T22	47172		T23	39
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1489822	1			T21	11013		T22	13690		T23	139
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1824693	1			T21	1152		T22	1572		T23	201
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	491815	1			T21	17044		T22	20057		T23	33
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1467338	1			T21	10975		T22	13510		T23	104
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5335476	1			T21	27202		T22	27913		T23	199
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3979101	1			T21	43421		T22	47111		T23	25
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1483958	1			T21	11648		T22	13445		T23	162
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1835484	1			T21	1186		T22	1653		T23	243
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	495919	1			T21	16550		T22	20409		T23	29
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1474657	1			T21	11205		T22	13302		T23	134
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5346655	1			T21	27110		T22	27711		T23	251
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3973300	1			T21	43141		T22	46812		T23	29
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1480508	1			T21	11447		T22	13526		T23	98
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1835337	1			T21	1352		T22	1673		T23	267
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	497046	1			T21	17187		T22	20741		T23	25
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1471749	1			T21	10975		T22	13370		T23	122
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5356550	1			T21	27212		T22	27752		T23	153
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3969537	1			T21	43187		T22	47647		T23	14
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1482394	1			T21	11156		T22	13605		T23	72
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1829366	1			T21	1279		T22	1538		T23	351
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	498085	1			T21	16994		T22	20216		T23	52
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1468663	1			T21	11384		T22	13075		T23	150
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5345168	1			T21	26869		T22	27989		T23	307
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3978935	1			T21	43081		T22	47095		T23	28
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1490193	1			T21	11028		T22	13684		T23	72
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1826595	1			T21	1458		T22	1559		T23	244
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	495753	1			T21	17483		T22	20228		T23	35
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1467951	1			T21	11293		T22	13278		T23	106
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5341235	1			T21	27215		T22	27950		T23	266
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3980619	1			T21	42576		T22	47643		T23	24
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1474319	1			T21	11267		T22	13478		T23	83
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1836726	1			T21	1301		T22	1567		T23	257
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	497858	1			T21	17276		T22	20344		T23	37
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1473838	1			T21	11577		T22	12851		T23	125
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5348244	1			T21	27153		T22	27898		T23	224
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3971271	1			T21	42931		T22	46933		T23	20
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1483331	1			T21	11084		T22	13439		T23	72
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1835771	1			T21	1270		T22	1622		T23	298
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	495249	1			T21	16808		T22	20392		T23	49
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1470729	1			T21	11966		T22	13549		T23	129
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5348181	1			T21	27186		T22	27954		T23	217
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3973122	1			T21	43570		T22	47379		T23	28
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1483790	1			T21	12110		T22	13209		T23	85
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1832255	1			T21	1230		T22	1522		T23	284
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	494308	1			T21	15911		T22	20050		T23	39
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1472939	1			T21	11205		T22	13719		T23	139
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5345431	1			T21	26998		T22	27736		T23	222
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3979257	1			T21	43508		T22	47396		T23	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1480687	1			T21	11385		T22	14076		T23	74
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1834724	1			T21	1428		T22	1600		T23	267
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	494738	1			T21	17181		T22	19555		T23	34
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1469758	1			T21	10712		T22	13470		T23	161
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5340159	1			T21	27027		T22	27820		T23	203
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3988224	1			T21	43467		T22	47099		T23	29
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1486508	1			T21	11034		T22	13678		T23	115
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1827040	1			T21	1210		T22	1620		T23	270
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	492730	1			T21	17071		T22	20034		T23	32
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1469934	1			T21	11403		T22	13582		T23	143
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5346443	1			T21	27110		T22	27970		T23	249
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3979919	1			T21	43328		T22	47615		T23	37
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1484321	1			T21	11571		T22	13219		T23	121
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1829018	1			T21	1280		T22	1449		T23	269
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	491817	1			T21	16990		T22	20489		T23	29
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1473077	1			T21	10933		T22	13091		T23	87
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5351602	1			T21	27154		T22	27855		T23	244
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3972911	1			T21	43618		T22	47913		T23	29
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1485487	1			T21	11065		T22	13920		T23	113
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1827521	1			T21	1295		T22	1577		T23	234
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	495994	1			T21	16846		T22	19751		T23	39
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1471080	1			T21	11234		T22	12817		T23	133
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5347797	1			T21	27062		T22	27947		T23	288
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3978911	1			T21	43638		T22	48011		T23	47
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1479641	1			T21	11151		T22	12994		T23	141
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1834459	1			T21	1321		T22	1457		T23	198
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	496711	1			T21	17052		T22	20395		T23	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1467076	1			T21	10988		T22	13029		T23	90
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5356295	1			T21	27207		T22	27928		T23	232
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3974874	1			T21	43531		T22	47048		T23	28
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1473600	1			T21	11711		T22	13513		T23	81
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1837122	1			T21	1302		T22	1578		T23	289
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	492878	1			T21	16598		T22	20247		T23	31
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1469826	1			T21	10863		T22	13519		T23	131
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5356063	1			T21	27278		T22	27792		T23	222
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3973062	1			T21	43188		T22	47035		T23	38
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1481958	1			T21	12021		T22	13459		T23	96
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1833178	1			T21	1310		T22	1688		T23	291
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	492262	1			T21	16195		T22	20418		T23	29
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1468072	1			T21	11220		T22	13441		T23	116
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5342467	1			T21	27067		T22	27776		T23	249
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3988326	1			T21	43838		T22	47364		T23	41
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1479904	1			T21	11629		T22	13350		T23	72
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1832952	1			T21	1249		T22	1508		T23	317
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	495896	1			T21	16749		T22	20300		T23	32
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1465050	1			T21	10680		T22	13535		T23	81
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5350591	1			T21	27086		T22	28099		T23	267
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3977460	1			T21	43467		T22	47474		T23	22
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1479150	1			T21	11586		T22	13432		T23	87
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1832383	1			T21	1266		T22	1516		T23	271
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	496961	1			T21	16383		T22	20184		T23	35
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1468050	1			T21	11424		T22	13128		T23	110
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5353089	1			T21	27080		T22	27995		T23	228
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3979183	1			T21	43481		T22	47502		T23	32
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1485388	1			T21	11315		T22	13611		T23	96
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1828886	1			T21	1220		T22	1478		T23	270
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	492352	1			T21	16635		T22	19818		T23	38
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1465697	1			T21	11481		T22	13429		T23	128
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5361048	1			T21	27339		T22	27652		T23	266
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3964576	1			T21	44050		T22	47294		T23	29
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1474651	1			T21	10681		T22	13571		T23	136
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1839203	1			T21	1273		T22	1682		T23	226
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	497923	1			T21	16918		T22	20035		T23	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1467194	1			T21	10951		T22	13599		T23	104
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5353074	1			T21	27176		T22	27939		T23	256
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3979817	1			T21	43121		T22	48134		T23	39
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1477520	1			T21	11164		T22	13851		T23	121
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1829394	1			T21	1316		T22	1481		T23	225
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	496059	1			T21	17173		T22	19388		T23	37
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1468731	1			T21	11262		T22	13040		T23	114
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5364845	1			T21	27021		T22	28066		T23	249
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3967895	1			T21	42972		T22	47703		T23	44
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1480432	1			T21	11386		T22	13692		T23	176
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1832165	1			T21	1349		T22	1488		T23	168
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	493886	1			T21	17453		T22	19624		T23	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1465372	1			T21	11031		T22	13260		T23	136
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5351373	1			T21	26970		T22	27973		T23	210
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3978585	1			T21	43617		T22	48240		T23	19
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1479752	1			T21	10954		T22	13620		T23	98
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1835007	1			T21	1309		T22	1520		T23	303
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	497348	1			T21	17146		T22	19771		T23	42
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1462530	1			T21	11216		T22	12709		T23	120
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5341056	1			T21	27163		T22	27863		T23	230
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3987618	1			T21	43364		T22	48137		T23	31
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1478186	1			T21	11388		T22	13158		T23	80
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1835375	1			T21	1285		T22	1452		T23	274
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	498507	1			T21	16575		T22	20107		T23	45
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1463853	1			T21	11437		T22	13116		T23	132
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5349181	1			T21	27023		T22	28007		T23	231
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3974678	1			T21	43370		T22	46881		T23	33
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1479712	1			T21	11580		T22	13410		T23	113
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1835555	1			T21	1185		T22	1570		T23	246
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	496820	1			T21	16800		T22	20546		T23	34
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1468649	1			T21	11254		T22	13419		T23	135
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5356933	1			T21	27161		T22	27923		T23	187
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3977287	1			T21	43471		T22	47196		T23	12
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1482415	1			T21	11608		T22	13064		T23	74
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1827167	1			T21	1230		T22	1669		T23	314
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	494830	1			T21	16312		T22	20526		T23	50
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1465963	1			T21	11430		T22	13455		T23	155
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5346306	1			T21	26912		T22	28108		T23	234
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3987742	1			T21	43679		T22	47020		T23	26
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1480540	1			T21	11240		T22	13028		T23	112
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1830697	1			T21	1296		T22	1574		T23	277
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	492657	1			T21	16946		T22	20751		T23	39
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1466653	1			T21	11139		T22	13352		T23	104
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5356423	1			T21	27042		T22	27984		T23	226
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3976422	1			T21	43589		T22	47497		T23	28
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1476624	1			T21	10885		T22	13347		T23	125
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1836497	1			T21	1317		T22	1576		T23	287
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	494525	1			T21	17108		T22	20582		T23	40
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1464104	1			T21	11271		T22	12847		T23	86
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5357204	1			T21	27041		T22	27675		T23	211
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3972467	1			T21	43676		T22	47097		T23	23
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1479524	1			T21	11153		T22	13020		T23	148
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1838706	1			T21	1267		T22	1648		T23	265
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	496374	1			T21	17014		T22	21190		T23	38
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1460320	1			T21	11061		T22	13203		T23	107

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal