Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8482745 |
1 |
|
|
T21 |
67385 |
|
T22 |
68968 |
|
T23 |
416 |
| auto[1] |
6351924 |
1 |
|
|
T21 |
50025 |
|
T22 |
55682 |
|
T24 |
164 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027891 |
1 |
|
|
T21 |
110788 |
|
T22 |
117391 |
|
T23 |
416 |
| auto[1] |
806778 |
1 |
|
|
T21 |
6622 |
|
T22 |
7259 |
|
T24 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8513676 |
1 |
|
|
T21 |
66549 |
|
T22 |
69805 |
|
T23 |
416 |
| auto[1] |
6320993 |
1 |
|
|
T21 |
50861 |
|
T22 |
54845 |
|
T24 |
177 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2772539 |
1 |
|
|
T21 |
23071 |
|
T22 |
23740 |
|
T24 |
94 |
| auto[1] |
auto[0] |
auto[1] |
406372 |
1 |
|
|
T21 |
3456 |
|
T22 |
3593 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2741676 |
1 |
|
|
T21 |
21168 |
|
T22 |
23846 |
|
T24 |
72 |
| auto[1] |
auto[1] |
auto[1] |
400406 |
1 |
|
|
T21 |
3166 |
|
T22 |
3666 |
|
T24 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8488597 |
1 |
|
|
T21 |
64146 |
|
T22 |
68002 |
|
T23 |
416 |
| auto[1] |
6346072 |
1 |
|
|
T21 |
53264 |
|
T22 |
56648 |
|
T24 |
198 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14023503 |
1 |
|
|
T21 |
110835 |
|
T22 |
117103 |
|
T23 |
416 |
| auto[1] |
811166 |
1 |
|
|
T21 |
6575 |
|
T22 |
7547 |
|
T24 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8467084 |
1 |
|
|
T21 |
65841 |
|
T22 |
67396 |
|
T23 |
416 |
| auto[1] |
6367585 |
1 |
|
|
T21 |
51569 |
|
T22 |
57254 |
|
T24 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2783488 |
1 |
|
|
T21 |
22307 |
|
T22 |
24665 |
|
T24 |
70 |
| auto[1] |
auto[0] |
auto[1] |
407526 |
1 |
|
|
T21 |
3189 |
|
T22 |
3661 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2772931 |
1 |
|
|
T21 |
22687 |
|
T22 |
25042 |
|
T24 |
117 |
| auto[1] |
auto[1] |
auto[1] |
403640 |
1 |
|
|
T21 |
3386 |
|
T22 |
3886 |
|
T24 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8486225 |
1 |
|
|
T21 |
64182 |
|
T22 |
69227 |
|
T23 |
416 |
| auto[1] |
6348444 |
1 |
|
|
T21 |
53228 |
|
T22 |
55423 |
|
T24 |
178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14028031 |
1 |
|
|
T21 |
110899 |
|
T22 |
116925 |
|
T23 |
416 |
| auto[1] |
806638 |
1 |
|
|
T21 |
6511 |
|
T22 |
7725 |
|
T24 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8503356 |
1 |
|
|
T21 |
66529 |
|
T22 |
66989 |
|
T23 |
416 |
| auto[1] |
6331313 |
1 |
|
|
T21 |
50881 |
|
T22 |
57661 |
|
T24 |
170 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2763524 |
1 |
|
|
T21 |
22131 |
|
T22 |
25815 |
|
T24 |
79 |
| auto[1] |
auto[0] |
auto[1] |
403259 |
1 |
|
|
T21 |
3229 |
|
T22 |
4043 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2761151 |
1 |
|
|
T21 |
22239 |
|
T22 |
24121 |
|
T24 |
80 |
| auto[1] |
auto[1] |
auto[1] |
403379 |
1 |
|
|
T21 |
3282 |
|
T22 |
3682 |
|
T24 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8489830 |
1 |
|
|
T21 |
66048 |
|
T22 |
67774 |
|
T23 |
416 |
| auto[1] |
6344839 |
1 |
|
|
T21 |
51362 |
|
T22 |
56876 |
|
T24 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14022285 |
1 |
|
|
T21 |
110491 |
|
T22 |
117625 |
|
T23 |
416 |
| auto[1] |
812384 |
1 |
|
|
T21 |
6919 |
|
T22 |
7025 |
|
T24 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8466028 |
1 |
|
|
T21 |
64696 |
|
T22 |
70309 |
|
T23 |
416 |
| auto[1] |
6368641 |
1 |
|
|
T21 |
52714 |
|
T22 |
54341 |
|
T24 |
169 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2783630 |
1 |
|
|
T21 |
23457 |
|
T22 |
23072 |
|
T24 |
62 |
| auto[1] |
auto[0] |
auto[1] |
407295 |
1 |
|
|
T21 |
3530 |
|
T22 |
3421 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2772627 |
1 |
|
|
T21 |
22338 |
|
T22 |
24244 |
|
T24 |
97 |
| auto[1] |
auto[1] |
auto[1] |
405089 |
1 |
|
|
T21 |
3389 |
|
T22 |
3604 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477754 |
1 |
|
|
T21 |
63821 |
|
T22 |
69966 |
|
T23 |
416 |
| auto[1] |
6356915 |
1 |
|
|
T21 |
53589 |
|
T22 |
54684 |
|
T24 |
165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14024092 |
1 |
|
|
T21 |
110483 |
|
T22 |
116934 |
|
T23 |
416 |
| auto[1] |
810577 |
1 |
|
|
T21 |
6927 |
|
T22 |
7716 |
|
T24 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8487179 |
1 |
|
|
T21 |
65609 |
|
T22 |
66229 |
|
T23 |
416 |
| auto[1] |
6347490 |
1 |
|
|
T21 |
51801 |
|
T22 |
58421 |
|
T24 |
112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2766519 |
1 |
|
|
T21 |
22062 |
|
T22 |
27297 |
|
T24 |
34 |
| auto[1] |
auto[0] |
auto[1] |
404596 |
1 |
|
|
T21 |
3408 |
|
T22 |
4226 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2770394 |
1 |
|
|
T21 |
22812 |
|
T22 |
23408 |
|
T24 |
70 |
| auto[1] |
auto[1] |
auto[1] |
405981 |
1 |
|
|
T21 |
3519 |
|
T22 |
3490 |
|
T24 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8492484 |
1 |
|
|
T21 |
67675 |
|
T22 |
69213 |
|
T23 |
416 |
| auto[1] |
6342185 |
1 |
|
|
T21 |
49735 |
|
T22 |
55437 |
|
T24 |
188 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14028511 |
1 |
|
|
T21 |
110402 |
|
T22 |
117345 |
|
T23 |
416 |
| auto[1] |
806158 |
1 |
|
|
T21 |
7008 |
|
T22 |
7305 |
|
T24 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8510507 |
1 |
|
|
T21 |
65413 |
|
T22 |
68781 |
|
T23 |
416 |
| auto[1] |
6324162 |
1 |
|
|
T21 |
51997 |
|
T22 |
55869 |
|
T24 |
176 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2764499 |
1 |
|
|
T21 |
24419 |
|
T22 |
23797 |
|
T24 |
72 |
| auto[1] |
auto[0] |
auto[1] |
404493 |
1 |
|
|
T21 |
3808 |
|
T22 |
3653 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2753505 |
1 |
|
|
T21 |
20570 |
|
T22 |
24767 |
|
T24 |
95 |
| auto[1] |
auto[1] |
auto[1] |
401665 |
1 |
|
|
T21 |
3200 |
|
T22 |
3652 |
|
T24 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8499712 |
1 |
|
|
T21 |
64242 |
|
T22 |
66257 |
|
T23 |
416 |
| auto[1] |
6334957 |
1 |
|
|
T21 |
53168 |
|
T22 |
58393 |
|
T24 |
155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027507 |
1 |
|
|
T21 |
110619 |
|
T22 |
117194 |
|
T23 |
416 |
| auto[1] |
807162 |
1 |
|
|
T21 |
6791 |
|
T22 |
7456 |
|
T24 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8500225 |
1 |
|
|
T21 |
65438 |
|
T22 |
69099 |
|
T23 |
416 |
| auto[1] |
6334444 |
1 |
|
|
T21 |
51972 |
|
T22 |
55551 |
|
T24 |
144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2770096 |
1 |
|
|
T21 |
21978 |
|
T22 |
22675 |
|
T24 |
74 |
| auto[1] |
auto[0] |
auto[1] |
404404 |
1 |
|
|
T21 |
3336 |
|
T22 |
3441 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2757186 |
1 |
|
|
T21 |
23203 |
|
T22 |
25420 |
|
T24 |
59 |
| auto[1] |
auto[1] |
auto[1] |
402758 |
1 |
|
|
T21 |
3455 |
|
T22 |
4015 |
|
T24 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477040 |
1 |
|
|
T21 |
65053 |
|
T22 |
67743 |
|
T23 |
416 |
| auto[1] |
6357629 |
1 |
|
|
T21 |
52357 |
|
T22 |
56907 |
|
T24 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14025755 |
1 |
|
|
T21 |
110497 |
|
T22 |
117513 |
|
T23 |
416 |
| auto[1] |
808914 |
1 |
|
|
T21 |
6913 |
|
T22 |
7137 |
|
T24 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8489605 |
1 |
|
|
T21 |
65705 |
|
T22 |
69176 |
|
T23 |
416 |
| auto[1] |
6345064 |
1 |
|
|
T21 |
51705 |
|
T22 |
55474 |
|
T24 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2764167 |
1 |
|
|
T21 |
21861 |
|
T22 |
22766 |
|
T24 |
55 |
| auto[1] |
auto[0] |
auto[1] |
404730 |
1 |
|
|
T21 |
3340 |
|
T22 |
3317 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2771983 |
1 |
|
|
T21 |
22931 |
|
T22 |
25571 |
|
T24 |
79 |
| auto[1] |
auto[1] |
auto[1] |
404184 |
1 |
|
|
T21 |
3573 |
|
T22 |
3820 |
|
T24 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455890 |
1 |
|
|
T21 |
64534 |
|
T22 |
69648 |
|
T23 |
416 |
| auto[1] |
6378779 |
1 |
|
|
T21 |
52876 |
|
T22 |
55002 |
|
T24 |
160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14026736 |
1 |
|
|
T21 |
110503 |
|
T22 |
117616 |
|
T23 |
416 |
| auto[1] |
807933 |
1 |
|
|
T21 |
6907 |
|
T22 |
7034 |
|
T24 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8491908 |
1 |
|
|
T21 |
64339 |
|
T22 |
70168 |
|
T23 |
416 |
| auto[1] |
6342761 |
1 |
|
|
T21 |
53071 |
|
T22 |
54482 |
|
T24 |
180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2745712 |
1 |
|
|
T21 |
23263 |
|
T22 |
23739 |
|
T24 |
108 |
| auto[1] |
auto[0] |
auto[1] |
400090 |
1 |
|
|
T21 |
3458 |
|
T22 |
3560 |
|
T24 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2789116 |
1 |
|
|
T21 |
22901 |
|
T22 |
23709 |
|
T24 |
59 |
| auto[1] |
auto[1] |
auto[1] |
407843 |
1 |
|
|
T21 |
3449 |
|
T22 |
3474 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8470491 |
1 |
|
|
T21 |
64797 |
|
T22 |
68215 |
|
T23 |
416 |
| auto[1] |
6364178 |
1 |
|
|
T21 |
52613 |
|
T22 |
56435 |
|
T24 |
174 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14024607 |
1 |
|
|
T21 |
110599 |
|
T22 |
117520 |
|
T23 |
416 |
| auto[1] |
810062 |
1 |
|
|
T21 |
6811 |
|
T22 |
7130 |
|
T24 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8467880 |
1 |
|
|
T21 |
64702 |
|
T22 |
69346 |
|
T23 |
416 |
| auto[1] |
6366789 |
1 |
|
|
T21 |
52708 |
|
T22 |
55304 |
|
T24 |
159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2759138 |
1 |
|
|
T21 |
22886 |
|
T22 |
24202 |
|
T24 |
81 |
| auto[1] |
auto[0] |
auto[1] |
401395 |
1 |
|
|
T21 |
3419 |
|
T22 |
3679 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2797589 |
1 |
|
|
T21 |
23011 |
|
T22 |
23972 |
|
T24 |
68 |
| auto[1] |
auto[1] |
auto[1] |
408667 |
1 |
|
|
T21 |
3392 |
|
T22 |
3451 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8488491 |
1 |
|
|
T21 |
65104 |
|
T22 |
69382 |
|
T23 |
416 |
| auto[1] |
6346178 |
1 |
|
|
T21 |
52306 |
|
T22 |
55268 |
|
T24 |
157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027520 |
1 |
|
|
T21 |
110791 |
|
T22 |
117560 |
|
T23 |
416 |
| auto[1] |
807149 |
1 |
|
|
T21 |
6619 |
|
T22 |
7090 |
|
T24 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8497448 |
1 |
|
|
T21 |
66244 |
|
T22 |
69471 |
|
T23 |
416 |
| auto[1] |
6337221 |
1 |
|
|
T21 |
51166 |
|
T22 |
55179 |
|
T24 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2775757 |
1 |
|
|
T21 |
22524 |
|
T22 |
23958 |
|
T24 |
78 |
| auto[1] |
auto[0] |
auto[1] |
404833 |
1 |
|
|
T21 |
3313 |
|
T22 |
3467 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2754315 |
1 |
|
|
T21 |
22023 |
|
T22 |
24131 |
|
T24 |
60 |
| auto[1] |
auto[1] |
auto[1] |
402316 |
1 |
|
|
T21 |
3306 |
|
T22 |
3623 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8490957 |
1 |
|
|
T21 |
63476 |
|
T22 |
67739 |
|
T23 |
416 |
| auto[1] |
6343712 |
1 |
|
|
T21 |
53934 |
|
T22 |
56911 |
|
T24 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14034130 |
1 |
|
|
T21 |
110669 |
|
T22 |
117676 |
|
T23 |
416 |
| auto[1] |
800539 |
1 |
|
|
T21 |
6741 |
|
T22 |
6974 |
|
T24 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8535321 |
1 |
|
|
T21 |
65455 |
|
T22 |
70880 |
|
T23 |
416 |
| auto[1] |
6299348 |
1 |
|
|
T21 |
51955 |
|
T22 |
53770 |
|
T24 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2758723 |
1 |
|
|
T21 |
21985 |
|
T22 |
22679 |
|
T24 |
75 |
| auto[1] |
auto[0] |
auto[1] |
402408 |
1 |
|
|
T21 |
3283 |
|
T22 |
3367 |
|
T24 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2740086 |
1 |
|
|
T21 |
23229 |
|
T22 |
24117 |
|
T24 |
85 |
| auto[1] |
auto[1] |
auto[1] |
398131 |
1 |
|
|
T21 |
3458 |
|
T22 |
3607 |
|
T24 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456675 |
1 |
|
|
T21 |
67516 |
|
T22 |
67694 |
|
T23 |
416 |
| auto[1] |
6377994 |
1 |
|
|
T21 |
49894 |
|
T22 |
56956 |
|
T24 |
155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14019552 |
1 |
|
|
T21 |
110538 |
|
T22 |
117669 |
|
T23 |
416 |
| auto[1] |
815117 |
1 |
|
|
T21 |
6872 |
|
T22 |
6981 |
|
T24 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8454119 |
1 |
|
|
T21 |
64880 |
|
T22 |
69785 |
|
T23 |
416 |
| auto[1] |
6380550 |
1 |
|
|
T21 |
52530 |
|
T22 |
54865 |
|
T24 |
172 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2776606 |
1 |
|
|
T21 |
23900 |
|
T22 |
23310 |
|
T24 |
92 |
| auto[1] |
auto[0] |
auto[1] |
405907 |
1 |
|
|
T21 |
3624 |
|
T22 |
3436 |
|
T24 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2788827 |
1 |
|
|
T21 |
21758 |
|
T22 |
24574 |
|
T24 |
65 |
| auto[1] |
auto[1] |
auto[1] |
409210 |
1 |
|
|
T21 |
3248 |
|
T22 |
3545 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8481868 |
1 |
|
|
T21 |
65139 |
|
T22 |
68605 |
|
T23 |
416 |
| auto[1] |
6352801 |
1 |
|
|
T21 |
52271 |
|
T22 |
56045 |
|
T24 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027604 |
1 |
|
|
T21 |
110339 |
|
T22 |
117738 |
|
T23 |
416 |
| auto[1] |
807065 |
1 |
|
|
T21 |
7071 |
|
T22 |
6912 |
|
T24 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8496793 |
1 |
|
|
T21 |
64325 |
|
T22 |
70908 |
|
T23 |
416 |
| auto[1] |
6337876 |
1 |
|
|
T21 |
53085 |
|
T22 |
53742 |
|
T24 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767568 |
1 |
|
|
T21 |
22297 |
|
T22 |
23780 |
|
T24 |
58 |
| auto[1] |
auto[0] |
auto[1] |
403234 |
1 |
|
|
T21 |
3318 |
|
T22 |
3569 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2763243 |
1 |
|
|
T21 |
23717 |
|
T22 |
23050 |
|
T24 |
55 |
| auto[1] |
auto[1] |
auto[1] |
403831 |
1 |
|
|
T21 |
3753 |
|
T22 |
3343 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8483546 |
1 |
|
|
T21 |
63157 |
|
T22 |
69714 |
|
T23 |
416 |
| auto[1] |
6351123 |
1 |
|
|
T21 |
54253 |
|
T22 |
54936 |
|
T24 |
179 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14024235 |
1 |
|
|
T21 |
110488 |
|
T22 |
117246 |
|
T23 |
416 |
| auto[1] |
810434 |
1 |
|
|
T21 |
6922 |
|
T22 |
7404 |
|
T24 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8485906 |
1 |
|
|
T21 |
65442 |
|
T22 |
67861 |
|
T23 |
416 |
| auto[1] |
6348763 |
1 |
|
|
T21 |
51968 |
|
T22 |
56789 |
|
T24 |
156 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2748955 |
1 |
|
|
T21 |
21904 |
|
T22 |
25349 |
|
T24 |
77 |
| auto[1] |
auto[0] |
auto[1] |
402001 |
1 |
|
|
T21 |
3352 |
|
T22 |
3820 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2789374 |
1 |
|
|
T21 |
23142 |
|
T22 |
24036 |
|
T24 |
68 |
| auto[1] |
auto[1] |
auto[1] |
408433 |
1 |
|
|
T21 |
3570 |
|
T22 |
3584 |
|
T24 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8476948 |
1 |
|
|
T21 |
64638 |
|
T22 |
71041 |
|
T23 |
416 |
| auto[1] |
6357721 |
1 |
|
|
T21 |
52772 |
|
T22 |
53609 |
|
T24 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14028263 |
1 |
|
|
T21 |
110600 |
|
T22 |
117613 |
|
T23 |
416 |
| auto[1] |
806406 |
1 |
|
|
T21 |
6810 |
|
T22 |
7037 |
|
T24 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8516647 |
1 |
|
|
T21 |
64332 |
|
T22 |
70083 |
|
T23 |
416 |
| auto[1] |
6318022 |
1 |
|
|
T21 |
53078 |
|
T22 |
54567 |
|
T24 |
133 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757845 |
1 |
|
|
T21 |
23248 |
|
T22 |
24565 |
|
T24 |
56 |
| auto[1] |
auto[0] |
auto[1] |
401997 |
1 |
|
|
T21 |
3379 |
|
T22 |
3678 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2753771 |
1 |
|
|
T21 |
23020 |
|
T22 |
22965 |
|
T24 |
69 |
| auto[1] |
auto[1] |
auto[1] |
404409 |
1 |
|
|
T21 |
3431 |
|
T22 |
3359 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8461241 |
1 |
|
|
T21 |
66034 |
|
T22 |
68891 |
|
T23 |
416 |
| auto[1] |
6373428 |
1 |
|
|
T21 |
51376 |
|
T22 |
55759 |
|
T24 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027841 |
1 |
|
|
T21 |
110455 |
|
T22 |
117368 |
|
T23 |
416 |
| auto[1] |
806828 |
1 |
|
|
T21 |
6955 |
|
T22 |
7282 |
|
T24 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8505530 |
1 |
|
|
T21 |
64454 |
|
T22 |
68774 |
|
T23 |
416 |
| auto[1] |
6329139 |
1 |
|
|
T21 |
52956 |
|
T22 |
55876 |
|
T24 |
141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2751043 |
1 |
|
|
T21 |
24011 |
|
T22 |
24561 |
|
T24 |
51 |
| auto[1] |
auto[0] |
auto[1] |
402758 |
1 |
|
|
T21 |
3732 |
|
T22 |
3693 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2771268 |
1 |
|
|
T21 |
21990 |
|
T22 |
24033 |
|
T24 |
83 |
| auto[1] |
auto[1] |
auto[1] |
404070 |
1 |
|
|
T21 |
3223 |
|
T22 |
3589 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8468199 |
1 |
|
|
T21 |
64479 |
|
T22 |
69876 |
|
T23 |
416 |
| auto[1] |
6366470 |
1 |
|
|
T21 |
52931 |
|
T22 |
54774 |
|
T24 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14021445 |
1 |
|
|
T21 |
110476 |
|
T22 |
117498 |
|
T23 |
416 |
| auto[1] |
813224 |
1 |
|
|
T21 |
6934 |
|
T22 |
7152 |
|
T24 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8472539 |
1 |
|
|
T21 |
64843 |
|
T22 |
69653 |
|
T23 |
416 |
| auto[1] |
6362130 |
1 |
|
|
T21 |
52567 |
|
T22 |
54997 |
|
T24 |
148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2774664 |
1 |
|
|
T21 |
22617 |
|
T22 |
23952 |
|
T24 |
54 |
| auto[1] |
auto[0] |
auto[1] |
407251 |
1 |
|
|
T21 |
3444 |
|
T22 |
3617 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2774242 |
1 |
|
|
T21 |
23016 |
|
T22 |
23893 |
|
T24 |
86 |
| auto[1] |
auto[1] |
auto[1] |
405973 |
1 |
|
|
T21 |
3490 |
|
T22 |
3535 |
|
T24 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8504472 |
1 |
|
|
T21 |
64825 |
|
T22 |
68486 |
|
T23 |
416 |
| auto[1] |
6330197 |
1 |
|
|
T21 |
52585 |
|
T22 |
56164 |
|
T24 |
160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14025800 |
1 |
|
|
T21 |
110635 |
|
T22 |
117477 |
|
T23 |
416 |
| auto[1] |
808869 |
1 |
|
|
T21 |
6775 |
|
T22 |
7173 |
|
T24 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8480806 |
1 |
|
|
T21 |
65344 |
|
T22 |
69833 |
|
T23 |
416 |
| auto[1] |
6353863 |
1 |
|
|
T21 |
52066 |
|
T22 |
54817 |
|
T24 |
255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2785352 |
1 |
|
|
T21 |
22319 |
|
T22 |
24102 |
|
T24 |
126 |
| auto[1] |
auto[0] |
auto[1] |
406578 |
1 |
|
|
T21 |
3375 |
|
T22 |
3552 |
|
T24 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2759642 |
1 |
|
|
T21 |
22972 |
|
T22 |
23542 |
|
T24 |
113 |
| auto[1] |
auto[1] |
auto[1] |
402291 |
1 |
|
|
T21 |
3400 |
|
T22 |
3621 |
|
T24 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8486220 |
1 |
|
|
T21 |
64429 |
|
T22 |
70841 |
|
T23 |
416 |
| auto[1] |
6348449 |
1 |
|
|
T21 |
52981 |
|
T22 |
53809 |
|
T24 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14027737 |
1 |
|
|
T21 |
110918 |
|
T22 |
117362 |
|
T23 |
416 |
| auto[1] |
806932 |
1 |
|
|
T21 |
6492 |
|
T22 |
7288 |
|
T24 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8489361 |
1 |
|
|
T21 |
66425 |
|
T22 |
67873 |
|
T23 |
416 |
| auto[1] |
6345308 |
1 |
|
|
T21 |
50985 |
|
T22 |
56777 |
|
T24 |
145 |