Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T765 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4155211869 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:56 PM PDT 24 47393685 ps
T766 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1461409848 Apr 30 12:30:06 PM PDT 24 Apr 30 12:30:07 PM PDT 24 59650941 ps
T87 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1108033110 Apr 30 12:29:56 PM PDT 24 Apr 30 12:29:58 PM PDT 24 22180466 ps
T767 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3550757029 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:05 PM PDT 24 107370501 ps
T88 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4053118992 Apr 30 12:29:57 PM PDT 24 Apr 30 12:29:58 PM PDT 24 17221893 ps
T768 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3117167519 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:03 PM PDT 24 65738875 ps
T114 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2234983809 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:58 PM PDT 24 114525072 ps
T769 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.98555697 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:56 PM PDT 24 14572169 ps
T770 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2360484543 Apr 30 12:29:59 PM PDT 24 Apr 30 12:30:01 PM PDT 24 114051001 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4238911323 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 60796987 ps
T90 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3558733316 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:02 PM PDT 24 87158544 ps
T771 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2219541423 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:06 PM PDT 24 27156646 ps
T42 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.650917845 Apr 30 12:29:58 PM PDT 24 Apr 30 12:30:00 PM PDT 24 314393209 ps
T91 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.107990118 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:54 PM PDT 24 15285400 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2640839923 Apr 30 12:30:03 PM PDT 24 Apr 30 12:30:04 PM PDT 24 11840548 ps
T773 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3014808339 Apr 30 12:30:05 PM PDT 24 Apr 30 12:30:07 PM PDT 24 33565593 ps
T774 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1644469235 Apr 30 12:30:12 PM PDT 24 Apr 30 12:30:13 PM PDT 24 12565963 ps
T775 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.167900581 Apr 30 12:29:58 PM PDT 24 Apr 30 12:30:01 PM PDT 24 109320745 ps
T92 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3566824417 Apr 30 12:29:51 PM PDT 24 Apr 30 12:29:52 PM PDT 24 16546990 ps
T776 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3649561944 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:02 PM PDT 24 11067566 ps
T777 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2504847818 Apr 30 12:30:08 PM PDT 24 Apr 30 12:30:10 PM PDT 24 41817351 ps
T778 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1248208871 Apr 30 12:30:08 PM PDT 24 Apr 30 12:30:10 PM PDT 24 27701010 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3081815641 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:59 PM PDT 24 491559667 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_intr_test.580718934 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:55 PM PDT 24 49005987 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2706277894 Apr 30 12:29:51 PM PDT 24 Apr 30 12:29:53 PM PDT 24 38898958 ps
T782 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1647736711 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:10 PM PDT 24 22196883 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2586249988 Apr 30 12:29:58 PM PDT 24 Apr 30 12:30:00 PM PDT 24 171023203 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3225520458 Apr 30 12:30:02 PM PDT 24 Apr 30 12:30:03 PM PDT 24 18638835 ps
T785 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.876918429 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:53 PM PDT 24 133343274 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3485379207 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:07 PM PDT 24 46671598 ps
T787 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3901367606 Apr 30 12:29:49 PM PDT 24 Apr 30 12:29:51 PM PDT 24 97686710 ps
T788 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1324452589 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:12 PM PDT 24 164267325 ps
T789 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3059942054 Apr 30 12:30:08 PM PDT 24 Apr 30 12:30:09 PM PDT 24 38595503 ps
T93 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.153424743 Apr 30 12:29:50 PM PDT 24 Apr 30 12:29:51 PM PDT 24 15175613 ps
T790 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1139993285 Apr 30 12:29:53 PM PDT 24 Apr 30 12:29:57 PM PDT 24 515116444 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2465558427 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:03 PM PDT 24 33712142 ps
T792 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.945610507 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:55 PM PDT 24 177607208 ps
T793 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2642256414 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:02 PM PDT 24 33635605 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3895397769 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:58 PM PDT 24 178388598 ps
T795 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.13343499 Apr 30 12:29:56 PM PDT 24 Apr 30 12:29:58 PM PDT 24 216764351 ps
T796 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4288869371 Apr 30 12:29:59 PM PDT 24 Apr 30 12:30:00 PM PDT 24 41082682 ps
T43 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4066007121 Apr 30 12:29:56 PM PDT 24 Apr 30 12:29:58 PM PDT 24 271656118 ps
T44 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3002653509 Apr 30 12:30:07 PM PDT 24 Apr 30 12:30:09 PM PDT 24 634815938 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_intr_test.706092154 Apr 30 12:29:50 PM PDT 24 Apr 30 12:29:52 PM PDT 24 51979176 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.472429179 Apr 30 12:30:00 PM PDT 24 Apr 30 12:30:02 PM PDT 24 243083266 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_intr_test.17110439 Apr 30 12:29:56 PM PDT 24 Apr 30 12:29:58 PM PDT 24 19698855 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.489399468 Apr 30 12:30:00 PM PDT 24 Apr 30 12:30:03 PM PDT 24 41947926 ps
T801 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3591606084 Apr 30 12:30:05 PM PDT 24 Apr 30 12:30:06 PM PDT 24 58956169 ps
T49 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.961242919 Apr 30 12:29:59 PM PDT 24 Apr 30 12:30:01 PM PDT 24 211293271 ps
T94 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.511258114 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:56 PM PDT 24 113493069 ps
T802 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.801683265 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:02 PM PDT 24 20468596 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4224622201 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:56 PM PDT 24 30429526 ps
T804 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2166207293 Apr 30 12:30:00 PM PDT 24 Apr 30 12:30:01 PM PDT 24 42712856 ps
T95 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.109008294 Apr 30 12:29:53 PM PDT 24 Apr 30 12:29:54 PM PDT 24 39804551 ps
T805 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.634929335 Apr 30 12:29:51 PM PDT 24 Apr 30 12:29:52 PM PDT 24 43435326 ps
T806 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1381117012 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 16407043 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1309703041 Apr 30 12:29:57 PM PDT 24 Apr 30 12:29:58 PM PDT 24 20425560 ps
T808 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2756736023 Apr 30 12:30:06 PM PDT 24 Apr 30 12:30:09 PM PDT 24 33510882 ps
T809 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2334168989 Apr 30 12:30:11 PM PDT 24 Apr 30 12:30:12 PM PDT 24 13286163 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.129453794 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:21 PM PDT 24 309676109 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3102489911 Apr 30 12:29:51 PM PDT 24 Apr 30 12:29:52 PM PDT 24 32335726 ps
T812 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1478088567 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:10 PM PDT 24 18489181 ps
T813 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3635093449 Apr 30 12:30:02 PM PDT 24 Apr 30 12:30:03 PM PDT 24 81944848 ps
T814 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3180613142 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:12 PM PDT 24 51661716 ps
T815 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1516524533 Apr 30 12:30:05 PM PDT 24 Apr 30 12:30:06 PM PDT 24 20294675 ps
T816 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.90302436 Apr 30 12:29:57 PM PDT 24 Apr 30 12:29:59 PM PDT 24 36426484 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_intr_test.387570880 Apr 30 12:29:54 PM PDT 24 Apr 30 12:29:55 PM PDT 24 96103021 ps
T818 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1870973665 Apr 30 12:30:13 PM PDT 24 Apr 30 12:30:15 PM PDT 24 35640651 ps
T819 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3547872440 Apr 30 12:29:50 PM PDT 24 Apr 30 12:29:52 PM PDT 24 177375987 ps
T820 /workspace/coverage/cover_reg_top/29.gpio_intr_test.178143472 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:05 PM PDT 24 14161248 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2593484403 Apr 30 12:29:57 PM PDT 24 Apr 30 12:29:59 PM PDT 24 71015915 ps
T822 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1198528371 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:10 PM PDT 24 101937469 ps
T823 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1039034218 Apr 30 12:29:59 PM PDT 24 Apr 30 12:30:01 PM PDT 24 35564033 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.869229529 Apr 30 12:30:11 PM PDT 24 Apr 30 12:30:13 PM PDT 24 166132841 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.717373849 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:06 PM PDT 24 195405742 ps
T826 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1113671740 Apr 30 12:30:04 PM PDT 24 Apr 30 12:30:05 PM PDT 24 49484992 ps
T827 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.955807815 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:53 PM PDT 24 18487986 ps
T828 /workspace/coverage/cover_reg_top/31.gpio_intr_test.640453677 Apr 30 12:30:05 PM PDT 24 Apr 30 12:30:06 PM PDT 24 39774419 ps
T829 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1368929914 Apr 30 12:29:58 PM PDT 24 Apr 30 12:29:59 PM PDT 24 13646362 ps
T830 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1374378483 Apr 30 12:30:01 PM PDT 24 Apr 30 12:30:03 PM PDT 24 190665065 ps
T831 /workspace/coverage/cover_reg_top/44.gpio_intr_test.761650495 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 54184882 ps
T832 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3568231519 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 24322156 ps
T833 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1951897175 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:53 PM PDT 24 77124469 ps
T834 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3272475670 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:59 PM PDT 24 154736821 ps
T835 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3725424334 Apr 30 12:29:53 PM PDT 24 Apr 30 12:29:55 PM PDT 24 19029426 ps
T836 /workspace/coverage/cover_reg_top/43.gpio_intr_test.208903139 Apr 30 12:30:10 PM PDT 24 Apr 30 12:30:11 PM PDT 24 24708094 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_intr_test.423500809 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:56 PM PDT 24 18927943 ps
T838 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.884242348 Apr 30 12:29:53 PM PDT 24 Apr 30 12:29:55 PM PDT 24 68509771 ps
T839 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3978465656 Apr 30 12:30:10 PM PDT 24 Apr 30 12:30:12 PM PDT 24 37014749 ps
T840 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1983282886 Apr 30 12:30:13 PM PDT 24 Apr 30 12:30:14 PM PDT 24 14050964 ps
T841 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3476613431 Apr 30 12:29:58 PM PDT 24 Apr 30 12:30:00 PM PDT 24 25329325 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2805619375 Apr 30 12:29:52 PM PDT 24 Apr 30 12:29:53 PM PDT 24 44261038 ps
T843 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1820616851 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:33 PM PDT 24 90291766 ps
T844 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864856616 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:37 PM PDT 24 128388418 ps
T845 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2427000562 Apr 30 12:30:37 PM PDT 24 Apr 30 12:30:39 PM PDT 24 186239262 ps
T846 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2893237441 Apr 30 12:30:16 PM PDT 24 Apr 30 12:30:18 PM PDT 24 65431457 ps
T847 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3657220247 Apr 30 12:30:36 PM PDT 24 Apr 30 12:30:38 PM PDT 24 197390861 ps
T848 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23385163 Apr 30 12:30:25 PM PDT 24 Apr 30 12:30:27 PM PDT 24 77414204 ps
T849 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.146980489 Apr 30 12:30:22 PM PDT 24 Apr 30 12:30:24 PM PDT 24 37195782 ps
T850 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1859918927 Apr 30 12:30:36 PM PDT 24 Apr 30 12:30:38 PM PDT 24 74954618 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701384553 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:22 PM PDT 24 211766869 ps
T852 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1348086445 Apr 30 12:30:34 PM PDT 24 Apr 30 12:30:35 PM PDT 24 68098629 ps
T853 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3517382351 Apr 30 12:30:43 PM PDT 24 Apr 30 12:30:45 PM PDT 24 68264700 ps
T854 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2540538486 Apr 30 12:30:19 PM PDT 24 Apr 30 12:30:21 PM PDT 24 189766840 ps
T855 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2156073245 Apr 30 12:30:10 PM PDT 24 Apr 30 12:30:11 PM PDT 24 52413284 ps
T856 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3390335909 Apr 30 12:30:29 PM PDT 24 Apr 30 12:30:31 PM PDT 24 78037260 ps
T857 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.255383312 Apr 30 12:30:37 PM PDT 24 Apr 30 12:30:39 PM PDT 24 48906217 ps
T858 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2384098979 Apr 30 12:30:29 PM PDT 24 Apr 30 12:30:31 PM PDT 24 57374483 ps
T859 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503508481 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:33 PM PDT 24 454143554 ps
T860 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353273828 Apr 30 12:30:38 PM PDT 24 Apr 30 12:30:40 PM PDT 24 1419262121 ps
T861 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4195913662 Apr 30 12:30:16 PM PDT 24 Apr 30 12:30:18 PM PDT 24 77819796 ps
T862 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2767214333 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 233083987 ps
T863 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426267649 Apr 30 12:30:19 PM PDT 24 Apr 30 12:30:21 PM PDT 24 155180426 ps
T864 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2691299034 Apr 30 12:30:24 PM PDT 24 Apr 30 12:30:25 PM PDT 24 419044736 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.642962 Apr 30 12:30:11 PM PDT 24 Apr 30 12:30:13 PM PDT 24 572501406 ps
T866 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3599796762 Apr 30 12:30:21 PM PDT 24 Apr 30 12:30:23 PM PDT 24 306895045 ps
T867 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2127259440 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 157880494 ps
T868 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316568459 Apr 30 12:30:34 PM PDT 24 Apr 30 12:30:36 PM PDT 24 55204655 ps
T869 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1135669727 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:32 PM PDT 24 111684494 ps
T870 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408090028 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 35353495 ps
T871 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2172356172 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:36 PM PDT 24 43469754 ps
T872 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1525866619 Apr 30 12:30:46 PM PDT 24 Apr 30 12:30:49 PM PDT 24 93769780 ps
T873 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.606147517 Apr 30 12:30:32 PM PDT 24 Apr 30 12:30:34 PM PDT 24 39273631 ps
T874 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.96637116 Apr 30 12:30:32 PM PDT 24 Apr 30 12:30:34 PM PDT 24 146191517 ps
T875 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3670616101 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:37 PM PDT 24 37647106 ps
T876 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3959728105 Apr 30 12:30:28 PM PDT 24 Apr 30 12:30:29 PM PDT 24 164888629 ps
T877 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864447845 Apr 30 12:30:12 PM PDT 24 Apr 30 12:30:14 PM PDT 24 177501964 ps
T878 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1804761106 Apr 30 12:30:16 PM PDT 24 Apr 30 12:30:18 PM PDT 24 149636278 ps
T879 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2791843342 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 358776676 ps
T880 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4254499269 Apr 30 12:30:36 PM PDT 24 Apr 30 12:30:38 PM PDT 24 308253682 ps
T881 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4131144820 Apr 30 12:30:40 PM PDT 24 Apr 30 12:30:42 PM PDT 24 204131757 ps
T882 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2114567483 Apr 30 12:30:30 PM PDT 24 Apr 30 12:30:32 PM PDT 24 81100688 ps
T883 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.812761868 Apr 30 12:30:30 PM PDT 24 Apr 30 12:30:31 PM PDT 24 175027086 ps
T884 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4099075597 Apr 30 12:30:36 PM PDT 24 Apr 30 12:30:38 PM PDT 24 79281124 ps
T885 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3115091077 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 274719907 ps
T886 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1383821762 Apr 30 12:30:11 PM PDT 24 Apr 30 12:30:13 PM PDT 24 141363689 ps
T887 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2973401153 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:34 PM PDT 24 32741674 ps
T888 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1989808373 Apr 30 12:30:36 PM PDT 24 Apr 30 12:30:38 PM PDT 24 1077456258 ps
T889 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3474968403 Apr 30 12:30:21 PM PDT 24 Apr 30 12:30:22 PM PDT 24 129017913 ps
T890 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2995163216 Apr 30 12:30:17 PM PDT 24 Apr 30 12:30:19 PM PDT 24 89578845 ps
T891 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623320825 Apr 30 12:30:28 PM PDT 24 Apr 30 12:30:29 PM PDT 24 183270322 ps
T892 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.196482595 Apr 30 12:30:24 PM PDT 24 Apr 30 12:30:26 PM PDT 24 476493974 ps
T893 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.930781384 Apr 30 12:30:29 PM PDT 24 Apr 30 12:30:30 PM PDT 24 95363592 ps
T894 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1688934811 Apr 30 12:30:15 PM PDT 24 Apr 30 12:30:17 PM PDT 24 105852264 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2394737959 Apr 30 12:30:22 PM PDT 24 Apr 30 12:30:24 PM PDT 24 95301139 ps
T896 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2869986461 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 63973369 ps
T897 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1350419788 Apr 30 12:30:19 PM PDT 24 Apr 30 12:30:20 PM PDT 24 315527344 ps
T898 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3539530830 Apr 30 12:30:28 PM PDT 24 Apr 30 12:30:29 PM PDT 24 98301872 ps
T899 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3570887933 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:36 PM PDT 24 26841438 ps
T900 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2186445184 Apr 30 12:30:21 PM PDT 24 Apr 30 12:30:23 PM PDT 24 51949176 ps
T901 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3403829763 Apr 30 12:30:42 PM PDT 24 Apr 30 12:30:44 PM PDT 24 67639401 ps
T902 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3038981940 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:38 PM PDT 24 167057780 ps
T903 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577115912 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:33 PM PDT 24 94491713 ps
T904 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1126527346 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:32 PM PDT 24 168041410 ps
T905 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2062520705 Apr 30 12:30:31 PM PDT 24 Apr 30 12:30:32 PM PDT 24 55924349 ps
T906 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.579434516 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:21 PM PDT 24 55452339 ps
T907 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3445016186 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:22 PM PDT 24 379375093 ps
T908 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3189958268 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:22 PM PDT 24 71477567 ps
T909 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.456213257 Apr 30 12:30:23 PM PDT 24 Apr 30 12:30:25 PM PDT 24 75527295 ps
T910 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1927156148 Apr 30 12:30:45 PM PDT 24 Apr 30 12:30:47 PM PDT 24 228816643 ps
T911 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1754521871 Apr 30 12:30:19 PM PDT 24 Apr 30 12:30:20 PM PDT 24 66164045 ps
T912 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3405436550 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 68755933 ps
T913 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509040635 Apr 30 12:30:40 PM PDT 24 Apr 30 12:30:42 PM PDT 24 34845496 ps
T914 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1164640453 Apr 30 12:30:26 PM PDT 24 Apr 30 12:30:28 PM PDT 24 238308723 ps
T915 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1537728477 Apr 30 12:30:09 PM PDT 24 Apr 30 12:30:11 PM PDT 24 82950518 ps
T916 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664955264 Apr 30 12:30:39 PM PDT 24 Apr 30 12:30:41 PM PDT 24 118747169 ps
T917 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700007346 Apr 30 12:30:37 PM PDT 24 Apr 30 12:30:39 PM PDT 24 93484326 ps
T918 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743057897 Apr 30 12:30:23 PM PDT 24 Apr 30 12:30:25 PM PDT 24 51988252 ps
T919 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1103841412 Apr 30 12:30:16 PM PDT 24 Apr 30 12:30:17 PM PDT 24 44726519 ps
T920 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1089229715 Apr 30 12:30:33 PM PDT 24 Apr 30 12:30:35 PM PDT 24 45931435 ps
T921 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1646528922 Apr 30 12:30:22 PM PDT 24 Apr 30 12:30:23 PM PDT 24 89655113 ps
T922 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867719924 Apr 30 12:30:40 PM PDT 24 Apr 30 12:30:42 PM PDT 24 38189425 ps
T923 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4234103198 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:21 PM PDT 24 180889245 ps
T924 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3368545402 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:37 PM PDT 24 74256310 ps
T925 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1601562408 Apr 30 12:30:28 PM PDT 24 Apr 30 12:30:30 PM PDT 24 380755234 ps
T926 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1083198012 Apr 30 12:30:22 PM PDT 24 Apr 30 12:30:24 PM PDT 24 51479089 ps
T927 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3363114636 Apr 30 12:30:46 PM PDT 24 Apr 30 12:30:49 PM PDT 24 64458643 ps
T928 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1959519947 Apr 30 12:30:35 PM PDT 24 Apr 30 12:30:36 PM PDT 24 94021135 ps
T929 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4110962187 Apr 30 12:30:10 PM PDT 24 Apr 30 12:30:12 PM PDT 24 874704334 ps
T930 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3515273030 Apr 30 12:30:28 PM PDT 24 Apr 30 12:30:29 PM PDT 24 107569734 ps
T931 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.732303186 Apr 30 12:30:18 PM PDT 24 Apr 30 12:30:19 PM PDT 24 101068736 ps
T932 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951152783 Apr 30 12:30:16 PM PDT 24 Apr 30 12:30:17 PM PDT 24 34131417 ps
T933 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1786490418 Apr 30 12:30:32 PM PDT 24 Apr 30 12:30:34 PM PDT 24 56451294 ps
T934 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3113474049 Apr 30 12:30:23 PM PDT 24 Apr 30 12:30:25 PM PDT 24 56111526 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1888836380 Apr 30 12:30:45 PM PDT 24 Apr 30 12:30:47 PM PDT 24 102253802 ps
T936 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1296681109 Apr 30 12:30:10 PM PDT 24 Apr 30 12:30:12 PM PDT 24 138008663 ps
T937 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2881455705 Apr 30 12:30:27 PM PDT 24 Apr 30 12:30:28 PM PDT 24 82939368 ps
T938 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.462025084 Apr 30 12:30:30 PM PDT 24 Apr 30 12:30:31 PM PDT 24 95817215 ps
T939 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4103326225 Apr 30 12:30:45 PM PDT 24 Apr 30 12:30:47 PM PDT 24 82105528 ps
T940 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2602377562 Apr 30 12:30:27 PM PDT 24 Apr 30 12:30:28 PM PDT 24 91077174 ps
T941 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1397261030 Apr 30 12:30:20 PM PDT 24 Apr 30 12:30:22 PM PDT 24 422610580 ps
T942 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.211693588 Apr 30 12:30:29 PM PDT 24 Apr 30 12:30:31 PM PDT 24 46454629 ps

Test location /workspace/coverage/default/36.gpio_stress_all.1657896280
Short name T27
Test name
Test status
Simulation time 8384443608 ps
CPU time 184.31 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:26:02 PM PDT 24
Peak memory 197944 kb
Host smart-cf45859c-7ca7-44f3-a19c-a24253e59204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657896280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1657896280
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2218602225
Short name T28
Test name
Test status
Simulation time 73857056 ps
CPU time 1.42 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 196184 kb
Host smart-0e41f307-70f5-4939-8bdc-2dd3878e2021
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218602225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2218602225
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3566936168
Short name T4
Test name
Test status
Simulation time 36395542179 ps
CPU time 431.95 seconds
Started Apr 30 12:23:55 PM PDT 24
Finished Apr 30 12:31:08 PM PDT 24
Peak memory 197864 kb
Host smart-e60e4d1d-337f-46b5-90fe-d61d8bd3d589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3566936168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3566936168
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1060264298
Short name T38
Test name
Test status
Simulation time 68625927 ps
CPU time 0.86 seconds
Started Apr 30 12:18:40 PM PDT 24
Finished Apr 30 12:18:42 PM PDT 24
Peak memory 213728 kb
Host smart-eae3793a-853c-41f8-8fc2-5cb7c5a91408
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060264298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1060264298
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4238911323
Short name T89
Test name
Test status
Simulation time 60796987 ps
CPU time 0.83 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 195704 kb
Host smart-e09dbfcd-0dbe-4339-b848-fa446f418dbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238911323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.4238911323
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1790486912
Short name T46
Test name
Test status
Simulation time 93952077 ps
CPU time 1.13 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 197604 kb
Host smart-786dc32c-4295-4c8a-bab8-fff008735ee0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790486912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1790486912
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2448873003
Short name T79
Test name
Test status
Simulation time 41888206 ps
CPU time 0.78 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 195480 kb
Host smart-4507d822-7e15-4db4-8128-9157332951f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448873003 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2448873003
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2738308813
Short name T25
Test name
Test status
Simulation time 14946218 ps
CPU time 0.61 seconds
Started Apr 30 12:21:27 PM PDT 24
Finished Apr 30 12:21:28 PM PDT 24
Peak memory 194484 kb
Host smart-97add5f8-c7d2-4325-ad9d-3879ef321471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738308813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2738308813
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3002653509
Short name T44
Test name
Test status
Simulation time 634815938 ps
CPU time 1.44 seconds
Started Apr 30 12:30:07 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 197600 kb
Host smart-6927dbd6-482d-41fd-928e-0c971065fa0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002653509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3002653509
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4073322514
Short name T36
Test name
Test status
Simulation time 91926164 ps
CPU time 1.15 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 197504 kb
Host smart-fce12de1-d5de-48bd-93ef-388d5d23824c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073322514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4073322514
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1174323064
Short name T112
Test name
Test status
Simulation time 131124571 ps
CPU time 1.43 seconds
Started Apr 30 12:29:49 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 196372 kb
Host smart-e3f45682-b3f0-49d9-bb9d-dd9ba83a0057
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174323064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1174323064
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.634929335
Short name T805
Test name
Test status
Simulation time 43435326 ps
CPU time 0.6 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 193984 kb
Host smart-b081e02c-adff-4e96-8171-810896e30aab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634929335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.634929335
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.868095100
Short name T751
Test name
Test status
Simulation time 490087085 ps
CPU time 1.5 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 197624 kb
Host smart-0587f71b-b1d9-4481-b220-f3cc3556e368
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868095100 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.868095100
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.955807815
Short name T827
Test name
Test status
Simulation time 18487986 ps
CPU time 0.57 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 192808 kb
Host smart-af5fb9ef-c94e-4a83-9b1a-75b0bbb549e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955807815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.955807815
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.423500809
Short name T837
Test name
Test status
Simulation time 18927943 ps
CPU time 0.62 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 193352 kb
Host smart-d3742ceb-e60f-4657-92b2-b844d706f340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423500809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.423500809
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2805619375
Short name T842
Test name
Test status
Simulation time 44261038 ps
CPU time 0.81 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 195796 kb
Host smart-1dc302c0-8b08-4b5a-80d6-f28db35000f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805619375 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2805619375
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3191675386
Short name T737
Test name
Test status
Simulation time 203241671 ps
CPU time 0.98 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 197460 kb
Host smart-a8c5014f-7a3c-4074-81b1-99d07b7fd039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191675386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3191675386
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3901367606
Short name T787
Test name
Test status
Simulation time 97686710 ps
CPU time 0.9 seconds
Started Apr 30 12:29:49 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 196812 kb
Host smart-c99ecdbd-29f9-4da0-8cce-af8cd36266fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901367606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3901367606
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.153424743
Short name T93
Test name
Test status
Simulation time 15175613 ps
CPU time 0.65 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 194448 kb
Host smart-1032a47a-5892-49d7-badb-ef97d00042d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153424743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.153424743
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3081815641
Short name T779
Test name
Test status
Simulation time 491559667 ps
CPU time 3.19 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 196764 kb
Host smart-7ec1d257-1ecf-4bf1-9779-aea2b2b84562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081815641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3081815641
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.994003768
Short name T75
Test name
Test status
Simulation time 22434781 ps
CPU time 0.61 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 194336 kb
Host smart-e8d5ec04-a0ce-4f31-94b5-a3ee7f2c1b5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994003768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.994003768
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3547872440
Short name T819
Test name
Test status
Simulation time 177375987 ps
CPU time 0.77 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 197568 kb
Host smart-50aff0a3-f9aa-4843-99ad-19e52aa85dbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547872440 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3547872440
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.959073138
Short name T77
Test name
Test status
Simulation time 36576987 ps
CPU time 0.6 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 194068 kb
Host smart-badd86e1-6fb3-4790-8af9-df05b2c0f146
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959073138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.959073138
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1950272779
Short name T729
Test name
Test status
Simulation time 14217274 ps
CPU time 0.58 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 193912 kb
Host smart-aabbe99e-abfb-4d43-a0ae-d21b8cf15f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950272779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1950272779
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.884242348
Short name T838
Test name
Test status
Simulation time 68509771 ps
CPU time 0.84 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 196000 kb
Host smart-f301021e-abe7-45d9-bacc-2386d91434cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884242348 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.884242348
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3895397769
Short name T794
Test name
Test status
Simulation time 178388598 ps
CPU time 1.59 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197724 kb
Host smart-fcfdd8cc-cdf8-48b6-866d-d37c50e41a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895397769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3895397769
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2234983809
Short name T114
Test name
Test status
Simulation time 114525072 ps
CPU time 1.45 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197620 kb
Host smart-aa2d5cc2-a51c-463b-9071-076d1a571d17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234983809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2234983809
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1293893051
Short name T758
Test name
Test status
Simulation time 39663635 ps
CPU time 0.9 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197908 kb
Host smart-cafd34fd-9ac9-4928-8416-0c8e0682b9d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293893051 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1293893051
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2993154469
Short name T753
Test name
Test status
Simulation time 35186954 ps
CPU time 0.58 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 194208 kb
Host smart-f98c7e61-5587-441b-b950-301917544cf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993154469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2993154469
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2790799845
Short name T721
Test name
Test status
Simulation time 53075995 ps
CPU time 0.61 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 193232 kb
Host smart-3c59abea-aa91-4f07-a856-4357e9dacbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790799845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2790799845
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.801683265
Short name T802
Test name
Test status
Simulation time 20468596 ps
CPU time 0.72 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 195136 kb
Host smart-4da8563c-73a4-47c0-954f-f597e2b54319
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801683265 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.801683265
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.500552085
Short name T739
Test name
Test status
Simulation time 35501927 ps
CPU time 1.58 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 197536 kb
Host smart-14fa2c0d-e09e-43ea-a170-d1a5cee4d2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500552085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.500552085
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.13343499
Short name T795
Test name
Test status
Simulation time 216764351 ps
CPU time 0.79 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197448 kb
Host smart-245fb84a-fb8d-434c-8d6f-9a92774a9c1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343499 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.13343499
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1108033110
Short name T87
Test name
Test status
Simulation time 22180466 ps
CPU time 0.6 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 194248 kb
Host smart-fc11ad1d-8841-4bae-a18d-2456c69975ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108033110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1108033110
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1432130302
Short name T755
Test name
Test status
Simulation time 16584351 ps
CPU time 0.63 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 193948 kb
Host smart-5bbe9f05-88fa-4b08-b4fe-0f4dadd7769b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432130302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1432130302
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3725424334
Short name T835
Test name
Test status
Simulation time 19029426 ps
CPU time 0.68 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 195332 kb
Host smart-4f3a6c2a-600b-47aa-a42c-a4d97cae8782
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725424334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3725424334
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1281532416
Short name T730
Test name
Test status
Simulation time 174397582 ps
CPU time 1.23 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197596 kb
Host smart-f513ff49-3b1d-4375-8630-36bfd3cdd00b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281532416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1281532416
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4155211869
Short name T765
Test name
Test status
Simulation time 47393685 ps
CPU time 0.99 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 196768 kb
Host smart-63072007-0d32-4026-9aad-6179a105f094
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155211869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4155211869
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2350387002
Short name T743
Test name
Test status
Simulation time 63445436 ps
CPU time 1.57 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197668 kb
Host smart-ea863549-57cc-4965-acce-721c405d7129
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350387002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2350387002
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4224622201
Short name T803
Test name
Test status
Simulation time 30429526 ps
CPU time 0.56 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 193560 kb
Host smart-aaa6665c-9cbf-4e87-849b-1884a5440112
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224622201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4224622201
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.17110439
Short name T799
Test name
Test status
Simulation time 19698855 ps
CPU time 0.63 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 193320 kb
Host smart-5478a932-c548-478e-9447-db13b265aca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17110439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.17110439
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1153752592
Short name T101
Test name
Test status
Simulation time 18836183 ps
CPU time 0.75 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 195792 kb
Host smart-245e84e3-76c7-4f9b-a361-8a8e22cba3ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153752592 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1153752592
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4212861449
Short name T754
Test name
Test status
Simulation time 2717677032 ps
CPU time 2.71 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 197680 kb
Host smart-6afd2b2a-6535-456e-be0d-d71b0a36256b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212861449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4212861449
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.465362035
Short name T35
Test name
Test status
Simulation time 47445645 ps
CPU time 0.89 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 197412 kb
Host smart-5e603c46-0d7b-4c63-834e-8ae3fca7a1ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465362035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.465362035
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2360484543
Short name T770
Test name
Test status
Simulation time 114051001 ps
CPU time 1.35 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197608 kb
Host smart-32c21cf5-9800-46a2-93b7-0b9ea6e557ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360484543 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2360484543
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4053118992
Short name T88
Test name
Test status
Simulation time 17221893 ps
CPU time 0.66 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 194524 kb
Host smart-30e4c414-dec4-44f1-9554-ea081d1dfd68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053118992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4053118992
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2593484403
Short name T821
Test name
Test status
Simulation time 71015915 ps
CPU time 0.6 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 193924 kb
Host smart-8d2fb9ce-49bc-4ca4-9346-665f224bb720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593484403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2593484403
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2166207293
Short name T804
Test name
Test status
Simulation time 42712856 ps
CPU time 0.89 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 196048 kb
Host smart-c0977322-95f5-43f3-a38c-e73869c551c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166207293 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2166207293
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3272475670
Short name T834
Test name
Test status
Simulation time 154736821 ps
CPU time 2.59 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 197544 kb
Host smart-83f637a8-9b0f-4eec-afc3-e4842d5e9ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272475670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3272475670
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2205153493
Short name T34
Test name
Test status
Simulation time 87363978 ps
CPU time 0.88 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 196460 kb
Host smart-d7d1c3d7-7b10-4bdb-871a-f738e322b46c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205153493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2205153493
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3014808339
Short name T773
Test name
Test status
Simulation time 33565593 ps
CPU time 0.93 seconds
Started Apr 30 12:30:05 PM PDT 24
Finished Apr 30 12:30:07 PM PDT 24
Peak memory 197504 kb
Host smart-7f4a6133-74e1-449c-82dd-3b67b0ea2167
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014808339 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3014808339
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.98555697
Short name T769
Test name
Test status
Simulation time 14572169 ps
CPU time 0.55 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 194276 kb
Host smart-82af2e2f-3d48-48e4-9d96-6506c136142e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98555697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.98555697
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3705620133
Short name T725
Test name
Test status
Simulation time 16955954 ps
CPU time 0.6 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 193320 kb
Host smart-53695619-ef66-4b15-9a5e-6b1a0f62cfd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705620133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3705620133
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.869229529
Short name T824
Test name
Test status
Simulation time 166132841 ps
CPU time 1.23 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 197692 kb
Host smart-591b82d2-b583-40b8-bced-1fba1c6391fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869229529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.869229529
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2465558427
Short name T791
Test name
Test status
Simulation time 33712142 ps
CPU time 0.96 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 197556 kb
Host smart-ee23a133-0051-4af0-841a-51534e270c12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465558427 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2465558427
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1903937640
Short name T111
Test name
Test status
Simulation time 12769101 ps
CPU time 0.6 seconds
Started Apr 30 12:30:15 PM PDT 24
Finished Apr 30 12:30:16 PM PDT 24
Peak memory 194940 kb
Host smart-65e8d789-83b7-4944-8e5c-f53f84eb10c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903937640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1903937640
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1478088567
Short name T812
Test name
Test status
Simulation time 18489181 ps
CPU time 0.65 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 194048 kb
Host smart-7666fe6c-6886-4cdc-8394-6a9be2c01c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478088567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1478088567
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.307027890
Short name T100
Test name
Test status
Simulation time 552373984 ps
CPU time 0.93 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 195928 kb
Host smart-d4751dc5-02d2-4dc8-b870-c03deef3b515
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307027890 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.307027890
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.489399468
Short name T800
Test name
Test status
Simulation time 41947926 ps
CPU time 2.24 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 197648 kb
Host smart-d5db798d-29ac-42dc-bc3e-9933f4b4689d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489399468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.489399468
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.118452024
Short name T113
Test name
Test status
Simulation time 482385483 ps
CPU time 0.89 seconds
Started Apr 30 12:30:03 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 196736 kb
Host smart-57b37dc7-58e3-4578-930d-8d28f5f2dc1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118452024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.118452024
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2219541423
Short name T771
Test name
Test status
Simulation time 27156646 ps
CPU time 1.3 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 197752 kb
Host smart-10b9e005-9252-4a69-9645-b1037aea5b45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219541423 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2219541423
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2640839923
Short name T772
Test name
Test status
Simulation time 11840548 ps
CPU time 0.57 seconds
Started Apr 30 12:30:03 PM PDT 24
Finished Apr 30 12:30:04 PM PDT 24
Peak memory 193624 kb
Host smart-1e264fcb-79ac-4bc8-b68b-773a7db73007
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640839923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2640839923
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3550757029
Short name T767
Test name
Test status
Simulation time 107370501 ps
CPU time 0.63 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 193968 kb
Host smart-0d13a68f-00ec-495b-9960-9f00891bb9fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550757029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3550757029
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1158475025
Short name T80
Test name
Test status
Simulation time 26699392 ps
CPU time 0.71 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 194676 kb
Host smart-f41763cb-f421-46c3-b326-4bc213fbb035
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158475025 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1158475025
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2756736023
Short name T808
Test name
Test status
Simulation time 33510882 ps
CPU time 1.64 seconds
Started Apr 30 12:30:06 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 197624 kb
Host smart-79a8a83a-d6a2-416e-9318-8244b8dad004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756736023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2756736023
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1113671740
Short name T826
Test name
Test status
Simulation time 49484992 ps
CPU time 0.92 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 196584 kb
Host smart-98ac7b65-42f3-4665-975a-cdac0f552c46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113671740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1113671740
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1647736711
Short name T782
Test name
Test status
Simulation time 22196883 ps
CPU time 0.78 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 197508 kb
Host smart-3d1ca0d9-be07-4cf9-9665-41782e8f83f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647736711 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1647736711
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3591606084
Short name T801
Test name
Test status
Simulation time 58956169 ps
CPU time 0.59 seconds
Started Apr 30 12:30:05 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 194432 kb
Host smart-3b80cdcf-d957-406b-8620-d8ebcb459836
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591606084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3591606084
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4175793437
Short name T748
Test name
Test status
Simulation time 31948141 ps
CPU time 0.63 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:17 PM PDT 24
Peak memory 193308 kb
Host smart-7f542cbc-b002-4212-94d7-b1f9f6fb008f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175793437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4175793437
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3635093449
Short name T813
Test name
Test status
Simulation time 81944848 ps
CPU time 0.92 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 197004 kb
Host smart-9d524d0f-04ae-47de-a214-84b49cb8f973
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635093449 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3635093449
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4199576702
Short name T741
Test name
Test status
Simulation time 188680050 ps
CPU time 1.33 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 197992 kb
Host smart-461b047a-f7c3-4625-9d07-e5f481b925dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199576702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4199576702
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3331166612
Short name T728
Test name
Test status
Simulation time 23606293 ps
CPU time 1.12 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 197644 kb
Host smart-f6eda2f1-015d-4043-ba11-9f5fca423397
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331166612 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3331166612
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3649561944
Short name T776
Test name
Test status
Simulation time 11067566 ps
CPU time 0.6 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 194876 kb
Host smart-9f6809da-55f5-4c16-81a7-f25ed405bc91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649561944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3649561944
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2642256414
Short name T793
Test name
Test status
Simulation time 33635605 ps
CPU time 0.57 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 193236 kb
Host smart-8041e873-27ec-4082-b6ea-e2f317ac7683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642256414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2642256414
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3225520458
Short name T784
Test name
Test status
Simulation time 18638835 ps
CPU time 0.92 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 195792 kb
Host smart-d1de190c-e4ec-4121-965e-ee4525ec1074
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225520458 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3225520458
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3180613142
Short name T814
Test name
Test status
Simulation time 51661716 ps
CPU time 2.38 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 197556 kb
Host smart-33a283c2-625b-48d1-919b-7fc7bead3ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180613142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3180613142
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.129453794
Short name T810
Test name
Test status
Simulation time 309676109 ps
CPU time 1.17 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 197568 kb
Host smart-468ca1dd-ff5d-41ae-b322-7a3bc2c02343
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129453794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.129453794
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.717373849
Short name T825
Test name
Test status
Simulation time 195405742 ps
CPU time 0.77 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 197376 kb
Host smart-a8c8f0c9-5970-415d-a42b-3f6839b7284d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717373849 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.717373849
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4229184961
Short name T81
Test name
Test status
Simulation time 47393589 ps
CPU time 0.62 seconds
Started Apr 30 12:30:05 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 194272 kb
Host smart-1408ae30-48ac-4803-bb0e-2899db91e7ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229184961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4229184961
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1924646060
Short name T762
Test name
Test status
Simulation time 34087596 ps
CPU time 0.63 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:04 PM PDT 24
Peak memory 193948 kb
Host smart-d55c752d-ca33-46d3-b0d4-170e87ff31f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924646060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1924646060
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2953502275
Short name T99
Test name
Test status
Simulation time 22431529 ps
CPU time 0.68 seconds
Started Apr 30 12:30:03 PM PDT 24
Finished Apr 30 12:30:04 PM PDT 24
Peak memory 194292 kb
Host smart-cb4d8ecd-09cd-4f9f-9653-aa309c73294c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953502275 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2953502275
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3485379207
Short name T786
Test name
Test status
Simulation time 46671598 ps
CPU time 2.18 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:07 PM PDT 24
Peak memory 197588 kb
Host smart-ef4aa7fe-2ce1-419c-9aac-8b177a49b95a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485379207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3485379207
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.610919599
Short name T45
Test name
Test status
Simulation time 216513899 ps
CPU time 1.38 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 197500 kb
Host smart-435bb54f-fed8-4d5d-9be2-8c68e7725790
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610919599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.610919599
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3566824417
Short name T92
Test name
Test status
Simulation time 16546990 ps
CPU time 0.76 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 195680 kb
Host smart-8e7a8963-160e-44bc-abd0-ad483529df3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566824417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3566824417
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3510415531
Short name T83
Test name
Test status
Simulation time 370490666 ps
CPU time 3.51 seconds
Started Apr 30 12:29:48 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 196720 kb
Host smart-b1a870c5-6965-4850-b1d5-985f40224562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510415531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3510415531
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.109008294
Short name T95
Test name
Test status
Simulation time 39804551 ps
CPU time 0.68 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 195320 kb
Host smart-a51984e3-eea4-4d1b-91e2-c91294fecdfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109008294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.109008294
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1646675176
Short name T764
Test name
Test status
Simulation time 29515424 ps
CPU time 0.67 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 196520 kb
Host smart-66cfb133-4057-4680-961c-3e8ba4530ac9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646675176 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1646675176
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2706277894
Short name T781
Test name
Test status
Simulation time 38898958 ps
CPU time 0.62 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 194820 kb
Host smart-c675edfa-e77c-4ad2-afc6-d7b9e9900f3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706277894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2706277894
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.706092154
Short name T797
Test name
Test status
Simulation time 51979176 ps
CPU time 0.6 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 193976 kb
Host smart-eda964eb-475e-4beb-8afe-15ed124202ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706092154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.706092154
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4092102223
Short name T76
Test name
Test status
Simulation time 24400733 ps
CPU time 0.65 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 194524 kb
Host smart-f3f20268-6c6d-40c3-903b-cbd473a8d420
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092102223 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4092102223
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.526994215
Short name T733
Test name
Test status
Simulation time 135675345 ps
CPU time 1.82 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197600 kb
Host smart-439237c4-84b8-4c9d-9294-24a2dda20232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526994215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.526994215
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.919076940
Short name T33
Test name
Test status
Simulation time 73477672 ps
CPU time 1.19 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 197608 kb
Host smart-26327d64-d304-4bd5-8d33-c8631a38b614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919076940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.919076940
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3866993039
Short name T732
Test name
Test status
Simulation time 10397874 ps
CPU time 0.58 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 193956 kb
Host smart-c3d42044-23d4-495a-8ff1-8a87a69b1ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866993039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3866993039
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.623115646
Short name T726
Test name
Test status
Simulation time 11698066 ps
CPU time 0.56 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 193248 kb
Host smart-8862267b-08b1-417d-98d2-4ec46f327012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623115646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.623115646
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3568231519
Short name T832
Test name
Test status
Simulation time 24322156 ps
CPU time 0.57 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 193260 kb
Host smart-0a9478cd-3bc9-4a4c-b6b4-4ab53e7b3d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568231519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3568231519
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1374378483
Short name T830
Test name
Test status
Simulation time 190665065 ps
CPU time 0.62 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 193976 kb
Host smart-589cc91d-d99d-4446-8f07-ca8db9ff66c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374378483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1374378483
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3117167519
Short name T768
Test name
Test status
Simulation time 65738875 ps
CPU time 0.61 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 193268 kb
Host smart-e16d52cc-296c-4fe6-a835-7d1647633355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117167519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3117167519
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.341493871
Short name T734
Test name
Test status
Simulation time 36548829 ps
CPU time 0.59 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 193868 kb
Host smart-6c5cfb99-e4fd-4318-acaa-40dc3fbb4111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341493871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.341493871
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1142918941
Short name T742
Test name
Test status
Simulation time 15408786 ps
CPU time 0.61 seconds
Started Apr 30 12:30:12 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 193352 kb
Host smart-ea6003e3-b1a4-418d-9da3-0a88825c2e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142918941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1142918941
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4167775133
Short name T750
Test name
Test status
Simulation time 21337484 ps
CPU time 0.59 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 193280 kb
Host smart-747b4a93-8e3c-4e73-88c7-cab7fa44f868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167775133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4167775133
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.527428695
Short name T727
Test name
Test status
Simulation time 37860152 ps
CPU time 0.58 seconds
Started Apr 30 12:30:03 PM PDT 24
Finished Apr 30 12:30:04 PM PDT 24
Peak memory 193264 kb
Host smart-9ef963f5-ae7c-49be-bb55-cdaa05ef7551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527428695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.527428695
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.178143472
Short name T820
Test name
Test status
Simulation time 14161248 ps
CPU time 0.6 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 193228 kb
Host smart-7d65a676-26a4-4e57-84fa-745c2eb7e6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178143472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.178143472
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.553355993
Short name T84
Test name
Test status
Simulation time 16952540 ps
CPU time 0.73 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 195480 kb
Host smart-d8ee7b0d-1037-465d-9b7b-6dd62e28ee4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553355993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.553355993
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.945610507
Short name T792
Test name
Test status
Simulation time 177607208 ps
CPU time 1.45 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 196308 kb
Host smart-a250366d-fc0e-4118-b567-63deee70a70d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945610507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.945610507
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.876918429
Short name T785
Test name
Test status
Simulation time 133343274 ps
CPU time 0.66 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 195012 kb
Host smart-1b009015-62c0-4183-8f5d-dacf0393771c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876918429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.876918429
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.248129248
Short name T744
Test name
Test status
Simulation time 38338091 ps
CPU time 0.66 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 197396 kb
Host smart-374ced4c-b967-48c6-b191-c7d8e855ce91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248129248 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.248129248
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1558009970
Short name T85
Test name
Test status
Simulation time 17108007 ps
CPU time 0.63 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 194348 kb
Host smart-da38a221-f2db-42bd-bf32-f5151a2aabe5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558009970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1558009970
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3102489911
Short name T811
Test name
Test status
Simulation time 32335726 ps
CPU time 0.57 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 193244 kb
Host smart-42ab5bcb-11ca-49b1-851e-5f3d3d060ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102489911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3102489911
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1972805658
Short name T97
Test name
Test status
Simulation time 17392317 ps
CPU time 0.69 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 194792 kb
Host smart-7d620e8f-7dbb-4863-8ee6-43f6b5794ba1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972805658 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1972805658
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.454840478
Short name T759
Test name
Test status
Simulation time 110031447 ps
CPU time 0.96 seconds
Started Apr 30 12:29:48 PM PDT 24
Finished Apr 30 12:29:50 PM PDT 24
Peak memory 197424 kb
Host smart-15d575c7-79f5-4f16-9cf9-a03a21af745b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454840478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.454840478
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2586249988
Short name T783
Test name
Test status
Simulation time 171023203 ps
CPU time 0.87 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 197464 kb
Host smart-4a90103b-faa6-4538-9def-131cb77344f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586249988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2586249988
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3978465656
Short name T839
Test name
Test status
Simulation time 37014749 ps
CPU time 0.59 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 193316 kb
Host smart-fe2de3bf-fa38-4fe5-8b06-62f0674119c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978465656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3978465656
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.640453677
Short name T828
Test name
Test status
Simulation time 39774419 ps
CPU time 0.59 seconds
Started Apr 30 12:30:05 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 193880 kb
Host smart-d405f72d-dc2e-4d9b-8765-9176e4a0cf4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640453677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.640453677
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1516524533
Short name T815
Test name
Test status
Simulation time 20294675 ps
CPU time 0.6 seconds
Started Apr 30 12:30:05 PM PDT 24
Finished Apr 30 12:30:06 PM PDT 24
Peak memory 193336 kb
Host smart-5d45975b-24a3-4f66-bb65-0f0b0113d6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516524533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1516524533
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.250618505
Short name T736
Test name
Test status
Simulation time 38876692 ps
CPU time 0.6 seconds
Started Apr 30 12:30:02 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 193288 kb
Host smart-fc116e3c-22d5-4996-a581-925910c97315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250618505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.250618505
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1461409848
Short name T766
Test name
Test status
Simulation time 59650941 ps
CPU time 0.64 seconds
Started Apr 30 12:30:06 PM PDT 24
Finished Apr 30 12:30:07 PM PDT 24
Peak memory 193276 kb
Host smart-87b34d0f-aa85-43f5-a1f5-5f7bca1c8ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461409848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1461409848
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2334168989
Short name T809
Test name
Test status
Simulation time 13286163 ps
CPU time 0.59 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 193316 kb
Host smart-1aadd0d5-d162-46a6-8bb8-b9948bcd2814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334168989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2334168989
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.756069531
Short name T723
Test name
Test status
Simulation time 16109096 ps
CPU time 0.57 seconds
Started Apr 30 12:30:14 PM PDT 24
Finished Apr 30 12:30:15 PM PDT 24
Peak memory 193928 kb
Host smart-222b9892-0bb5-4798-9dbe-bcfd1d796e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756069531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.756069531
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.335025037
Short name T756
Test name
Test status
Simulation time 17397969 ps
CPU time 0.63 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:03 PM PDT 24
Peak memory 194036 kb
Host smart-6d2eb5a9-a0ae-4f64-b102-10f8ce228ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335025037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.335025037
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3654562641
Short name T757
Test name
Test status
Simulation time 13527318 ps
CPU time 0.57 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 193292 kb
Host smart-1222ade6-0eb7-430d-b0e2-130d44e9427c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654562641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3654562641
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3433711755
Short name T724
Test name
Test status
Simulation time 13966543 ps
CPU time 0.59 seconds
Started Apr 30 12:30:04 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 193968 kb
Host smart-5a039f21-6403-4c59-883b-747abf682094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433711755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3433711755
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3476613431
Short name T841
Test name
Test status
Simulation time 25329325 ps
CPU time 0.78 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 195992 kb
Host smart-92f22843-4859-476a-a957-390b2b4b9fc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476613431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3476613431
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1139993285
Short name T790
Test name
Test status
Simulation time 515116444 ps
CPU time 2.59 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 196584 kb
Host smart-340cf833-b381-4a2d-8039-2c3025a94cc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139993285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1139993285
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.511258114
Short name T94
Test name
Test status
Simulation time 113493069 ps
CPU time 0.64 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 194628 kb
Host smart-94d0c979-7e36-4432-84c2-efcb27d6dfea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511258114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.511258114
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1204194655
Short name T746
Test name
Test status
Simulation time 14940720 ps
CPU time 0.79 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197552 kb
Host smart-7d667b0f-d0a7-4db7-a96c-81e6f526802d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204194655 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1204194655
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4287264935
Short name T86
Test name
Test status
Simulation time 67497882 ps
CPU time 0.59 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 194124 kb
Host smart-de4041fe-b70e-4ccc-899d-6f0b91088e77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287264935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4287264935
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.387570880
Short name T817
Test name
Test status
Simulation time 96103021 ps
CPU time 0.64 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 193988 kb
Host smart-b99fb5b2-1594-4ad4-82cd-20afc184eb4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387570880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.387570880
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.472429179
Short name T798
Test name
Test status
Simulation time 243083266 ps
CPU time 0.7 seconds
Started Apr 30 12:30:00 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 194432 kb
Host smart-e27d8a7e-4c17-4fd1-a0f8-423cbb589cc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472429179 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.472429179
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3116805715
Short name T731
Test name
Test status
Simulation time 248640476 ps
CPU time 2.82 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197632 kb
Host smart-8cae0b7a-0b01-4192-984b-9fa603c14536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116805715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3116805715
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3657465560
Short name T47
Test name
Test status
Simulation time 116805151 ps
CPU time 1.35 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 197444 kb
Host smart-f48449e6-a3ed-449f-b459-3817967e3627
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657465560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3657465560
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1870973665
Short name T818
Test name
Test status
Simulation time 35640651 ps
CPU time 0.59 seconds
Started Apr 30 12:30:13 PM PDT 24
Finished Apr 30 12:30:15 PM PDT 24
Peak memory 193992 kb
Host smart-9c720605-a198-4c3f-aefc-b7985ea4d393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870973665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1870973665
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1644469235
Short name T774
Test name
Test status
Simulation time 12565963 ps
CPU time 0.58 seconds
Started Apr 30 12:30:12 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 193268 kb
Host smart-bfe665fb-6451-4152-aa30-7f7bdd798378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644469235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1644469235
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1935523235
Short name T763
Test name
Test status
Simulation time 38344898 ps
CPU time 0.59 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 193196 kb
Host smart-1978da01-2ad3-4b75-b158-5fa1a0749579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935523235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1935523235
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.208903139
Short name T836
Test name
Test status
Simulation time 24708094 ps
CPU time 0.6 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 193928 kb
Host smart-b708930e-84ee-40dd-9184-b9c147641042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208903139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.208903139
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.761650495
Short name T831
Test name
Test status
Simulation time 54184882 ps
CPU time 0.58 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 193340 kb
Host smart-cf724050-d40a-4777-aae8-cacc5d82c0e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761650495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.761650495
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1983282886
Short name T840
Test name
Test status
Simulation time 14050964 ps
CPU time 0.65 seconds
Started Apr 30 12:30:13 PM PDT 24
Finished Apr 30 12:30:14 PM PDT 24
Peak memory 193956 kb
Host smart-d9990e72-539d-478d-9972-68b1fffa2f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983282886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1983282886
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1381117012
Short name T806
Test name
Test status
Simulation time 16407043 ps
CPU time 0.63 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 193260 kb
Host smart-86fe346b-8ab5-4991-8e99-36e9ecd4078c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381117012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1381117012
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1198528371
Short name T822
Test name
Test status
Simulation time 101937469 ps
CPU time 0.61 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 193908 kb
Host smart-d5e87f0c-6523-4a5c-bf96-143b04ecab03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198528371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1198528371
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.138450487
Short name T752
Test name
Test status
Simulation time 117618992 ps
CPU time 0.58 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 193316 kb
Host smart-12ccae6a-d718-448e-8e9d-4085d35760dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138450487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.138450487
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2489783072
Short name T761
Test name
Test status
Simulation time 43456193 ps
CPU time 0.61 seconds
Started Apr 30 12:30:13 PM PDT 24
Finished Apr 30 12:30:14 PM PDT 24
Peak memory 193956 kb
Host smart-c8060d7b-b021-4cd7-a089-c6e7226ef0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489783072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2489783072
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1715687476
Short name T722
Test name
Test status
Simulation time 64095339 ps
CPU time 0.73 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 196848 kb
Host smart-e35c3e1b-f51b-4fc8-bdba-87fa70520d56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715687476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1715687476
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.107990118
Short name T91
Test name
Test status
Simulation time 15285400 ps
CPU time 0.62 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 195068 kb
Host smart-dcfeb66d-573b-4fd1-9899-0133d7ea5746
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107990118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.107990118
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.580718934
Short name T780
Test name
Test status
Simulation time 49005987 ps
CPU time 0.59 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 193256 kb
Host smart-c3367dc3-4f80-428e-91c2-d0a8dee08b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580718934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.580718934
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.90302436
Short name T816
Test name
Test status
Simulation time 36426484 ps
CPU time 0.87 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 195876 kb
Host smart-a90bad35-82cb-4890-aecb-af8d88e31726
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90302436 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.gpio_same_csr_outstanding.90302436
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1324452589
Short name T788
Test name
Test status
Simulation time 164267325 ps
CPU time 1.71 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 197624 kb
Host smart-66f165a7-e3dc-4854-9dd5-e1855743a498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324452589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1324452589
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4066007121
Short name T43
Test name
Test status
Simulation time 271656118 ps
CPU time 1.12 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 197588 kb
Host smart-bf5d7238-e11a-4dd9-8d8f-5df99aa6a144
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066007121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4066007121
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1100572196
Short name T745
Test name
Test status
Simulation time 28369077 ps
CPU time 1.36 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 197696 kb
Host smart-ccf1444b-749a-4e3f-bd56-1c5f7eaa86eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100572196 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1100572196
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3558733316
Short name T90
Test name
Test status
Simulation time 87158544 ps
CPU time 0.55 seconds
Started Apr 30 12:30:01 PM PDT 24
Finished Apr 30 12:30:02 PM PDT 24
Peak memory 193960 kb
Host smart-e72f4dfd-6ed5-4eec-b818-5e5c53d970da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558733316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3558733316
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1368929914
Short name T829
Test name
Test status
Simulation time 13646362 ps
CPU time 0.64 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 194000 kb
Host smart-edf8ea1f-0e11-43a5-9fe7-3f0d4fef2be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368929914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1368929914
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2670409114
Short name T82
Test name
Test status
Simulation time 81897445 ps
CPU time 0.79 seconds
Started Apr 30 12:29:54 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 196484 kb
Host smart-f91485a5-78eb-4870-ae4b-05f863ade494
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670409114 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2670409114
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.142943505
Short name T735
Test name
Test status
Simulation time 1585981285 ps
CPU time 2.58 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 197560 kb
Host smart-2910b454-fd7b-4991-b379-e5420fec72d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142943505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.142943505
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.650917845
Short name T42
Test name
Test status
Simulation time 314393209 ps
CPU time 1.17 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 197692 kb
Host smart-ac853718-f1fa-49cf-9525-ba3e0513f217
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650917845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.650917845
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.787742997
Short name T740
Test name
Test status
Simulation time 30971160 ps
CPU time 0.72 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 196008 kb
Host smart-c587f52c-def6-4427-a12c-d1bbb0a8d45d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787742997 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.787742997
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2455955548
Short name T78
Test name
Test status
Simulation time 26059764 ps
CPU time 0.58 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 194908 kb
Host smart-df51a188-8bc2-4099-8a43-c625795d380d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455955548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2455955548
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1309703041
Short name T807
Test name
Test status
Simulation time 20425560 ps
CPU time 0.6 seconds
Started Apr 30 12:29:57 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 193620 kb
Host smart-aac4b388-a012-47f2-b19e-fdf280e6b7a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309703041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1309703041
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1418664244
Short name T96
Test name
Test status
Simulation time 19835886 ps
CPU time 0.66 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 194964 kb
Host smart-2f84e744-6251-4e9c-a888-26fa7de76da3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418664244 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1418664244
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1969487218
Short name T760
Test name
Test status
Simulation time 136604012 ps
CPU time 2.63 seconds
Started Apr 30 12:29:53 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 197700 kb
Host smart-436639a8-6204-458e-bb95-48a607e38064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969487218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1969487218
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.961242919
Short name T49
Test name
Test status
Simulation time 211293271 ps
CPU time 1.37 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197652 kb
Host smart-319865e1-b26f-4759-9fad-50dc606ee3da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961242919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.961242919
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2106959966
Short name T738
Test name
Test status
Simulation time 21472412 ps
CPU time 0.85 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197624 kb
Host smart-b7d231a0-73c5-47a5-9398-4d5d976c05b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106959966 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2106959966
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1951897175
Short name T833
Test name
Test status
Simulation time 77124469 ps
CPU time 0.58 seconds
Started Apr 30 12:29:52 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 192872 kb
Host smart-9a6760ac-ee19-45f2-b3d7-cff99bf70cb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951897175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1951897175
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3059942054
Short name T789
Test name
Test status
Simulation time 38595503 ps
CPU time 0.57 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 193244 kb
Host smart-6da44839-67b4-4701-8c7d-638193a993eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059942054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3059942054
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1039034218
Short name T823
Test name
Test status
Simulation time 35564033 ps
CPU time 0.81 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 195736 kb
Host smart-b6d26a31-01b9-4d0c-8b7d-76726e8e15b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039034218 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1039034218
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2504847818
Short name T777
Test name
Test status
Simulation time 41817351 ps
CPU time 1.23 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 197340 kb
Host smart-c6029352-1356-40fe-97fd-8b15c2dc0e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504847818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2504847818
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.167900581
Short name T775
Test name
Test status
Simulation time 109320745 ps
CPU time 1.42 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 197596 kb
Host smart-60fab551-cb0a-4759-a760-f5ffcdb1ed08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167900581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.167900581
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1248208871
Short name T778
Test name
Test status
Simulation time 27701010 ps
CPU time 1.32 seconds
Started Apr 30 12:30:08 PM PDT 24
Finished Apr 30 12:30:10 PM PDT 24
Peak memory 197576 kb
Host smart-4174a71e-edad-4e07-b9d0-9a84d8cfa7d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248208871 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1248208871
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4288869371
Short name T796
Test name
Test status
Simulation time 41082682 ps
CPU time 0.69 seconds
Started Apr 30 12:29:59 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 194300 kb
Host smart-30c18ce1-15f1-4a2c-b681-2e0257916eb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288869371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4288869371
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3032190545
Short name T749
Test name
Test status
Simulation time 84937206 ps
CPU time 0.63 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 193336 kb
Host smart-63e8706f-e92b-4252-b6be-195f0ac7558c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032190545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3032190545
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1697895868
Short name T98
Test name
Test status
Simulation time 94498335 ps
CPU time 0.73 seconds
Started Apr 30 12:29:58 PM PDT 24
Finished Apr 30 12:30:00 PM PDT 24
Peak memory 195616 kb
Host smart-7c68ceab-ba1e-4d92-8e69-3ee4e69a22ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697895868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1697895868
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2207649605
Short name T747
Test name
Test status
Simulation time 67983408 ps
CPU time 1.18 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 197656 kb
Host smart-8b880918-26be-4971-8447-cd3392997cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207649605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2207649605
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3095527798
Short name T48
Test name
Test status
Simulation time 94925153 ps
CPU time 1.14 seconds
Started Apr 30 12:29:56 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 197608 kb
Host smart-22c98f35-8068-4a50-bf48-d813ca446e9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095527798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3095527798
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2923213648
Short name T188
Test name
Test status
Simulation time 41460552 ps
CPU time 0.61 seconds
Started Apr 30 12:17:05 PM PDT 24
Finished Apr 30 12:17:06 PM PDT 24
Peak memory 194384 kb
Host smart-d387ec81-c735-4c47-a04f-1600872139fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923213648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2923213648
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1904518045
Short name T682
Test name
Test status
Simulation time 76917954 ps
CPU time 0.66 seconds
Started Apr 30 12:18:40 PM PDT 24
Finished Apr 30 12:18:41 PM PDT 24
Peak memory 194144 kb
Host smart-ae69637c-0104-4835-ad02-5da9293d44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904518045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1904518045
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2122679997
Short name T351
Test name
Test status
Simulation time 1753301844 ps
CPU time 13.2 seconds
Started Apr 30 12:17:12 PM PDT 24
Finished Apr 30 12:17:26 PM PDT 24
Peak memory 197704 kb
Host smart-20d1fcf7-250a-4f62-a7e4-bcee6f5c2579
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122679997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2122679997
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.4116120608
Short name T512
Test name
Test status
Simulation time 98458815 ps
CPU time 0.71 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:18 PM PDT 24
Peak memory 194080 kb
Host smart-0baa629b-4d88-4565-815e-c79619fc4c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116120608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.4116120608
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3758350958
Short name T109
Test name
Test status
Simulation time 72625221 ps
CPU time 0.74 seconds
Started Apr 30 12:20:56 PM PDT 24
Finished Apr 30 12:20:57 PM PDT 24
Peak memory 194060 kb
Host smart-abb7f394-e47a-48da-b7c7-b0dfffec9c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758350958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3758350958
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1453362900
Short name T239
Test name
Test status
Simulation time 158599169 ps
CPU time 2.95 seconds
Started Apr 30 12:17:11 PM PDT 24
Finished Apr 30 12:17:15 PM PDT 24
Peak memory 197752 kb
Host smart-bd7dbd03-3106-4cd9-a97b-d985edffb2b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453362900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1453362900
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1467123568
Short name T198
Test name
Test status
Simulation time 161918371 ps
CPU time 3.47 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:17:20 PM PDT 24
Peak memory 196740 kb
Host smart-cf5299a6-9323-48dd-b7bc-197070698865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467123568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1467123568
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1597344996
Short name T500
Test name
Test status
Simulation time 69192031 ps
CPU time 0.81 seconds
Started Apr 30 12:18:20 PM PDT 24
Finished Apr 30 12:18:21 PM PDT 24
Peak memory 196284 kb
Host smart-83f0f777-29f4-4597-8af1-cb7c5c79b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597344996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1597344996
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1325805184
Short name T664
Test name
Test status
Simulation time 69278192 ps
CPU time 0.82 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 195492 kb
Host smart-7cf485ff-1b2d-48fc-a00f-32a9c0567afc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325805184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1325805184
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1349687021
Short name T471
Test name
Test status
Simulation time 137314934 ps
CPU time 1.44 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:17:18 PM PDT 24
Peak memory 197648 kb
Host smart-6c70ec43-5464-45a2-8993-607366a324e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349687021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1349687021
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1498215872
Short name T290
Test name
Test status
Simulation time 156156525 ps
CPU time 1 seconds
Started Apr 30 12:17:05 PM PDT 24
Finished Apr 30 12:17:06 PM PDT 24
Peak memory 195736 kb
Host smart-b1727dff-4701-4fd7-8396-5d243966267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498215872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1498215872
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.348816744
Short name T717
Test name
Test status
Simulation time 31113984 ps
CPU time 0.74 seconds
Started Apr 30 12:17:18 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 195156 kb
Host smart-b870ca8e-d2b8-4383-aec3-f0517704b56b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348816744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.348816744
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.4230604488
Short name T545
Test name
Test status
Simulation time 66670193292 ps
CPU time 204.91 seconds
Started Apr 30 12:18:17 PM PDT 24
Finished Apr 30 12:21:43 PM PDT 24
Peak memory 197508 kb
Host smart-635f4352-aa60-4103-b77e-afd50d60a8a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230604488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.4230604488
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1718550442
Short name T323
Test name
Test status
Simulation time 41089765 ps
CPU time 0.53 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:18 PM PDT 24
Peak memory 193584 kb
Host smart-6b1a4ffd-3fda-4cbd-9b34-9f3b664ad54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718550442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1718550442
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2159858943
Short name T691
Test name
Test status
Simulation time 64887646 ps
CPU time 0.68 seconds
Started Apr 30 12:17:05 PM PDT 24
Finished Apr 30 12:17:06 PM PDT 24
Peak memory 193836 kb
Host smart-899aa335-5c5b-4bea-b5ea-1d1905c8cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159858943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2159858943
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3076165511
Short name T546
Test name
Test status
Simulation time 546953595 ps
CPU time 6.53 seconds
Started Apr 30 12:17:13 PM PDT 24
Finished Apr 30 12:17:20 PM PDT 24
Peak memory 196724 kb
Host smart-17b2e139-61df-4cf8-8929-6e355de4a9b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076165511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3076165511
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.19738959
Short name T687
Test name
Test status
Simulation time 25674950 ps
CPU time 0.7 seconds
Started Apr 30 12:17:23 PM PDT 24
Finished Apr 30 12:17:24 PM PDT 24
Peak memory 194288 kb
Host smart-ef100b88-3fc6-4451-8196-01215d77ad8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.19738959
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3517675264
Short name T325
Test name
Test status
Simulation time 20032149 ps
CPU time 0.64 seconds
Started Apr 30 12:17:13 PM PDT 24
Finished Apr 30 12:17:14 PM PDT 24
Peak memory 194312 kb
Host smart-173c6e52-735a-483f-9962-ad326a10ddb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517675264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3517675264
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1163573226
Short name T314
Test name
Test status
Simulation time 52316389 ps
CPU time 2.2 seconds
Started Apr 30 12:17:13 PM PDT 24
Finished Apr 30 12:17:16 PM PDT 24
Peak memory 198036 kb
Host smart-13fc671a-7c95-4c6c-8790-1d9ffc2fb2b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163573226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1163573226
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.847539888
Short name T260
Test name
Test status
Simulation time 52035572 ps
CPU time 1.66 seconds
Started Apr 30 12:17:23 PM PDT 24
Finished Apr 30 12:17:25 PM PDT 24
Peak memory 196576 kb
Host smart-8495002a-a7c0-478c-a367-2944e65358a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847539888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.847539888
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2642136768
Short name T334
Test name
Test status
Simulation time 42969439 ps
CPU time 1.02 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:17:18 PM PDT 24
Peak memory 195504 kb
Host smart-e1e381ba-49d6-4048-921d-cb318fe2a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642136768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2642136768
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.578466669
Short name T394
Test name
Test status
Simulation time 169761772 ps
CPU time 1.02 seconds
Started Apr 30 12:19:26 PM PDT 24
Finished Apr 30 12:19:27 PM PDT 24
Peak memory 195960 kb
Host smart-76296027-70bf-406a-8f7b-da7f22f90654
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578466669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.578466669
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1793602393
Short name T376
Test name
Test status
Simulation time 1016238576 ps
CPU time 5.26 seconds
Started Apr 30 12:18:40 PM PDT 24
Finished Apr 30 12:18:45 PM PDT 24
Peak memory 197900 kb
Host smart-8550c40f-5f5e-4640-a38b-89ea6cde07bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793602393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1793602393
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2692486251
Short name T51
Test name
Test status
Simulation time 179518598 ps
CPU time 0.88 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 212264 kb
Host smart-19ed2a32-47f2-4c63-bfea-9fdb5d300727
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692486251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2692486251
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2263585829
Short name T253
Test name
Test status
Simulation time 382359422 ps
CPU time 1.26 seconds
Started Apr 30 12:17:11 PM PDT 24
Finished Apr 30 12:17:13 PM PDT 24
Peak memory 196472 kb
Host smart-57198951-805b-40ec-b66b-3f070c47d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263585829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2263585829
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.485408164
Short name T672
Test name
Test status
Simulation time 144523941 ps
CPU time 1.23 seconds
Started Apr 30 12:19:22 PM PDT 24
Finished Apr 30 12:19:24 PM PDT 24
Peak memory 196504 kb
Host smart-2365455f-23b1-41e0-b2bb-298e7746de00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485408164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.485408164
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1961423027
Short name T595
Test name
Test status
Simulation time 26905923428 ps
CPU time 184.2 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:20:21 PM PDT 24
Peak memory 197204 kb
Host smart-8bb9e7ea-f831-4442-99fc-ba528c1146ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961423027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1961423027
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3689520543
Short name T450
Test name
Test status
Simulation time 19734871 ps
CPU time 0.55 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 193004 kb
Host smart-6af4d007-3c30-4613-9a1a-ca20e4635145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689520543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3689520543
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1245542014
Short name T688
Test name
Test status
Simulation time 99416879 ps
CPU time 0.88 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 194152 kb
Host smart-467775a4-2968-46aa-9d86-70f00abef4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245542014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1245542014
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1285086636
Short name T646
Test name
Test status
Simulation time 862862550 ps
CPU time 23.55 seconds
Started Apr 30 12:18:05 PM PDT 24
Finished Apr 30 12:18:29 PM PDT 24
Peak memory 195460 kb
Host smart-79cfd48d-1d76-44fd-bc0f-e3e7fc66ef98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285086636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1285086636
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.453423429
Short name T123
Test name
Test status
Simulation time 38480437 ps
CPU time 0.75 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:17:58 PM PDT 24
Peak memory 195872 kb
Host smart-45b85138-3da5-4ff3-8d32-10e2e20e323b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453423429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.453423429
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.58011826
Short name T104
Test name
Test status
Simulation time 108758502 ps
CPU time 0.88 seconds
Started Apr 30 12:18:01 PM PDT 24
Finished Apr 30 12:18:02 PM PDT 24
Peak memory 196276 kb
Host smart-22231712-c2aa-4f63-b189-005c3f4bbeeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58011826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.58011826
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2796370036
Short name T530
Test name
Test status
Simulation time 37039419 ps
CPU time 1.51 seconds
Started Apr 30 12:18:00 PM PDT 24
Finished Apr 30 12:18:02 PM PDT 24
Peak memory 196556 kb
Host smart-73c24a9f-6a55-4af0-95e7-ba03b7fd16e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796370036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2796370036
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3850222379
Short name T472
Test name
Test status
Simulation time 569665355 ps
CPU time 2.97 seconds
Started Apr 30 12:17:56 PM PDT 24
Finished Apr 30 12:18:00 PM PDT 24
Peak memory 196448 kb
Host smart-d1610ee1-0c8f-456b-998d-3d12047b3ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850222379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3850222379
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4257596113
Short name T673
Test name
Test status
Simulation time 57700016 ps
CPU time 0.78 seconds
Started Apr 30 12:17:56 PM PDT 24
Finished Apr 30 12:17:57 PM PDT 24
Peak memory 195940 kb
Host smart-6cfd2ec8-ddd0-4e89-b735-94471b5ee476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257596113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4257596113
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.92117131
Short name T258
Test name
Test status
Simulation time 302073492 ps
CPU time 1.04 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:17:59 PM PDT 24
Peak memory 196264 kb
Host smart-8be4369a-410d-42b6-ab43-cbcfa3e2742d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92117131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup_
pulldown.92117131
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1468354152
Short name T455
Test name
Test status
Simulation time 752482893 ps
CPU time 5.9 seconds
Started Apr 30 12:17:59 PM PDT 24
Finished Apr 30 12:18:06 PM PDT 24
Peak memory 197880 kb
Host smart-a6c8c082-5d70-4886-8ef8-aaba8248a0d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468354152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1468354152
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2023212340
Short name T13
Test name
Test status
Simulation time 334702929 ps
CPU time 1.29 seconds
Started Apr 30 12:17:53 PM PDT 24
Finished Apr 30 12:17:55 PM PDT 24
Peak memory 195628 kb
Host smart-1300567e-2ac4-41ab-b278-fa1db0d697c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023212340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2023212340
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1903205743
Short name T415
Test name
Test status
Simulation time 140322501 ps
CPU time 1.48 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:17:59 PM PDT 24
Peak memory 197032 kb
Host smart-92044a72-4bc5-41ef-bd67-e40abb09e176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903205743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1903205743
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1532514898
Short name T284
Test name
Test status
Simulation time 91467859115 ps
CPU time 195.77 seconds
Started Apr 30 12:21:07 PM PDT 24
Finished Apr 30 12:24:23 PM PDT 24
Peak memory 198224 kb
Host smart-5c2c96d8-b459-4414-a0eb-4e83c976966e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532514898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1532514898
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1256068858
Short name T580
Test name
Test status
Simulation time 159026499847 ps
CPU time 1739.44 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:51:33 PM PDT 24
Peak memory 197412 kb
Host smart-7cdb4367-14c9-4c8b-b06f-f6f3d8d8a85a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1256068858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1256068858
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.145390964
Short name T347
Test name
Test status
Simulation time 26762547 ps
CPU time 0.56 seconds
Started Apr 30 12:18:14 PM PDT 24
Finished Apr 30 12:18:15 PM PDT 24
Peak memory 193812 kb
Host smart-8667b9e4-6628-4df0-8dac-02dac7ef4b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145390964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.145390964
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3786711611
Short name T463
Test name
Test status
Simulation time 48721203 ps
CPU time 0.68 seconds
Started Apr 30 12:18:06 PM PDT 24
Finished Apr 30 12:18:07 PM PDT 24
Peak memory 193968 kb
Host smart-4ba38462-04e1-488c-98c5-84ab17620d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786711611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3786711611
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2421310886
Short name T292
Test name
Test status
Simulation time 125318127 ps
CPU time 4.41 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:53 PM PDT 24
Peak memory 194152 kb
Host smart-a6e6ad00-bfec-4572-bba4-8df1182e3789
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421310886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2421310886
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3789481636
Short name T522
Test name
Test status
Simulation time 32717251 ps
CPU time 0.67 seconds
Started Apr 30 12:18:04 PM PDT 24
Finished Apr 30 12:18:05 PM PDT 24
Peak memory 194532 kb
Host smart-69cbcfe2-573b-4496-b349-2ea53686c50f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789481636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3789481636
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3963812676
Short name T182
Test name
Test status
Simulation time 173692043 ps
CPU time 1.17 seconds
Started Apr 30 12:18:02 PM PDT 24
Finished Apr 30 12:18:03 PM PDT 24
Peak memory 195996 kb
Host smart-942bb4e7-e097-4e0c-b693-7ee9bd2ea077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963812676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3963812676
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3227307141
Short name T356
Test name
Test status
Simulation time 121273182 ps
CPU time 2.72 seconds
Started Apr 30 12:18:05 PM PDT 24
Finished Apr 30 12:18:08 PM PDT 24
Peak memory 197996 kb
Host smart-4bea2a5d-f2ce-4766-992e-804dae47f171
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227307141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3227307141
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1054718592
Short name T511
Test name
Test status
Simulation time 149801544 ps
CPU time 2.07 seconds
Started Apr 30 12:18:05 PM PDT 24
Finished Apr 30 12:18:07 PM PDT 24
Peak memory 196096 kb
Host smart-f07fe5de-1bf4-4d83-b655-4b7d237fce33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054718592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1054718592
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.179216417
Short name T602
Test name
Test status
Simulation time 67028279 ps
CPU time 0.61 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:49 PM PDT 24
Peak memory 192996 kb
Host smart-8b849fa5-fb12-4956-9752-d6e998ff77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179216417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.179216417
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1861858600
Short name T662
Test name
Test status
Simulation time 28989150 ps
CPU time 0.79 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:49 PM PDT 24
Peak memory 192552 kb
Host smart-45cb89fe-b42e-4003-9d5f-b7acb6041c60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861858600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1861858600
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2633882169
Short name T248
Test name
Test status
Simulation time 104734171 ps
CPU time 4.66 seconds
Started Apr 30 12:18:05 PM PDT 24
Finished Apr 30 12:18:10 PM PDT 24
Peak memory 197912 kb
Host smart-944196aa-df58-4363-82af-3158e65391ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633882169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2633882169
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1985979142
Short name T430
Test name
Test status
Simulation time 378015346 ps
CPU time 1.47 seconds
Started Apr 30 12:21:43 PM PDT 24
Finished Apr 30 12:21:45 PM PDT 24
Peak memory 195420 kb
Host smart-a7ea6f2c-1f26-4d45-87aa-1633b1cfe894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985979142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1985979142
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3239802313
Short name T419
Test name
Test status
Simulation time 167309748 ps
CPU time 1.19 seconds
Started Apr 30 12:18:25 PM PDT 24
Finished Apr 30 12:18:26 PM PDT 24
Peak memory 195800 kb
Host smart-7d670bdd-530e-43ad-90c7-befb35464df6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239802313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3239802313
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2169906497
Short name T7
Test name
Test status
Simulation time 7118009228 ps
CPU time 21.55 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:20:11 PM PDT 24
Peak memory 197768 kb
Host smart-cd7fd4c5-3307-480c-bb30-254f34a6efb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169906497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2169906497
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.4264905259
Short name T660
Test name
Test status
Simulation time 50703192 ps
CPU time 0.57 seconds
Started Apr 30 12:18:20 PM PDT 24
Finished Apr 30 12:18:21 PM PDT 24
Peak memory 193872 kb
Host smart-4bfd68ed-ce32-44f5-bb6b-4184b53f54fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264905259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.4264905259
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2930550159
Short name T213
Test name
Test status
Simulation time 51406473 ps
CPU time 0.82 seconds
Started Apr 30 12:20:57 PM PDT 24
Finished Apr 30 12:20:59 PM PDT 24
Peak memory 195164 kb
Host smart-1ad64829-6b3a-4120-b17d-614f12c024ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930550159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2930550159
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2426610338
Short name T137
Test name
Test status
Simulation time 273010264 ps
CPU time 6.73 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:55 PM PDT 24
Peak memory 192780 kb
Host smart-1bc25307-a42d-4e3a-a9ff-6115099fab41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426610338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2426610338
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2708644734
Short name T462
Test name
Test status
Simulation time 374815395 ps
CPU time 1.02 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:50 PM PDT 24
Peak memory 195092 kb
Host smart-85dd57ee-c19a-42ce-9b75-bb05567fe6eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708644734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2708644734
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4002304762
Short name T491
Test name
Test status
Simulation time 219459832 ps
CPU time 1.04 seconds
Started Apr 30 12:20:03 PM PDT 24
Finished Apr 30 12:20:04 PM PDT 24
Peak memory 196020 kb
Host smart-e595b74c-4e5c-43dd-9979-ccc182c41ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002304762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4002304762
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1135752249
Short name T396
Test name
Test status
Simulation time 424087347 ps
CPU time 3.36 seconds
Started Apr 30 12:20:41 PM PDT 24
Finished Apr 30 12:20:44 PM PDT 24
Peak memory 196260 kb
Host smart-a16aae97-8ad6-4585-b506-5238e1db05d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135752249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1135752249
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2286353232
Short name T287
Test name
Test status
Simulation time 205815917 ps
CPU time 2.28 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195660 kb
Host smart-ed44d4d4-159b-492d-9460-05f1ac532799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286353232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2286353232
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3569732662
Short name T567
Test name
Test status
Simulation time 20091494 ps
CPU time 0.78 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 197004 kb
Host smart-fc9d12b4-4052-4d0f-9db6-c31171d22cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569732662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3569732662
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2314886482
Short name T138
Test name
Test status
Simulation time 112290197 ps
CPU time 0.93 seconds
Started Apr 30 12:20:57 PM PDT 24
Finished Apr 30 12:20:58 PM PDT 24
Peak memory 197468 kb
Host smart-0463bd4b-b791-42bf-be4f-8e794d3ce96d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314886482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2314886482
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3949237776
Short name T561
Test name
Test status
Simulation time 1185409348 ps
CPU time 4.93 seconds
Started Apr 30 12:18:29 PM PDT 24
Finished Apr 30 12:18:35 PM PDT 24
Peak memory 198264 kb
Host smart-4994cf07-f5c6-4620-80e8-1fe6787c1cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949237776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3949237776
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3241997853
Short name T404
Test name
Test status
Simulation time 277298319 ps
CPU time 1.17 seconds
Started Apr 30 12:18:09 PM PDT 24
Finished Apr 30 12:18:11 PM PDT 24
Peak memory 195552 kb
Host smart-2af9a7ff-10b4-45bc-a7f9-f6cd60a824ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241997853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3241997853
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.959502404
Short name T14
Test name
Test status
Simulation time 300704731 ps
CPU time 1.59 seconds
Started Apr 30 12:20:42 PM PDT 24
Finished Apr 30 12:20:44 PM PDT 24
Peak memory 196888 kb
Host smart-90b7a0d6-1e68-43ad-a999-2d64bb1aaeeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959502404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.959502404
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3301973283
Short name T103
Test name
Test status
Simulation time 7254742864 ps
CPU time 180.19 seconds
Started Apr 30 12:21:57 PM PDT 24
Finished Apr 30 12:24:58 PM PDT 24
Peak memory 197708 kb
Host smart-5bdf8b51-a85e-41f7-b77a-7c1f98e71e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301973283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3301973283
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3401425153
Short name T181
Test name
Test status
Simulation time 81692006 ps
CPU time 0.65 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:20:45 PM PDT 24
Peak memory 193984 kb
Host smart-7665e7c4-9122-4329-a8c7-6861d1e29065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401425153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3401425153
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2705409335
Short name T626
Test name
Test status
Simulation time 317331554 ps
CPU time 0.88 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 196388 kb
Host smart-27be77c7-1892-4d8d-a53e-0e21552aff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705409335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2705409335
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3287814054
Short name T185
Test name
Test status
Simulation time 1316853073 ps
CPU time 20.49 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:20:09 PM PDT 24
Peak memory 194168 kb
Host smart-124e596b-71f3-4389-bf29-38aa7eeeff96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287814054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3287814054
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1724771754
Short name T3
Test name
Test status
Simulation time 28209451 ps
CPU time 0.67 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:02 PM PDT 24
Peak memory 194352 kb
Host smart-c432ab89-3835-4601-b72d-4a49ae4fcb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724771754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1724771754
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3209535164
Short name T295
Test name
Test status
Simulation time 97515135 ps
CPU time 0.81 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:49 PM PDT 24
Peak memory 193320 kb
Host smart-a459a029-9943-4370-9146-a5a6a77a52bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209535164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3209535164
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.405111587
Short name T436
Test name
Test status
Simulation time 72196216 ps
CPU time 2.86 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:02 PM PDT 24
Peak memory 197976 kb
Host smart-d194e08a-76ba-4de1-a188-22feef8f9a47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405111587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.405111587
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4060555789
Short name T118
Test name
Test status
Simulation time 63535088 ps
CPU time 1.18 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:50 PM PDT 24
Peak memory 194708 kb
Host smart-03951425-8194-4d33-82a0-3e1719b22a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060555789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4060555789
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1181856195
Short name T355
Test name
Test status
Simulation time 62879104 ps
CPU time 0.95 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:50 PM PDT 24
Peak memory 194484 kb
Host smart-b618d3d3-161b-4234-865c-288f3ab460b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181856195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1181856195
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2566889736
Short name T320
Test name
Test status
Simulation time 53100085 ps
CPU time 1.18 seconds
Started Apr 30 12:18:28 PM PDT 24
Finished Apr 30 12:18:30 PM PDT 24
Peak memory 196732 kb
Host smart-040ed10d-7d41-4b3f-9580-08788d072a73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566889736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2566889736
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.99851280
Short name T398
Test name
Test status
Simulation time 46002185 ps
CPU time 2.09 seconds
Started Apr 30 12:18:30 PM PDT 24
Finished Apr 30 12:18:32 PM PDT 24
Peak memory 197872 kb
Host smart-e0d002b0-2364-401c-9e4e-da12ef24ed07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99851280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand
om_long_reg_writes_reg_reads.99851280
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.724704362
Short name T282
Test name
Test status
Simulation time 39528721 ps
CPU time 1.09 seconds
Started Apr 30 12:21:52 PM PDT 24
Finished Apr 30 12:21:54 PM PDT 24
Peak memory 194880 kb
Host smart-c6cc6eb9-51b5-4c50-ad37-6ebb9844e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724704362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.724704362
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2727058959
Short name T714
Test name
Test status
Simulation time 83299659 ps
CPU time 0.86 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:19:50 PM PDT 24
Peak memory 192256 kb
Host smart-eed24458-f8ee-4cc1-9546-85542dbc3b7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727058959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2727058959
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1833210817
Short name T558
Test name
Test status
Simulation time 76765777008 ps
CPU time 203.37 seconds
Started Apr 30 12:18:40 PM PDT 24
Finished Apr 30 12:22:03 PM PDT 24
Peak memory 198056 kb
Host smart-4a9b3ad3-9f9c-4775-99db-00500aa13655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833210817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1833210817
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2877858002
Short name T533
Test name
Test status
Simulation time 120003400003 ps
CPU time 1973.88 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:54:54 PM PDT 24
Peak memory 197248 kb
Host smart-c51a0ef7-93d7-4917-89db-e4a725deb56e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2877858002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2877858002
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3792444302
Short name T445
Test name
Test status
Simulation time 353542077 ps
CPU time 0.84 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 195708 kb
Host smart-00cd7400-f4f9-40eb-b656-cd28f3bfb90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792444302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3792444302
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.982853112
Short name T127
Test name
Test status
Simulation time 598266340 ps
CPU time 17.5 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:21:01 PM PDT 24
Peak memory 196824 kb
Host smart-384dc422-6861-4d61-b01d-ca7d5442f614
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982853112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.982853112
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.297320255
Short name T395
Test name
Test status
Simulation time 100226158 ps
CPU time 0.83 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 193716 kb
Host smart-8c5ff48f-32d8-403c-ba57-5761b5972a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297320255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.297320255
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.83960141
Short name T136
Test name
Test status
Simulation time 85476185 ps
CPU time 1.17 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:22:35 PM PDT 24
Peak memory 195976 kb
Host smart-d22b5b12-5f13-4b70-b40f-1c4909815efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83960141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.83960141
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2925057495
Short name T718
Test name
Test status
Simulation time 157147984 ps
CPU time 1.83 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 197972 kb
Host smart-a2801bcc-530e-40f1-baae-9018ab2d346c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925057495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2925057495
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2649066431
Short name T151
Test name
Test status
Simulation time 74574594 ps
CPU time 2.22 seconds
Started Apr 30 12:19:08 PM PDT 24
Finished Apr 30 12:19:10 PM PDT 24
Peak memory 197360 kb
Host smart-055059fa-4327-477b-a0ae-af987dc1ae03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649066431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2649066431
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2974860357
Short name T227
Test name
Test status
Simulation time 94784474 ps
CPU time 1.21 seconds
Started Apr 30 12:21:12 PM PDT 24
Finished Apr 30 12:21:14 PM PDT 24
Peak memory 196412 kb
Host smart-1724259c-4a58-4554-8fd3-859cba02db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974860357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2974860357
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2900157923
Short name T669
Test name
Test status
Simulation time 537469188 ps
CPU time 1.03 seconds
Started Apr 30 12:19:06 PM PDT 24
Finished Apr 30 12:19:08 PM PDT 24
Peak memory 196192 kb
Host smart-6cabd31b-fea5-4448-9322-75ca4b7330ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900157923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2900157923
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2950349088
Short name T149
Test name
Test status
Simulation time 2677180058 ps
CPU time 3.78 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 197852 kb
Host smart-bf25f020-13dc-4c29-a8c3-c6a20561e721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950349088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2950349088
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1201411267
Short name T683
Test name
Test status
Simulation time 47059015 ps
CPU time 1.13 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 195348 kb
Host smart-54a0f3e2-0061-4747-adcb-05f2f3e517bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201411267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1201411267
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3480691054
Short name T424
Test name
Test status
Simulation time 51160130 ps
CPU time 1.09 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:02 PM PDT 24
Peak memory 195188 kb
Host smart-192a20a4-6c9e-4052-bd20-69b0300c56ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480691054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3480691054
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2740822131
Short name T637
Test name
Test status
Simulation time 24550818295 ps
CPU time 132.52 seconds
Started Apr 30 12:20:32 PM PDT 24
Finished Apr 30 12:22:45 PM PDT 24
Peak memory 198212 kb
Host smart-d312d460-322b-482d-b34c-00fa7c1914ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740822131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2740822131
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3121587696
Short name T590
Test name
Test status
Simulation time 14930028 ps
CPU time 0.56 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:56 PM PDT 24
Peak memory 193956 kb
Host smart-2d8bf1cf-df30-4e06-a95a-36746fbf4ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121587696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3121587696
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2388962735
Short name T300
Test name
Test status
Simulation time 113032909 ps
CPU time 0.7 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 194892 kb
Host smart-8b9c1702-8836-4cf7-ab96-19ac87f1a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388962735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2388962735
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2722123660
Short name T230
Test name
Test status
Simulation time 980824413 ps
CPU time 26.08 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 196264 kb
Host smart-89f44c4a-a5f9-4a97-a9d3-c46b919ba7ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722123660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2722123660
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.446869861
Short name T373
Test name
Test status
Simulation time 297584820 ps
CPU time 0.89 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 196720 kb
Host smart-6b2f67eb-38f7-4cd3-ad1a-efa28eb05c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446869861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.446869861
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.957535579
Short name T489
Test name
Test status
Simulation time 190811365 ps
CPU time 1.05 seconds
Started Apr 30 12:22:44 PM PDT 24
Finished Apr 30 12:22:45 PM PDT 24
Peak memory 196064 kb
Host smart-a77f0603-ec67-4d31-84c5-461256d4bdcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957535579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.957535579
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1284976814
Short name T663
Test name
Test status
Simulation time 145954657 ps
CPU time 1.6 seconds
Started Apr 30 12:20:32 PM PDT 24
Finished Apr 30 12:20:34 PM PDT 24
Peak memory 197916 kb
Host smart-117e5cb0-d5d8-4803-8dd2-b6dcaf72902d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284976814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1284976814
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1656728257
Short name T541
Test name
Test status
Simulation time 376768253 ps
CPU time 2.23 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:30 PM PDT 24
Peak memory 196240 kb
Host smart-a10943af-f8ef-4adb-9d6e-4fd7ee7c8e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656728257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1656728257
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1185940906
Short name T240
Test name
Test status
Simulation time 19545882 ps
CPU time 0.75 seconds
Started Apr 30 12:24:12 PM PDT 24
Finished Apr 30 12:24:14 PM PDT 24
Peak memory 193836 kb
Host smart-c327e750-53e5-4e55-ba07-1df195c79853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185940906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1185940906
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.475644553
Short name T488
Test name
Test status
Simulation time 120832616 ps
CPU time 0.99 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 195596 kb
Host smart-a3dbca11-e9fd-474a-a913-71ab1ae83048
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475644553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.475644553
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1193703112
Short name T538
Test name
Test status
Simulation time 177765711 ps
CPU time 3.11 seconds
Started Apr 30 12:22:30 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 196920 kb
Host smart-fce5a91d-c73a-46d8-91f8-3ed71ce19e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193703112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1193703112
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3454004323
Short name T427
Test name
Test status
Simulation time 78825810 ps
CPU time 1.4 seconds
Started Apr 30 12:20:18 PM PDT 24
Finished Apr 30 12:20:20 PM PDT 24
Peak memory 196516 kb
Host smart-d2c46deb-3721-4752-a0ad-ffaae06f8ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454004323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3454004323
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1081374300
Short name T578
Test name
Test status
Simulation time 102420835 ps
CPU time 0.77 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 195800 kb
Host smart-27286bd7-8300-44be-beae-4256f9a364e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081374300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1081374300
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3796225105
Short name T441
Test name
Test status
Simulation time 75287961141 ps
CPU time 210.52 seconds
Started Apr 30 12:19:06 PM PDT 24
Finished Apr 30 12:22:37 PM PDT 24
Peak memory 197972 kb
Host smart-2e485f48-8b83-49e4-a090-17e50a849132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796225105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3796225105
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.86984017
Short name T31
Test name
Test status
Simulation time 122037730843 ps
CPU time 941.67 seconds
Started Apr 30 12:19:07 PM PDT 24
Finished Apr 30 12:34:49 PM PDT 24
Peak memory 198056 kb
Host smart-366927d1-db52-4c3d-af74-9ba578024731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=86984017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.86984017
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1455140917
Short name T479
Test name
Test status
Simulation time 15771576 ps
CPU time 0.57 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:57 PM PDT 24
Peak memory 194028 kb
Host smart-8bad0db2-5bd8-4c9c-b438-ddd2e9a9d7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455140917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1455140917
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3601898952
Short name T679
Test name
Test status
Simulation time 66469022 ps
CPU time 0.62 seconds
Started Apr 30 12:19:15 PM PDT 24
Finished Apr 30 12:19:16 PM PDT 24
Peak memory 193996 kb
Host smart-81c1b72a-e255-44eb-8e15-c1ccc162d5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601898952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3601898952
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.281446642
Short name T505
Test name
Test status
Simulation time 1553607684 ps
CPU time 21.13 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 196580 kb
Host smart-72285c1b-5a50-4b55-bed3-a5f81b003552
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281446642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.281446642
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2997119676
Short name T447
Test name
Test status
Simulation time 169882879 ps
CPU time 0.72 seconds
Started Apr 30 12:19:52 PM PDT 24
Finished Apr 30 12:19:54 PM PDT 24
Peak memory 195436 kb
Host smart-b00493ca-b892-44b8-b002-5d1818fbbc8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997119676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2997119676
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2325252761
Short name T543
Test name
Test status
Simulation time 272737030 ps
CPU time 1.21 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:22:00 PM PDT 24
Peak memory 195672 kb
Host smart-e0372a6c-2c29-4ab0-865d-49396b329e3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325252761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2325252761
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3701967781
Short name T177
Test name
Test status
Simulation time 220847065 ps
CPU time 2.4 seconds
Started Apr 30 12:19:42 PM PDT 24
Finished Apr 30 12:19:45 PM PDT 24
Peak memory 198104 kb
Host smart-2a5d62bb-83e6-4789-9626-6b0dc8a31d93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701967781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3701967781
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1413372641
Short name T420
Test name
Test status
Simulation time 279831058 ps
CPU time 1.67 seconds
Started Apr 30 12:19:52 PM PDT 24
Finished Apr 30 12:19:54 PM PDT 24
Peak memory 195992 kb
Host smart-77c5949d-6d20-4b82-974c-a4bb9673a125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413372641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1413372641
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.506677470
Short name T303
Test name
Test status
Simulation time 90195624 ps
CPU time 0.76 seconds
Started Apr 30 12:20:48 PM PDT 24
Finished Apr 30 12:20:50 PM PDT 24
Peak memory 195712 kb
Host smart-9d290a3c-f6d1-403d-9a9c-caba3b28a56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506677470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.506677470
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1975891320
Short name T68
Test name
Test status
Simulation time 23476781 ps
CPU time 0.94 seconds
Started Apr 30 12:19:22 PM PDT 24
Finished Apr 30 12:19:24 PM PDT 24
Peak memory 195980 kb
Host smart-f4ccc34d-6938-4f98-ab12-843c0a6216cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975891320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1975891320
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1285987005
Short name T647
Test name
Test status
Simulation time 286158411 ps
CPU time 4.46 seconds
Started Apr 30 12:22:54 PM PDT 24
Finished Apr 30 12:22:59 PM PDT 24
Peak memory 197808 kb
Host smart-6e67302b-6e74-48c9-a150-90ec393ed860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285987005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1285987005
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3836001733
Short name T212
Test name
Test status
Simulation time 201618668 ps
CPU time 0.99 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:57 PM PDT 24
Peak memory 196384 kb
Host smart-c743c0cf-cef1-40a3-b6ae-4bfe2fec64f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836001733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3836001733
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4283955704
Short name T657
Test name
Test status
Simulation time 166420432 ps
CPU time 1.01 seconds
Started Apr 30 12:20:31 PM PDT 24
Finished Apr 30 12:20:32 PM PDT 24
Peak memory 196444 kb
Host smart-ff34f3c8-02eb-43b0-89b8-3c1286796564
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283955704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4283955704
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.138232745
Short name T288
Test name
Test status
Simulation time 33877478769 ps
CPU time 183.95 seconds
Started Apr 30 12:19:40 PM PDT 24
Finished Apr 30 12:22:45 PM PDT 24
Peak memory 198204 kb
Host smart-589c8ff5-6c06-47a2-a8aa-4df47c00e7cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138232745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.138232745
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3454780998
Short name T629
Test name
Test status
Simulation time 89693826100 ps
CPU time 1716.38 seconds
Started Apr 30 12:20:45 PM PDT 24
Finished Apr 30 12:49:23 PM PDT 24
Peak memory 198412 kb
Host smart-9c5f9665-0646-4971-823b-7f1b98017349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3454780998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3454780998
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.660173729
Short name T108
Test name
Test status
Simulation time 24303237 ps
CPU time 0.61 seconds
Started Apr 30 12:19:45 PM PDT 24
Finished Apr 30 12:19:47 PM PDT 24
Peak memory 194452 kb
Host smart-37a7611d-598a-47aa-8523-27db9603e7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660173729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.660173729
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1909945044
Short name T159
Test name
Test status
Simulation time 141053340 ps
CPU time 0.83 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:56 PM PDT 24
Peak memory 196164 kb
Host smart-d1478f54-6640-4cbe-93ec-b8f94c9bfc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909945044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1909945044
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1840714544
Short name T575
Test name
Test status
Simulation time 410443064 ps
CPU time 21.25 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:49 PM PDT 24
Peak memory 197740 kb
Host smart-efcdb8f2-b2c9-4c14-b03e-3a6d98250675
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840714544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1840714544
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1125029899
Short name T133
Test name
Test status
Simulation time 168399504 ps
CPU time 0.74 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 196396 kb
Host smart-c18bdf85-d17f-4014-ae93-713ed4f52a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125029899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1125029899
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2554601321
Short name T393
Test name
Test status
Simulation time 25531770 ps
CPU time 0.83 seconds
Started Apr 30 12:19:57 PM PDT 24
Finished Apr 30 12:19:59 PM PDT 24
Peak memory 195596 kb
Host smart-78fa2c0b-8e3e-47fa-9ee3-66504dd4144d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554601321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2554601321
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3394849887
Short name T654
Test name
Test status
Simulation time 68732013 ps
CPU time 2.82 seconds
Started Apr 30 12:19:24 PM PDT 24
Finished Apr 30 12:19:28 PM PDT 24
Peak memory 198068 kb
Host smart-a64c521a-c8b4-4d5f-a3e6-acda92ee55f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394849887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3394849887
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1153631253
Short name T568
Test name
Test status
Simulation time 401203727 ps
CPU time 2.29 seconds
Started Apr 30 12:23:18 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 197056 kb
Host smart-2c571092-c5d1-43c2-9645-e943e0abddc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153631253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1153631253
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1687841475
Short name T711
Test name
Test status
Simulation time 67997670 ps
CPU time 1.24 seconds
Started Apr 30 12:22:39 PM PDT 24
Finished Apr 30 12:22:42 PM PDT 24
Peak memory 196112 kb
Host smart-9cf357d2-5976-477f-bb6b-f4b2269cf938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687841475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1687841475
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3201636107
Short name T228
Test name
Test status
Simulation time 74385402 ps
CPU time 1.23 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 196924 kb
Host smart-da5962a4-c626-4784-a066-7042bf4c886c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201636107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3201636107
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.821199978
Short name T6
Test name
Test status
Simulation time 618040486 ps
CPU time 6.35 seconds
Started Apr 30 12:19:40 PM PDT 24
Finished Apr 30 12:19:47 PM PDT 24
Peak memory 198000 kb
Host smart-16a18e1a-829c-44b4-b7cd-843b5f0684d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821199978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.821199978
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1708596376
Short name T272
Test name
Test status
Simulation time 92926330 ps
CPU time 1.28 seconds
Started Apr 30 12:24:26 PM PDT 24
Finished Apr 30 12:24:29 PM PDT 24
Peak memory 196532 kb
Host smart-f020050d-bfd1-4e01-92b2-1912817151c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708596376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1708596376
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3859007599
Short name T685
Test name
Test status
Simulation time 77730455 ps
CPU time 1.45 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 196424 kb
Host smart-b43aeb5c-0533-4863-bbaf-1b1ac93e7e28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859007599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3859007599
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2840062118
Short name T655
Test name
Test status
Simulation time 27296806320 ps
CPU time 169.42 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:24:57 PM PDT 24
Peak memory 197856 kb
Host smart-7d7d3efc-aa21-45ab-b5d1-51772ac52e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840062118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2840062118
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3165920484
Short name T41
Test name
Test status
Simulation time 26181802 ps
CPU time 0.6 seconds
Started Apr 30 12:19:36 PM PDT 24
Finished Apr 30 12:19:38 PM PDT 24
Peak memory 193940 kb
Host smart-09b05530-9748-47ad-a6d8-8ba9d81f7763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165920484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3165920484
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3977032249
Short name T167
Test name
Test status
Simulation time 26441913 ps
CPU time 0.81 seconds
Started Apr 30 12:22:02 PM PDT 24
Finished Apr 30 12:22:04 PM PDT 24
Peak memory 196248 kb
Host smart-446c1091-1fa5-4632-a38c-8a60f7e3f1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977032249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3977032249
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.62248699
Short name T375
Test name
Test status
Simulation time 332510503 ps
CPU time 7.74 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 196416 kb
Host smart-2c64e225-0dd6-4f46-b8ac-c764d1fc4c5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62248699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stress
.62248699
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1266415216
Short name T690
Test name
Test status
Simulation time 28024063 ps
CPU time 0.65 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 194592 kb
Host smart-ba45676a-97fb-4c6a-a4f9-002665bfd2c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266415216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1266415216
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1391322287
Short name T321
Test name
Test status
Simulation time 72930815 ps
CPU time 0.82 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:22:08 PM PDT 24
Peak memory 195972 kb
Host smart-a58dcf57-c32d-491a-b308-259dae4ea5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391322287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1391322287
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2080250130
Short name T157
Test name
Test status
Simulation time 215966060 ps
CPU time 2.35 seconds
Started Apr 30 12:23:11 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 197840 kb
Host smart-f67ecc9b-4c9a-41a2-b782-f2bf6d574c3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080250130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2080250130
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.363057230
Short name T703
Test name
Test status
Simulation time 228178607 ps
CPU time 3.4 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 197720 kb
Host smart-a95a5152-0f74-418c-bf75-7126519c4d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363057230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
363057230
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3759201750
Short name T437
Test name
Test status
Simulation time 80523068 ps
CPU time 0.87 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 195696 kb
Host smart-42aac686-9fc0-445d-97d5-bca5f96ee01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759201750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3759201750
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.227834249
Short name T254
Test name
Test status
Simulation time 57647696 ps
CPU time 0.8 seconds
Started Apr 30 12:19:36 PM PDT 24
Finished Apr 30 12:19:38 PM PDT 24
Peak memory 196172 kb
Host smart-5e70b84c-4201-4136-912d-ee9d18cfeaf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227834249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.227834249
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1583168823
Short name T720
Test name
Test status
Simulation time 347645806 ps
CPU time 1.36 seconds
Started Apr 30 12:20:32 PM PDT 24
Finished Apr 30 12:20:34 PM PDT 24
Peak memory 197820 kb
Host smart-cb39f4c4-3879-45b1-be52-c19901f09eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583168823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1583168823
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2645747326
Short name T235
Test name
Test status
Simulation time 66911809 ps
CPU time 1.13 seconds
Started Apr 30 12:19:27 PM PDT 24
Finished Apr 30 12:19:29 PM PDT 24
Peak memory 196096 kb
Host smart-b0953bfa-109a-497d-a144-21c14247c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645747326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2645747326
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.877232478
Short name T603
Test name
Test status
Simulation time 113603879 ps
CPU time 0.95 seconds
Started Apr 30 12:23:18 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 195504 kb
Host smart-9c1297ec-8eab-4f54-a73d-0d46e7a09456
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877232478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.877232478
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.793080697
Short name T340
Test name
Test status
Simulation time 7452199265 ps
CPU time 199.12 seconds
Started Apr 30 12:19:48 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 198412 kb
Host smart-9721c17e-b871-455e-b2fb-6e11758ed77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793080697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.793080697
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2535597427
Short name T531
Test name
Test status
Simulation time 43130899 ps
CPU time 0.58 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:15 PM PDT 24
Peak memory 192356 kb
Host smart-01348a6b-4e28-4e0a-9c80-d15656bc212e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535597427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2535597427
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4036728864
Short name T650
Test name
Test status
Simulation time 51235354 ps
CPU time 0.82 seconds
Started Apr 30 12:24:06 PM PDT 24
Finished Apr 30 12:24:07 PM PDT 24
Peak memory 196236 kb
Host smart-ac121d97-50f7-4fc2-b079-fa5f52eba5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036728864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4036728864
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2013672228
Short name T210
Test name
Test status
Simulation time 1629070093 ps
CPU time 20.24 seconds
Started Apr 30 12:24:26 PM PDT 24
Finished Apr 30 12:24:48 PM PDT 24
Peak memory 196664 kb
Host smart-ce040cf6-8061-44b3-a044-6a4b7f570eaa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013672228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2013672228
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1024753045
Short name T384
Test name
Test status
Simulation time 351525098 ps
CPU time 0.86 seconds
Started Apr 30 12:19:56 PM PDT 24
Finished Apr 30 12:19:57 PM PDT 24
Peak memory 196872 kb
Host smart-237e5350-0465-499b-a91e-57bc8770b2d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024753045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1024753045
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3153701049
Short name T144
Test name
Test status
Simulation time 101753494 ps
CPU time 1.38 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:29 PM PDT 24
Peak memory 196740 kb
Host smart-ed3b0e6a-e3bc-4a25-924d-7443c4c64176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153701049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3153701049
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.215377261
Short name T569
Test name
Test status
Simulation time 59718864 ps
CPU time 2.34 seconds
Started Apr 30 12:19:50 PM PDT 24
Finished Apr 30 12:19:53 PM PDT 24
Peak memory 197888 kb
Host smart-e2558ea7-7f4c-45ed-bbcb-184130b7800e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215377261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.215377261
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1448934797
Short name T110
Test name
Test status
Simulation time 117599481 ps
CPU time 1.5 seconds
Started Apr 30 12:22:42 PM PDT 24
Finished Apr 30 12:22:44 PM PDT 24
Peak memory 195864 kb
Host smart-de8797a1-be9c-40d2-849f-d8e116034009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448934797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1448934797
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1902340072
Short name T676
Test name
Test status
Simulation time 57988567 ps
CPU time 0.87 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 196340 kb
Host smart-c4c6e564-766b-4946-89f7-e834b916f0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902340072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1902340072
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1952448462
Short name T362
Test name
Test status
Simulation time 199989549 ps
CPU time 0.97 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:29 PM PDT 24
Peak memory 195756 kb
Host smart-bbc71e8d-c06f-4cee-bbb0-def4088818d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952448462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1952448462
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.570708647
Short name T322
Test name
Test status
Simulation time 49571036 ps
CPU time 2.1 seconds
Started Apr 30 12:23:53 PM PDT 24
Finished Apr 30 12:23:57 PM PDT 24
Peak memory 196232 kb
Host smart-d1c5c0d4-b00c-44fd-8adc-2d5fa5405559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570708647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.570708647
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2297128115
Short name T709
Test name
Test status
Simulation time 280129437 ps
CPU time 1.31 seconds
Started Apr 30 12:22:21 PM PDT 24
Finished Apr 30 12:22:23 PM PDT 24
Peak memory 197764 kb
Host smart-2d5f2794-c060-4f15-abcf-4e5b487bd59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297128115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2297128115
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.718642380
Short name T429
Test name
Test status
Simulation time 41668186 ps
CPU time 1.1 seconds
Started Apr 30 12:21:42 PM PDT 24
Finished Apr 30 12:21:44 PM PDT 24
Peak memory 195636 kb
Host smart-0aa4d112-7539-40fc-832d-60251f7df3e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718642380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.718642380
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.233023964
Short name T452
Test name
Test status
Simulation time 7546006300 ps
CPU time 195.94 seconds
Started Apr 30 12:19:50 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 198164 kb
Host smart-4ad0d4ff-0482-460d-81fb-500e7a87e848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233023964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.233023964
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3792038565
Short name T66
Test name
Test status
Simulation time 56386439583 ps
CPU time 1400.3 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:45:35 PM PDT 24
Peak memory 197976 kb
Host smart-4065e1ed-4766-4f4d-badd-167c87117b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3792038565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3792038565
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3949737249
Short name T499
Test name
Test status
Simulation time 35662625 ps
CPU time 0.59 seconds
Started Apr 30 12:18:41 PM PDT 24
Finished Apr 30 12:18:42 PM PDT 24
Peak memory 194164 kb
Host smart-961bab32-e6ec-426c-ac7b-9e38a1e55bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949737249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3949737249
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3774092456
Short name T278
Test name
Test status
Simulation time 36734396 ps
CPU time 0.65 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:17:58 PM PDT 24
Peak memory 194280 kb
Host smart-d530c7d2-2bde-4ed5-a6a7-83cf826c2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774092456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3774092456
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3919935144
Short name T559
Test name
Test status
Simulation time 461133218 ps
CPU time 5.21 seconds
Started Apr 30 12:20:57 PM PDT 24
Finished Apr 30 12:21:03 PM PDT 24
Peak memory 195256 kb
Host smart-2132a90f-76fd-4a65-ac5b-439edf7a870d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919935144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3919935144
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1327753442
Short name T186
Test name
Test status
Simulation time 129614962 ps
CPU time 0.99 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 196148 kb
Host smart-45a5b91a-ef81-4177-9ca6-84a07048de91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327753442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1327753442
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1966477966
Short name T24
Test name
Test status
Simulation time 179533811 ps
CPU time 1.38 seconds
Started Apr 30 12:20:56 PM PDT 24
Finished Apr 30 12:20:58 PM PDT 24
Peak memory 196808 kb
Host smart-f6c6b0b5-9896-412c-b20a-f35cdad6dd48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966477966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1966477966
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1337679363
Short name T145
Test name
Test status
Simulation time 214463457 ps
CPU time 2.73 seconds
Started Apr 30 12:18:38 PM PDT 24
Finished Apr 30 12:18:41 PM PDT 24
Peak memory 196284 kb
Host smart-505eb71b-9e31-4f5d-bb75-38de73a30152
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337679363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1337679363
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1721710012
Short name T338
Test name
Test status
Simulation time 633359460 ps
CPU time 3.36 seconds
Started Apr 30 12:17:27 PM PDT 24
Finished Apr 30 12:17:31 PM PDT 24
Peak memory 197016 kb
Host smart-beb4dc0c-75cd-4467-a66b-69fef46337c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721710012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1721710012
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2366151765
Short name T609
Test name
Test status
Simulation time 141302811 ps
CPU time 0.93 seconds
Started Apr 30 12:17:11 PM PDT 24
Finished Apr 30 12:17:13 PM PDT 24
Peak memory 196404 kb
Host smart-711d7771-d846-40a8-861d-e4a53eadb81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366151765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2366151765
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1521995329
Short name T497
Test name
Test status
Simulation time 33871170 ps
CPU time 0.74 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 195864 kb
Host smart-9f16b7e9-0f59-426a-9c50-a322ef19663f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521995329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1521995329
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2112947868
Short name T8
Test name
Test status
Simulation time 1117190215 ps
CPU time 1.17 seconds
Started Apr 30 12:18:41 PM PDT 24
Finished Apr 30 12:18:43 PM PDT 24
Peak memory 198000 kb
Host smart-6d62a29b-7003-41d6-bd65-dc909495237c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112947868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2112947868
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3568992360
Short name T50
Test name
Test status
Simulation time 316414090 ps
CPU time 0.99 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 212772 kb
Host smart-121c6325-8bcf-47f6-8e0b-4f7f30df6af2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568992360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3568992360
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2146135240
Short name T291
Test name
Test status
Simulation time 177593345 ps
CPU time 1.05 seconds
Started Apr 30 12:17:05 PM PDT 24
Finished Apr 30 12:17:07 PM PDT 24
Peak memory 196104 kb
Host smart-0382f10c-784b-4811-8f7a-4e9d7848667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146135240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2146135240
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.649805747
Short name T553
Test name
Test status
Simulation time 122883041 ps
CPU time 1.12 seconds
Started Apr 30 12:17:15 PM PDT 24
Finished Apr 30 12:17:16 PM PDT 24
Peak memory 197176 kb
Host smart-114604ef-7c14-42df-a101-efe522f19748
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649805747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.649805747
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3147863926
Short name T400
Test name
Test status
Simulation time 32118774030 ps
CPU time 101.53 seconds
Started Apr 30 12:17:18 PM PDT 24
Finished Apr 30 12:19:01 PM PDT 24
Peak memory 197972 kb
Host smart-e2f54e39-5f26-4112-97e5-5dc77ea79294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147863926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3147863926
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1708507937
Short name T442
Test name
Test status
Simulation time 38126383 ps
CPU time 0.54 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 193340 kb
Host smart-d5f31c8b-580d-48c5-af43-b116f998c54e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708507937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1708507937
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1187259250
Short name T470
Test name
Test status
Simulation time 71364465 ps
CPU time 0.7 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 194920 kb
Host smart-72838d81-744d-4b36-b23b-e17b2e90bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187259250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1187259250
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2593469032
Short name T143
Test name
Test status
Simulation time 662014638 ps
CPU time 22.25 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:28 PM PDT 24
Peak memory 195088 kb
Host smart-c0de47c1-d874-447b-bf97-76eb270757f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593469032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2593469032
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.683080542
Short name T550
Test name
Test status
Simulation time 66092566 ps
CPU time 0.9 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 196920 kb
Host smart-1c123ceb-c3d8-46b4-8dee-0a06343c28cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683080542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.683080542
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1248303873
Short name T544
Test name
Test status
Simulation time 49317138 ps
CPU time 1.24 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 196444 kb
Host smart-0d7d36c7-9fa2-4a07-a37e-dd7d8efade97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248303873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1248303873
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2107205319
Short name T208
Test name
Test status
Simulation time 86782178 ps
CPU time 1.56 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 197908 kb
Host smart-3b1a30bf-047f-41e0-a605-957259c9dea2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107205319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2107205319
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2437644808
Short name T406
Test name
Test status
Simulation time 101145623 ps
CPU time 2.26 seconds
Started Apr 30 12:19:59 PM PDT 24
Finished Apr 30 12:20:01 PM PDT 24
Peak memory 197004 kb
Host smart-fb5b2726-1947-4bc4-8785-cf7d7bd64848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437644808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2437644808
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2384747599
Short name T343
Test name
Test status
Simulation time 30699596 ps
CPU time 1.21 seconds
Started Apr 30 12:19:58 PM PDT 24
Finished Apr 30 12:20:00 PM PDT 24
Peak memory 197864 kb
Host smart-a07962ec-f7b8-4efd-a5c7-41f4d8fc9daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384747599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2384747599
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1103127559
Short name T344
Test name
Test status
Simulation time 71336397 ps
CPU time 0.75 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 195112 kb
Host smart-000fe9c1-4d76-444d-ac0c-61bb9a5ecc39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103127559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1103127559
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.779482810
Short name T408
Test name
Test status
Simulation time 1500657069 ps
CPU time 6.02 seconds
Started Apr 30 12:20:14 PM PDT 24
Finished Apr 30 12:20:21 PM PDT 24
Peak memory 198176 kb
Host smart-175bf103-d77a-43dd-9fa9-5bd1fcc88bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779482810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.779482810
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1437845075
Short name T215
Test name
Test status
Simulation time 26672031 ps
CPU time 0.82 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 193808 kb
Host smart-3cf805a3-2925-4a59-b3e0-ade11ae7db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437845075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1437845075
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.956978718
Short name T317
Test name
Test status
Simulation time 194914950 ps
CPU time 1.52 seconds
Started Apr 30 12:20:30 PM PDT 24
Finished Apr 30 12:20:32 PM PDT 24
Peak memory 197076 kb
Host smart-1d2b74f1-9065-4888-9481-45a41fa33579
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956978718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.956978718
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2229303644
Short name T585
Test name
Test status
Simulation time 1457765155 ps
CPU time 29.8 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:29 PM PDT 24
Peak memory 197632 kb
Host smart-90e07046-a1ae-4305-ac8e-d92fd5e3a77c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229303644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2229303644
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.15356356
Short name T224
Test name
Test status
Simulation time 35580250 ps
CPU time 0.55 seconds
Started Apr 30 12:22:31 PM PDT 24
Finished Apr 30 12:22:32 PM PDT 24
Peak memory 193708 kb
Host smart-f5f526c3-c841-4653-90e1-781f93cdfaa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.15356356
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3717132395
Short name T604
Test name
Test status
Simulation time 35718278 ps
CPU time 0.79 seconds
Started Apr 30 12:20:15 PM PDT 24
Finished Apr 30 12:20:16 PM PDT 24
Peak memory 195236 kb
Host smart-00a40047-e66e-41fc-9abb-56e996c32e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717132395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3717132395
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1154444763
Short name T337
Test name
Test status
Simulation time 1322151271 ps
CPU time 15.88 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:27 PM PDT 24
Peak memory 195196 kb
Host smart-842e8b06-cc2b-483d-9da7-e69d1947c1fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154444763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1154444763
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2045638387
Short name T233
Test name
Test status
Simulation time 236461046 ps
CPU time 0.85 seconds
Started Apr 30 12:22:40 PM PDT 24
Finished Apr 30 12:22:42 PM PDT 24
Peak memory 195584 kb
Host smart-bcc0ee5b-6a38-4342-a4ce-6cf9722fc8b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045638387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2045638387
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3844818530
Short name T599
Test name
Test status
Simulation time 249195272 ps
CPU time 0.99 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 195548 kb
Host smart-b39e55db-ed45-4b47-92e5-083313e0a495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844818530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3844818530
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1173917931
Short name T699
Test name
Test status
Simulation time 54703815 ps
CPU time 2.21 seconds
Started Apr 30 12:20:09 PM PDT 24
Finished Apr 30 12:20:12 PM PDT 24
Peak memory 197868 kb
Host smart-6d967b5f-d0fc-4432-bef9-d5bf1aeb42a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173917931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1173917931
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2950124862
Short name T433
Test name
Test status
Simulation time 47834602 ps
CPU time 1.57 seconds
Started Apr 30 12:21:08 PM PDT 24
Finished Apr 30 12:21:10 PM PDT 24
Peak memory 195904 kb
Host smart-10efd5e7-a3b9-4b01-8668-9aab86284f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950124862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2950124862
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2908609039
Short name T670
Test name
Test status
Simulation time 75575250 ps
CPU time 1.44 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:22:09 PM PDT 24
Peak memory 195196 kb
Host smart-492abfec-980c-4b23-b9ff-8e72c1bda791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908609039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2908609039
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2598558021
Short name T405
Test name
Test status
Simulation time 37186108 ps
CPU time 0.95 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:05 PM PDT 24
Peak memory 195924 kb
Host smart-2a48aeb8-f580-40ff-82be-00c8c34a1fe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598558021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2598558021
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.532107565
Short name T697
Test name
Test status
Simulation time 335222783 ps
CPU time 3.6 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 197616 kb
Host smart-30035ba9-83ec-4848-a135-e371bca34708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532107565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.532107565
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.918654653
Short name T336
Test name
Test status
Simulation time 205927809 ps
CPU time 1.04 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195492 kb
Host smart-afe3a1af-c6b1-464b-934d-423eb3b3bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918654653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.918654653
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.885782160
Short name T434
Test name
Test status
Simulation time 131819994 ps
CPU time 1.04 seconds
Started Apr 30 12:21:00 PM PDT 24
Finished Apr 30 12:21:02 PM PDT 24
Peak memory 195700 kb
Host smart-648ce220-3fac-4759-9d1e-6d895d5ffb32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885782160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.885782160
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2615400361
Short name T686
Test name
Test status
Simulation time 19056246014 ps
CPU time 46.66 seconds
Started Apr 30 12:22:31 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 197944 kb
Host smart-e90681a8-ed1f-4dcc-9a1f-76cedac464bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615400361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2615400361
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3467666270
Short name T267
Test name
Test status
Simulation time 23222216 ps
CPU time 0.56 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 194336 kb
Host smart-661d7289-c1f6-4f89-a673-f6fc6bb0f7e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467666270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3467666270
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2798457279
Short name T539
Test name
Test status
Simulation time 17537159 ps
CPU time 0.62 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 193364 kb
Host smart-b9360098-f624-4b5a-b593-4d27e71a6cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798457279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2798457279
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1536411711
Short name T692
Test name
Test status
Simulation time 623188956 ps
CPU time 14.66 seconds
Started Apr 30 12:20:24 PM PDT 24
Finished Apr 30 12:20:39 PM PDT 24
Peak memory 196976 kb
Host smart-ca8e488e-9b96-4725-a0ae-a1bb2a8e075e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536411711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1536411711
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1060213956
Short name T636
Test name
Test status
Simulation time 145560687 ps
CPU time 0.81 seconds
Started Apr 30 12:22:54 PM PDT 24
Finished Apr 30 12:22:56 PM PDT 24
Peak memory 195932 kb
Host smart-9b8c9f4e-3f8c-4566-ba0d-371e290bff3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060213956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1060213956
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1627341336
Short name T221
Test name
Test status
Simulation time 131512007 ps
CPU time 1.16 seconds
Started Apr 30 12:22:30 PM PDT 24
Finished Apr 30 12:22:32 PM PDT 24
Peak memory 195704 kb
Host smart-e099e9c8-2029-4a82-9202-775842f8c241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627341336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1627341336
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3231701770
Short name T309
Test name
Test status
Simulation time 65554026 ps
CPU time 2.65 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 197924 kb
Host smart-60d21f5c-917a-4a21-8a52-e04622f096df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231701770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3231701770
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2649102090
Short name T273
Test name
Test status
Simulation time 318821526 ps
CPU time 3.1 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 197656 kb
Host smart-ca297c6e-202b-48a8-ba6d-940b08adb2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649102090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2649102090
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.70877903
Short name T506
Test name
Test status
Simulation time 96157271 ps
CPU time 1.19 seconds
Started Apr 30 12:22:15 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 195868 kb
Host smart-d655c763-91c9-4230-94fe-1d217abb5a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70877903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.70877903
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2296795633
Short name T608
Test name
Test status
Simulation time 15400010 ps
CPU time 0.65 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:06 PM PDT 24
Peak memory 193972 kb
Host smart-a0cfa235-f82b-43b5-aba0-3ae63b377425
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296795633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2296795633
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1516832246
Short name T9
Test name
Test status
Simulation time 1911542672 ps
CPU time 3.7 seconds
Started Apr 30 12:20:24 PM PDT 24
Finished Apr 30 12:20:28 PM PDT 24
Peak memory 197900 kb
Host smart-7514aa58-127c-451a-bb6c-f7feb98fc776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516832246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1516832246
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3002266138
Short name T560
Test name
Test status
Simulation time 64400682 ps
CPU time 1.28 seconds
Started Apr 30 12:20:26 PM PDT 24
Finished Apr 30 12:20:28 PM PDT 24
Peak memory 196668 kb
Host smart-cb6632c5-8c3f-471e-b4ba-ae9fcd29773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002266138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3002266138
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.292212269
Short name T704
Test name
Test status
Simulation time 212267305 ps
CPU time 1.35 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 196728 kb
Host smart-e9c5c393-4596-48bf-b5b2-db34bec44e7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292212269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.292212269
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2804967977
Short name T21
Test name
Test status
Simulation time 28354292415 ps
CPU time 167.76 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:25:01 PM PDT 24
Peak memory 197908 kb
Host smart-a0d55cd1-8936-4afe-9d90-e01e802af565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804967977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2804967977
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2423048642
Short name T371
Test name
Test status
Simulation time 49983011 ps
CPU time 0.54 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 193656 kb
Host smart-f401cf19-d747-4c18-a993-d84ebf31d906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423048642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2423048642
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.272944845
Short name T315
Test name
Test status
Simulation time 20372424 ps
CPU time 0.77 seconds
Started Apr 30 12:21:57 PM PDT 24
Finished Apr 30 12:21:59 PM PDT 24
Peak memory 194652 kb
Host smart-74cad6cc-617f-43e9-8eea-b2f6a2c26d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272944845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.272944845
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.378362741
Short name T548
Test name
Test status
Simulation time 721316278 ps
CPU time 20.27 seconds
Started Apr 30 12:21:46 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 197084 kb
Host smart-05e72278-f7b9-4e1d-9cf3-3f890de0be64
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378362741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.378362741
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3216530503
Short name T341
Test name
Test status
Simulation time 417359455 ps
CPU time 0.78 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:22:01 PM PDT 24
Peak memory 195044 kb
Host smart-492ff1b1-d75d-484c-a651-a981f565fca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216530503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3216530503
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4253466237
Short name T556
Test name
Test status
Simulation time 155265261 ps
CPU time 0.82 seconds
Started Apr 30 12:20:38 PM PDT 24
Finished Apr 30 12:20:39 PM PDT 24
Peak memory 195588 kb
Host smart-c1f9b771-0bc6-43e4-b0b2-340eb69f020b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253466237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4253466237
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1636347808
Short name T342
Test name
Test status
Simulation time 1381524709 ps
CPU time 3.31 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:20 PM PDT 24
Peak memory 196192 kb
Host smart-c8572ba1-4ba3-435d-9f59-ab00c7fe1783
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636347808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1636347808
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.58565158
Short name T490
Test name
Test status
Simulation time 297826038 ps
CPU time 2.74 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:03 PM PDT 24
Peak memory 196700 kb
Host smart-1ea9d3fe-406d-4fe6-9253-a98627cd9e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58565158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.58565158
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1146425136
Short name T482
Test name
Test status
Simulation time 52027271 ps
CPU time 1.09 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 196472 kb
Host smart-54cb53b2-fce4-4955-997d-ac78c5462f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146425136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1146425136
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3509439259
Short name T572
Test name
Test status
Simulation time 267132997 ps
CPU time 0.73 seconds
Started Apr 30 12:23:58 PM PDT 24
Finished Apr 30 12:24:00 PM PDT 24
Peak memory 195420 kb
Host smart-9e209cb0-9f23-4837-a841-eaff7a7acfd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509439259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3509439259
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.633699881
Short name T483
Test name
Test status
Simulation time 1515208074 ps
CPU time 5.78 seconds
Started Apr 30 12:21:55 PM PDT 24
Finished Apr 30 12:22:02 PM PDT 24
Peak memory 196936 kb
Host smart-463b317e-4f17-48d0-a196-305183815c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633699881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.633699881
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2951464008
Short name T656
Test name
Test status
Simulation time 173382238 ps
CPU time 1 seconds
Started Apr 30 12:21:35 PM PDT 24
Finished Apr 30 12:21:37 PM PDT 24
Peak memory 195348 kb
Host smart-28957270-2473-49a2-83df-11af092dfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951464008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2951464008
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1599719364
Short name T652
Test name
Test status
Simulation time 380899642 ps
CPU time 1.18 seconds
Started Apr 30 12:20:25 PM PDT 24
Finished Apr 30 12:20:27 PM PDT 24
Peak memory 195536 kb
Host smart-ed34c69d-d506-4b4a-bce6-397cd8824e1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599719364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1599719364
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3870434892
Short name T528
Test name
Test status
Simulation time 6671910803 ps
CPU time 158.56 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:25:34 PM PDT 24
Peak memory 198084 kb
Host smart-a1ff0d37-b00f-438a-b5da-c5806397e88d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870434892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3870434892
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1977812838
Short name T381
Test name
Test status
Simulation time 18525486 ps
CPU time 0.55 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:13 PM PDT 24
Peak memory 193532 kb
Host smart-bea7ac28-2321-4849-a636-40ef29b8270d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977812838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1977812838
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.379657404
Short name T527
Test name
Test status
Simulation time 106275841 ps
CPU time 0.76 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:01 PM PDT 24
Peak memory 194976 kb
Host smart-30b56e1b-5425-4316-8d55-d3db58cb9786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379657404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.379657404
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2433465736
Short name T130
Test name
Test status
Simulation time 261776614 ps
CPU time 8.45 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 195244 kb
Host smart-d42fb957-d1d7-4d90-8955-8371072e8d72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433465736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2433465736
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2050846842
Short name T607
Test name
Test status
Simulation time 122321518 ps
CPU time 0.85 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 194476 kb
Host smart-b4db468c-a84b-4368-b962-3af32b0c6658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050846842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2050846842
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2552840730
Short name T587
Test name
Test status
Simulation time 40738126 ps
CPU time 1.02 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 195624 kb
Host smart-b7abd082-4269-42fc-a177-f918209a83f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552840730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2552840730
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3812716573
Short name T526
Test name
Test status
Simulation time 314450701 ps
CPU time 2.86 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:13 PM PDT 24
Peak memory 197456 kb
Host smart-9c4cb78c-3ddf-42b0-add2-9fe52760e84a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812716573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3812716573
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.11451122
Short name T446
Test name
Test status
Simulation time 216978738 ps
CPU time 2.92 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 195772 kb
Host smart-40567b8f-70c8-4254-a659-44cfc1038ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11451122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.11451122
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1204289643
Short name T225
Test name
Test status
Simulation time 49659688 ps
CPU time 1.11 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:02 PM PDT 24
Peak memory 196368 kb
Host smart-db4462f8-ffeb-48b6-aeb5-5b4503a9399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204289643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1204289643
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.869064177
Short name T583
Test name
Test status
Simulation time 45301916 ps
CPU time 1.03 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 195664 kb
Host smart-71b869c1-8c9e-45c2-bdfd-621e419c7bc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869064177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.869064177
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.213422149
Short name T279
Test name
Test status
Simulation time 305106545 ps
CPU time 2.46 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:22:04 PM PDT 24
Peak memory 197632 kb
Host smart-28ba1f40-88a6-4e8a-892b-796653046b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213422149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.213422149
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2456574163
Short name T332
Test name
Test status
Simulation time 249921502 ps
CPU time 0.99 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195240 kb
Host smart-483f19fc-83a5-4785-8837-e41d2d06fcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456574163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2456574163
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.70908743
Short name T456
Test name
Test status
Simulation time 122312436 ps
CPU time 1.21 seconds
Started Apr 30 12:22:01 PM PDT 24
Finished Apr 30 12:22:03 PM PDT 24
Peak memory 196300 kb
Host smart-f75aa3ad-37e0-45e8-9d28-9d9171d8ca65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70908743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.70908743
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3073698433
Short name T1
Test name
Test status
Simulation time 4898808002 ps
CPU time 52.07 seconds
Started Apr 30 12:22:09 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 197968 kb
Host smart-51f4755a-3fcb-4a74-8ab8-82a550f4cc26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073698433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3073698433
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3204306668
Short name T40
Test name
Test status
Simulation time 14908700 ps
CPU time 0.61 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:15 PM PDT 24
Peak memory 193604 kb
Host smart-b771b4e7-a695-41f5-83d2-2df470eeec47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204306668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3204306668
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3391714134
Short name T187
Test name
Test status
Simulation time 18219277 ps
CPU time 0.65 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 192940 kb
Host smart-541da2a4-1144-4433-ace6-a88bc71dde21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391714134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3391714134
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2467612097
Short name T605
Test name
Test status
Simulation time 2219807175 ps
CPU time 15.49 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:29 PM PDT 24
Peak memory 197788 kb
Host smart-86b5fa58-7c64-4ba1-88c4-9f8b58626cb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467612097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2467612097
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1935734637
Short name T57
Test name
Test status
Simulation time 95448500 ps
CPU time 0.68 seconds
Started Apr 30 12:22:15 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 194448 kb
Host smart-6ba60f6f-4d15-4dfe-ade0-e43dd928db06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935734637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1935734637
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.37536299
Short name T469
Test name
Test status
Simulation time 28088192 ps
CPU time 0.62 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 194692 kb
Host smart-131d6bdb-d5c7-4d6e-b83b-64f1b59babfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37536299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.37536299
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1262083778
Short name T115
Test name
Test status
Simulation time 121063190 ps
CPU time 1.36 seconds
Started Apr 30 12:22:15 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 196320 kb
Host smart-6287d45d-4314-448d-91db-ebe22cf553b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262083778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1262083778
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2595740669
Short name T161
Test name
Test status
Simulation time 213768602 ps
CPU time 2.95 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 194364 kb
Host smart-6b1cac2c-aac5-4046-a45c-e2b24387ea10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595740669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2595740669
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.731084433
Short name T422
Test name
Test status
Simulation time 271596228 ps
CPU time 1.24 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 196212 kb
Host smart-f308537e-e9aa-4ed1-93ef-2145f74ff94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731084433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.731084433
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.26696170
Short name T155
Test name
Test status
Simulation time 62151349 ps
CPU time 0.69 seconds
Started Apr 30 12:22:16 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 195176 kb
Host smart-d3795778-6a01-443d-9565-2ab2aebfbe68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_
pulldown.26696170
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3929109741
Short name T705
Test name
Test status
Simulation time 45990728 ps
CPU time 1.84 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 196316 kb
Host smart-0c79e907-f330-4470-910f-f4fb7b2bfdc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929109741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3929109741
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2248608087
Short name T346
Test name
Test status
Simulation time 268830521 ps
CPU time 0.81 seconds
Started Apr 30 12:22:17 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 195944 kb
Host smart-0e540bee-796f-4539-aa65-baf5f8d545db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248608087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2248608087
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4050945385
Short name T54
Test name
Test status
Simulation time 84401351 ps
CPU time 1.37 seconds
Started Apr 30 12:22:15 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 196868 kb
Host smart-5bf14bcf-64cb-4855-aece-1a86151e6825
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050945385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4050945385
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2660598122
Short name T392
Test name
Test status
Simulation time 62633348269 ps
CPU time 171.52 seconds
Started Apr 30 12:20:51 PM PDT 24
Finished Apr 30 12:23:43 PM PDT 24
Peak memory 198128 kb
Host smart-9aaca14d-41cf-40b7-9eeb-030681c89a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660598122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2660598122
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.4060178789
Short name T62
Test name
Test status
Simulation time 74853005758 ps
CPU time 1696.88 seconds
Started Apr 30 12:22:31 PM PDT 24
Finished Apr 30 12:50:49 PM PDT 24
Peak memory 198048 kb
Host smart-83ff58ea-5aba-4dfa-94ab-23ba8dd80d06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4060178789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.4060178789
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.895331251
Short name T542
Test name
Test status
Simulation time 15110263 ps
CPU time 0.64 seconds
Started Apr 30 12:21:07 PM PDT 24
Finished Apr 30 12:21:08 PM PDT 24
Peak memory 193928 kb
Host smart-5d9d2223-f3cf-4ace-9ae4-0b1f2d2728ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895331251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.895331251
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1232958410
Short name T416
Test name
Test status
Simulation time 42527737 ps
CPU time 0.9 seconds
Started Apr 30 12:20:56 PM PDT 24
Finished Apr 30 12:20:57 PM PDT 24
Peak memory 196884 kb
Host smart-d1a4954b-867c-414e-96c9-5a15dc4941ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232958410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1232958410
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4187596980
Short name T107
Test name
Test status
Simulation time 461979085 ps
CPU time 4.13 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 195004 kb
Host smart-cfc7cfc1-865d-4bd3-bcd2-41ddda534bf9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187596980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4187596980
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3485256218
Short name T218
Test name
Test status
Simulation time 52066331 ps
CPU time 0.73 seconds
Started Apr 30 12:20:58 PM PDT 24
Finished Apr 30 12:20:59 PM PDT 24
Peak memory 194472 kb
Host smart-2109522c-663e-4dbb-93c0-27210fd92070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485256218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3485256218
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3114720327
Short name T266
Test name
Test status
Simulation time 30824836 ps
CPU time 0.77 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:15 PM PDT 24
Peak memory 194844 kb
Host smart-4adcfd09-3dcd-41ef-b459-6eff56f3d129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114720327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3114720327
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1799705395
Short name T573
Test name
Test status
Simulation time 82651813 ps
CPU time 3 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 196360 kb
Host smart-c3f4bc9b-4429-4e30-92e5-25f8bc743454
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799705395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1799705395
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2399554409
Short name T653
Test name
Test status
Simulation time 123852509 ps
CPU time 3.43 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 194372 kb
Host smart-412b0631-56ee-43ab-9763-d9a485dbfdb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399554409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2399554409
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1080499552
Short name T199
Test name
Test status
Simulation time 50475548 ps
CPU time 1.18 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 195872 kb
Host smart-30456514-0935-4b5a-94ce-55bd0b178714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080499552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1080499552
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.658769209
Short name T534
Test name
Test status
Simulation time 75145671 ps
CPU time 1.02 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 195216 kb
Host smart-c7409559-8f4c-4b16-896e-fd266966038a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658769209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.658769209
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2018432362
Short name T216
Test name
Test status
Simulation time 177521120 ps
CPU time 2.99 seconds
Started Apr 30 12:21:02 PM PDT 24
Finished Apr 30 12:21:05 PM PDT 24
Peak memory 197880 kb
Host smart-b797bbf7-7fa6-40f3-b0c8-b301ea81a5e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018432362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2018432362
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2086530328
Short name T361
Test name
Test status
Simulation time 136827338 ps
CPU time 0.92 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:15 PM PDT 24
Peak memory 194928 kb
Host smart-d102675d-817e-43b8-8add-f62558d38503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086530328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2086530328
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.761187324
Short name T168
Test name
Test status
Simulation time 308869489 ps
CPU time 1.39 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 196400 kb
Host smart-ea43aaa0-b062-4745-b316-e3d9d169cd41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761187324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.761187324
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.334178234
Short name T627
Test name
Test status
Simulation time 7948515778 ps
CPU time 169.06 seconds
Started Apr 30 12:23:02 PM PDT 24
Finished Apr 30 12:25:53 PM PDT 24
Peak memory 198024 kb
Host smart-a4429183-2914-4a96-8d63-ef756715673c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334178234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.334178234
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2670718579
Short name T65
Test name
Test status
Simulation time 52099464642 ps
CPU time 1394.45 seconds
Started Apr 30 12:21:14 PM PDT 24
Finished Apr 30 12:44:29 PM PDT 24
Peak memory 198176 kb
Host smart-5cf6cb6a-debb-4170-8ff3-8048bc4169bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2670718579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2670718579
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1477476707
Short name T454
Test name
Test status
Simulation time 13333309 ps
CPU time 0.6 seconds
Started Apr 30 12:21:21 PM PDT 24
Finished Apr 30 12:21:22 PM PDT 24
Peak memory 193928 kb
Host smart-7f9d0e58-6f77-4b73-ad88-637d14b50c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477476707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1477476707
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2676415285
Short name T638
Test name
Test status
Simulation time 128105419 ps
CPU time 0.92 seconds
Started Apr 30 12:21:13 PM PDT 24
Finished Apr 30 12:21:14 PM PDT 24
Peak memory 196304 kb
Host smart-e7fdcdbb-8712-47ee-ab30-3d1a31aa1a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676415285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2676415285
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3249654992
Short name T451
Test name
Test status
Simulation time 460550043 ps
CPU time 12.71 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 196880 kb
Host smart-87598b2a-d574-4707-a313-b9d5cc53be40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249654992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3249654992
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3259732617
Short name T116
Test name
Test status
Simulation time 81088028 ps
CPU time 0.68 seconds
Started Apr 30 12:21:19 PM PDT 24
Finished Apr 30 12:21:20 PM PDT 24
Peak memory 195244 kb
Host smart-92470c22-5dd6-4af6-ab70-fc050ceaa1f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259732617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3259732617
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2724361675
Short name T310
Test name
Test status
Simulation time 61902593 ps
CPU time 1.16 seconds
Started Apr 30 12:21:14 PM PDT 24
Finished Apr 30 12:21:16 PM PDT 24
Peak memory 195828 kb
Host smart-0e01f8c4-4a92-4eea-aa9d-f91d0afea1d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724361675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2724361675
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4136414316
Short name T306
Test name
Test status
Simulation time 643677123 ps
CPU time 3.75 seconds
Started Apr 30 12:22:36 PM PDT 24
Finished Apr 30 12:22:41 PM PDT 24
Peak memory 197952 kb
Host smart-44c37d41-8547-4715-a6fc-02df1b2cc8c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136414316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4136414316
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3308364968
Short name T173
Test name
Test status
Simulation time 83715326 ps
CPU time 1.49 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 195992 kb
Host smart-8de0d5bd-8018-4f24-b9a6-bc52af85def8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308364968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3308364968
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2701466301
Short name T308
Test name
Test status
Simulation time 167993305 ps
CPU time 0.79 seconds
Started Apr 30 12:21:14 PM PDT 24
Finished Apr 30 12:21:16 PM PDT 24
Peak memory 195400 kb
Host smart-4ff70a56-a1d1-49bd-8240-470a1d849f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701466301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2701466301
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3397951365
Short name T23
Test name
Test status
Simulation time 267436668 ps
CPU time 1.43 seconds
Started Apr 30 12:21:09 PM PDT 24
Finished Apr 30 12:21:11 PM PDT 24
Peak memory 198048 kb
Host smart-b09c1fc3-3980-4701-a7fa-af5283360448
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397951365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3397951365
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3308226712
Short name T15
Test name
Test status
Simulation time 362720588 ps
CPU time 4.16 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:43 PM PDT 24
Peak memory 197832 kb
Host smart-75745934-a81e-432b-9b33-87827aab33e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308226712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3308226712
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1666350234
Short name T689
Test name
Test status
Simulation time 331999192 ps
CPU time 1.28 seconds
Started Apr 30 12:21:08 PM PDT 24
Finished Apr 30 12:21:10 PM PDT 24
Peak memory 196796 kb
Host smart-832862d8-b6cc-475f-9d9f-c46df8bc5de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666350234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1666350234
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.89882019
Short name T74
Test name
Test status
Simulation time 149369379 ps
CPU time 0.94 seconds
Started Apr 30 12:21:09 PM PDT 24
Finished Apr 30 12:21:10 PM PDT 24
Peak memory 195604 kb
Host smart-24e7453f-ca98-4fcd-91b7-13cdf07475eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89882019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.89882019
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3576546857
Short name T494
Test name
Test status
Simulation time 6231281675 ps
CPU time 79.89 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:24:12 PM PDT 24
Peak memory 197984 kb
Host smart-b4e7ca08-8caa-4e05-aa39-7f5e81cc3af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576546857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3576546857
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1091043846
Short name T565
Test name
Test status
Simulation time 21556145910 ps
CPU time 346.43 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:28:32 PM PDT 24
Peak memory 197324 kb
Host smart-8d6d4e79-fd88-4ff3-956c-80b5e65693e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1091043846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1091043846
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1052210799
Short name T474
Test name
Test status
Simulation time 12857400 ps
CPU time 0.6 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:02 PM PDT 24
Peak memory 193752 kb
Host smart-743c9895-9210-401b-b437-d43cae4eda9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052210799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1052210799
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3011369848
Short name T390
Test name
Test status
Simulation time 54269114 ps
CPU time 0.77 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 195772 kb
Host smart-f9e440f5-2034-4c0b-9015-f3139d886c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011369848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3011369848
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3225232590
Short name T359
Test name
Test status
Simulation time 770442515 ps
CPU time 10.58 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:12 PM PDT 24
Peak memory 196748 kb
Host smart-53e17907-d17e-410b-8be5-73828ea1bf39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225232590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3225232590
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3711206201
Short name T117
Test name
Test status
Simulation time 95443341 ps
CPU time 0.78 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 195712 kb
Host smart-b1e43fad-59d7-4860-bdc7-5542dd537b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711206201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3711206201
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3445979250
Short name T299
Test name
Test status
Simulation time 27929199 ps
CPU time 0.69 seconds
Started Apr 30 12:22:44 PM PDT 24
Finished Apr 30 12:22:45 PM PDT 24
Peak memory 192932 kb
Host smart-b259662a-de26-4ba7-b6dd-416c7b407e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445979250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3445979250
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1102207353
Short name T517
Test name
Test status
Simulation time 74657377 ps
CPU time 1.15 seconds
Started Apr 30 12:21:23 PM PDT 24
Finished Apr 30 12:21:25 PM PDT 24
Peak memory 196404 kb
Host smart-9fe3a983-dc14-4b45-ba7f-7ac683d314a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102207353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1102207353
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1991137800
Short name T259
Test name
Test status
Simulation time 268096203 ps
CPU time 2.98 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 196324 kb
Host smart-946d483d-2bde-4ec9-93cb-64fe7adf258a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991137800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1991137800
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1254061204
Short name T536
Test name
Test status
Simulation time 265495589 ps
CPU time 1.01 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 195720 kb
Host smart-61889f77-06a1-48ff-8073-fc722c7c3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254061204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1254061204
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4235410182
Short name T201
Test name
Test status
Simulation time 159081407 ps
CPU time 0.8 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 195684 kb
Host smart-2b67069d-4eeb-44ea-974b-1c24fb8bacc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235410182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4235410182
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3678102111
Short name T330
Test name
Test status
Simulation time 208445270 ps
CPU time 3.38 seconds
Started Apr 30 12:22:44 PM PDT 24
Finished Apr 30 12:22:48 PM PDT 24
Peak memory 196432 kb
Host smart-6ab2a83b-406e-4d52-af89-6e01512a86a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678102111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3678102111
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2745630474
Short name T296
Test name
Test status
Simulation time 108317447 ps
CPU time 1.36 seconds
Started Apr 30 12:23:42 PM PDT 24
Finished Apr 30 12:23:44 PM PDT 24
Peak memory 196584 kb
Host smart-da341a26-9a2a-404b-ae47-02e2fd5d8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745630474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2745630474
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2787035942
Short name T440
Test name
Test status
Simulation time 73443547 ps
CPU time 1.1 seconds
Started Apr 30 12:23:40 PM PDT 24
Finished Apr 30 12:23:42 PM PDT 24
Peak memory 195368 kb
Host smart-3f2c8a84-702c-408d-be42-aaca629e4027
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787035942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2787035942
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3201491553
Short name T532
Test name
Test status
Simulation time 3888499942 ps
CPU time 37.46 seconds
Started Apr 30 12:21:27 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 198416 kb
Host smart-453b5d79-79d1-409d-b7b7-16ab295fff38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201491553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3201491553
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3268101829
Short name T163
Test name
Test status
Simulation time 24112787 ps
CPU time 0.63 seconds
Started Apr 30 12:21:39 PM PDT 24
Finished Apr 30 12:21:40 PM PDT 24
Peak memory 193952 kb
Host smart-30b4332e-8076-4777-9ccd-1ad8183217f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268101829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3268101829
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4142342550
Short name T418
Test name
Test status
Simulation time 15649965 ps
CPU time 0.66 seconds
Started Apr 30 12:21:30 PM PDT 24
Finished Apr 30 12:21:31 PM PDT 24
Peak memory 194000 kb
Host smart-c30ec286-761f-426d-b902-280d078cd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142342550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4142342550
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2600976034
Short name T297
Test name
Test status
Simulation time 739963760 ps
CPU time 25.37 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 197760 kb
Host smart-193851bf-3bf1-4dca-ad31-40e567b7b168
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600976034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2600976034
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1193902390
Short name T571
Test name
Test status
Simulation time 801568425 ps
CPU time 1.02 seconds
Started Apr 30 12:21:38 PM PDT 24
Finished Apr 30 12:21:40 PM PDT 24
Peak memory 196608 kb
Host smart-5eaa0f99-e3cf-4818-840a-7db81ab3b451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193902390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1193902390
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2649578230
Short name T220
Test name
Test status
Simulation time 149770830 ps
CPU time 0.79 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 195256 kb
Host smart-6d4ec09b-3f17-4024-ac4c-e576d5afb978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649578230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2649578230
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1747873115
Short name T339
Test name
Test status
Simulation time 45515152 ps
CPU time 1.01 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 195892 kb
Host smart-d3198595-eb36-4589-bc04-b1aa5a7e8763
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747873115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1747873115
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3888464074
Short name T152
Test name
Test status
Simulation time 354110514 ps
CPU time 1.09 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 196468 kb
Host smart-e009ab11-1bbd-496c-9990-2115caaa3fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888464074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3888464074
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1318293355
Short name T120
Test name
Test status
Simulation time 95739974 ps
CPU time 1.1 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 196836 kb
Host smart-616930a0-85be-4708-8277-2d83e6a9c7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318293355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1318293355
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3598161712
Short name T150
Test name
Test status
Simulation time 34863617 ps
CPU time 0.87 seconds
Started Apr 30 12:21:31 PM PDT 24
Finished Apr 30 12:21:32 PM PDT 24
Peak memory 196016 kb
Host smart-10bd4edf-4d53-406d-bda2-4b2591645af6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598161712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3598161712
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4158531603
Short name T283
Test name
Test status
Simulation time 70250478 ps
CPU time 2.91 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 197572 kb
Host smart-7b6caeda-9b03-4646-a8cf-29540426fdd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158531603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4158531603
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1061823895
Short name T612
Test name
Test status
Simulation time 92455606 ps
CPU time 1.37 seconds
Started Apr 30 12:22:42 PM PDT 24
Finished Apr 30 12:22:44 PM PDT 24
Peak memory 194732 kb
Host smart-e035ada6-a2db-4f14-9a0d-841b88821eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061823895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1061823895
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1335264044
Short name T131
Test name
Test status
Simulation time 86707267 ps
CPU time 0.89 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195248 kb
Host smart-5c06b0c1-b678-4467-ac66-9001de189476
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335264044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1335264044
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4043610571
Short name T651
Test name
Test status
Simulation time 6945319600 ps
CPU time 43.06 seconds
Started Apr 30 12:23:53 PM PDT 24
Finished Apr 30 12:24:38 PM PDT 24
Peak memory 196600 kb
Host smart-cd10f38d-7ea8-4a8e-b76b-3ddc8339f74d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043610571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4043610571
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4013507897
Short name T667
Test name
Test status
Simulation time 82922345 ps
CPU time 0.56 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 193584 kb
Host smart-6deaae25-357e-49a3-9075-23bf0ceffe53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013507897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4013507897
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1295809530
Short name T596
Test name
Test status
Simulation time 84829184 ps
CPU time 0.7 seconds
Started Apr 30 12:17:11 PM PDT 24
Finished Apr 30 12:17:12 PM PDT 24
Peak memory 194036 kb
Host smart-ee583ae2-dea6-41b6-9d5e-005748958992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295809530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1295809530
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.425142270
Short name T481
Test name
Test status
Simulation time 5364256289 ps
CPU time 18.53 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:23:05 PM PDT 24
Peak memory 196096 kb
Host smart-abb6164b-77f6-4e74-91b9-f3f71b0ab0b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425142270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.425142270
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1425043249
Short name T444
Test name
Test status
Simulation time 236915145 ps
CPU time 0.98 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 196172 kb
Host smart-3fedd745-970b-427f-b404-f9e5312648ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425043249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1425043249
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2090421445
Short name T358
Test name
Test status
Simulation time 155394333 ps
CPU time 1.36 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 196628 kb
Host smart-949b538c-3ad5-445e-b28d-a23edf9ef998
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090421445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2090421445
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3890968561
Short name T105
Test name
Test status
Simulation time 63982019 ps
CPU time 2.45 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 197764 kb
Host smart-af0b2715-2f4e-4605-9205-f376be5b1792
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890968561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3890968561
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.279603086
Short name T263
Test name
Test status
Simulation time 53553661 ps
CPU time 1.58 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 193876 kb
Host smart-b05be57c-b17e-4ae1-9c81-316da9f1e1dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279603086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.279603086
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1540191705
Short name T73
Test name
Test status
Simulation time 53571631 ps
CPU time 0.67 seconds
Started Apr 30 12:17:05 PM PDT 24
Finished Apr 30 12:17:06 PM PDT 24
Peak memory 194756 kb
Host smart-824fcbbc-6a90-47eb-ae10-043b554d5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540191705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1540191705
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1533773521
Short name T245
Test name
Test status
Simulation time 64520194 ps
CPU time 0.83 seconds
Started Apr 30 12:17:07 PM PDT 24
Finished Apr 30 12:17:08 PM PDT 24
Peak memory 196012 kb
Host smart-f547b2cc-1101-4083-8c9d-e50345c38ccb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533773521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1533773521
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3195178098
Short name T20
Test name
Test status
Simulation time 1063853805 ps
CPU time 3.56 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:22:11 PM PDT 24
Peak memory 197520 kb
Host smart-4f5e7acf-5c11-4676-9b7d-467b7d996dd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195178098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3195178098
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.598755554
Short name T39
Test name
Test status
Simulation time 184717015 ps
CPU time 0.88 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 213256 kb
Host smart-f2cc7428-82e4-4093-877a-912c7f0f3b85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598755554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.598755554
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2024099524
Short name T438
Test name
Test status
Simulation time 300308823 ps
CPU time 1.29 seconds
Started Apr 30 12:18:27 PM PDT 24
Finished Apr 30 12:18:29 PM PDT 24
Peak memory 197916 kb
Host smart-0f9ddeb2-8541-45fe-832e-f73cef5b8bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024099524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2024099524
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.399936886
Short name T453
Test name
Test status
Simulation time 52979365 ps
CPU time 0.97 seconds
Started Apr 30 12:20:57 PM PDT 24
Finished Apr 30 12:20:59 PM PDT 24
Peak memory 195412 kb
Host smart-d1dfd2c9-018c-464d-998b-dc3a5e56f641
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399936886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.399936886
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3285022322
Short name T16
Test name
Test status
Simulation time 12558343553 ps
CPU time 175.59 seconds
Started Apr 30 12:21:48 PM PDT 24
Finished Apr 30 12:24:44 PM PDT 24
Peak memory 198028 kb
Host smart-e2517942-75db-41f9-9b61-5fff7e063044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285022322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3285022322
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.256893802
Short name T64
Test name
Test status
Simulation time 358861274214 ps
CPU time 498.62 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:29:03 PM PDT 24
Peak memory 206316 kb
Host smart-ec4e4071-603e-49f6-a1e0-3da432552137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=256893802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.256893802
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1676666912
Short name T407
Test name
Test status
Simulation time 17143813 ps
CPU time 0.57 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:56 PM PDT 24
Peak memory 193796 kb
Host smart-6bad91e4-f35d-4c6f-8245-2601f5c374c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676666912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1676666912
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3080963372
Short name T554
Test name
Test status
Simulation time 30825299 ps
CPU time 0.94 seconds
Started Apr 30 12:21:49 PM PDT 24
Finished Apr 30 12:21:50 PM PDT 24
Peak memory 196652 kb
Host smart-8c2bf7ad-b048-4d8e-bf9d-44846eb112fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080963372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3080963372
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4208728156
Short name T234
Test name
Test status
Simulation time 858838434 ps
CPU time 4.02 seconds
Started Apr 30 12:21:50 PM PDT 24
Finished Apr 30 12:21:55 PM PDT 24
Peak memory 196100 kb
Host smart-db4e2611-9ab2-4cb3-bdbd-77e9e12fdbd8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208728156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4208728156
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.401254459
Short name T695
Test name
Test status
Simulation time 46530838 ps
CPU time 0.91 seconds
Started Apr 30 12:21:48 PM PDT 24
Finished Apr 30 12:21:50 PM PDT 24
Peak memory 195952 kb
Host smart-516ee922-ea28-4716-ac3e-de696c7d8a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401254459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.401254459
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2673737961
Short name T388
Test name
Test status
Simulation time 295085993 ps
CPU time 1.11 seconds
Started Apr 30 12:21:45 PM PDT 24
Finished Apr 30 12:21:46 PM PDT 24
Peak memory 195852 kb
Host smart-dd6518b5-39d8-4a17-a337-d694fc7a9246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673737961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2673737961
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1765013654
Short name T610
Test name
Test status
Simulation time 334436362 ps
CPU time 2.81 seconds
Started Apr 30 12:21:51 PM PDT 24
Finished Apr 30 12:21:54 PM PDT 24
Peak memory 197900 kb
Host smart-0deb2797-e394-4722-87f1-e76c6c9196ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765013654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1765013654
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.577138885
Short name T495
Test name
Test status
Simulation time 686351892 ps
CPU time 3.75 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:58 PM PDT 24
Peak memory 196996 kb
Host smart-e4331e53-bd41-481d-bfa3-68947041fccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577138885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
577138885
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1552232014
Short name T196
Test name
Test status
Simulation time 218046569 ps
CPU time 1.3 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 197204 kb
Host smart-3e12639a-2a2a-4b6d-86b7-44255106561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552232014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1552232014
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2443462676
Short name T179
Test name
Test status
Simulation time 16659794 ps
CPU time 0.69 seconds
Started Apr 30 12:21:46 PM PDT 24
Finished Apr 30 12:21:48 PM PDT 24
Peak memory 194236 kb
Host smart-aba97435-7a1e-440d-905e-676a61b782be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443462676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2443462676
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3175872523
Short name T547
Test name
Test status
Simulation time 145924116 ps
CPU time 3.3 seconds
Started Apr 30 12:21:53 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 198188 kb
Host smart-78ef4263-f385-477d-b551-aecfda725075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175872523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3175872523
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4272070912
Short name T386
Test name
Test status
Simulation time 136900028 ps
CPU time 1.24 seconds
Started Apr 30 12:21:44 PM PDT 24
Finished Apr 30 12:21:45 PM PDT 24
Peak memory 197916 kb
Host smart-4f5b7aa9-b7ae-48d3-85b2-a3a775d6761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272070912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4272070912
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2191517690
Short name T414
Test name
Test status
Simulation time 260955081 ps
CPU time 1.07 seconds
Started Apr 30 12:21:44 PM PDT 24
Finished Apr 30 12:21:46 PM PDT 24
Peak memory 195540 kb
Host smart-b607f3f0-d708-4ffb-9a0a-97a275452792
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191517690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2191517690
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3772577183
Short name T521
Test name
Test status
Simulation time 113047823269 ps
CPU time 230.98 seconds
Started Apr 30 12:21:47 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 198028 kb
Host smart-62c86a0c-88fb-4628-8476-f0d87130eed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772577183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3772577183
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.441063822
Short name T333
Test name
Test status
Simulation time 13099990 ps
CPU time 0.57 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 193752 kb
Host smart-d79d99ea-617d-4be7-b840-6c0dcbb42eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441063822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.441063822
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4286658799
Short name T515
Test name
Test status
Simulation time 28541817 ps
CPU time 0.68 seconds
Started Apr 30 12:22:25 PM PDT 24
Finished Apr 30 12:22:26 PM PDT 24
Peak memory 195020 kb
Host smart-f51431b8-c428-4bb6-968c-2c5d6d63291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286658799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4286658799
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3795495459
Short name T128
Test name
Test status
Simulation time 5281297468 ps
CPU time 11.75 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 196700 kb
Host smart-fb6cc80a-6b47-4703-9a41-8649726458ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795495459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3795495459
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2407027121
Short name T439
Test name
Test status
Simulation time 37187126 ps
CPU time 0.74 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195588 kb
Host smart-7a826a2d-f943-4239-ab36-7d359815c930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407027121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2407027121
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.483928828
Short name T643
Test name
Test status
Simulation time 66352984 ps
CPU time 0.8 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:06 PM PDT 24
Peak memory 195596 kb
Host smart-ad72e710-9231-49c9-8421-da7924f32013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483928828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.483928828
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2373047572
Short name T274
Test name
Test status
Simulation time 264842878 ps
CPU time 2.67 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 197848 kb
Host smart-014c3096-399f-4090-b97d-ede2446fe985
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373047572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2373047572
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2906991681
Short name T510
Test name
Test status
Simulation time 47662626 ps
CPU time 0.9 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:22:01 PM PDT 24
Peak memory 195080 kb
Host smart-3e26668a-2637-486a-a1eb-92430a3bc5a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906991681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2906991681
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2347081849
Short name T633
Test name
Test status
Simulation time 105131449 ps
CPU time 0.9 seconds
Started Apr 30 12:21:55 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 195748 kb
Host smart-5203b5ba-b245-4643-b826-8608974293fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347081849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2347081849
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.484498123
Short name T318
Test name
Test status
Simulation time 217354571 ps
CPU time 1.17 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:22:00 PM PDT 24
Peak memory 196812 kb
Host smart-9a29802f-58c3-41f0-839e-43785e01bd73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484498123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.484498123
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4212671595
Short name T129
Test name
Test status
Simulation time 429916002 ps
CPU time 2.05 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 197776 kb
Host smart-da85f8cd-447e-46dc-9c3a-2fcd31792394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212671595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4212671595
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3546782630
Short name T566
Test name
Test status
Simulation time 53769667 ps
CPU time 0.8 seconds
Started Apr 30 12:22:51 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 195112 kb
Host smart-1f076dd3-36bc-4048-92bf-4e92eee538c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546782630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3546782630
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2224031858
Short name T135
Test name
Test status
Simulation time 66436685 ps
CPU time 1.23 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 194496 kb
Host smart-34a0e0fe-b649-4d5f-bf48-dda923a0ce66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224031858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2224031858
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3591314112
Short name T715
Test name
Test status
Simulation time 33705043570 ps
CPU time 103.6 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:24:49 PM PDT 24
Peak memory 197900 kb
Host smart-eed6b8ab-16b8-4eb2-9add-e17275f1dcf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591314112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3591314112
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3455062608
Short name T63
Test name
Test status
Simulation time 220602928336 ps
CPU time 1242.39 seconds
Started Apr 30 12:22:08 PM PDT 24
Finished Apr 30 12:42:51 PM PDT 24
Peak memory 198104 kb
Host smart-711c1fa6-1987-41ad-8416-331c7518dfe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3455062608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3455062608
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3811778142
Short name T360
Test name
Test status
Simulation time 51283566 ps
CPU time 0.55 seconds
Started Apr 30 12:23:40 PM PDT 24
Finished Apr 30 12:23:41 PM PDT 24
Peak memory 193612 kb
Host smart-e086d6ce-23b0-4df3-ace4-336621a2d585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811778142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3811778142
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1853435987
Short name T540
Test name
Test status
Simulation time 40808040 ps
CPU time 0.94 seconds
Started Apr 30 12:22:10 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 197200 kb
Host smart-8cca21e2-7dbf-4cc5-97f1-879486a82793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853435987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1853435987
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1740591223
Short name T680
Test name
Test status
Simulation time 166784373 ps
CPU time 7.25 seconds
Started Apr 30 12:23:51 PM PDT 24
Finished Apr 30 12:24:00 PM PDT 24
Peak memory 196984 kb
Host smart-f1f1fdf3-82b8-4a3a-ba57-d8a5a42fe1ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740591223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1740591223
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3146284909
Short name T5
Test name
Test status
Simulation time 1156960366 ps
CPU time 1.07 seconds
Started Apr 30 12:22:23 PM PDT 24
Finished Apr 30 12:22:24 PM PDT 24
Peak memory 196544 kb
Host smart-7f61aff7-e863-4a5c-b933-314e227cd424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146284909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3146284909
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.875076128
Short name T204
Test name
Test status
Simulation time 46084342 ps
CPU time 0.71 seconds
Started Apr 30 12:23:42 PM PDT 24
Finished Apr 30 12:23:43 PM PDT 24
Peak memory 195296 kb
Host smart-a983ccc1-f08e-4cc2-aaf2-4a7e739fc6b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875076128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.875076128
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.726898285
Short name T529
Test name
Test status
Simulation time 487997959 ps
CPU time 2.02 seconds
Started Apr 30 12:22:09 PM PDT 24
Finished Apr 30 12:22:12 PM PDT 24
Peak memory 197968 kb
Host smart-6f8d69b6-7dce-459f-8332-5eb9bedbd1ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726898285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.726898285
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.671638662
Short name T586
Test name
Test status
Simulation time 354822229 ps
CPU time 2.06 seconds
Started Apr 30 12:23:50 PM PDT 24
Finished Apr 30 12:23:53 PM PDT 24
Peak memory 197020 kb
Host smart-d367e7c6-3821-45a5-a7b3-ee8ab8f131b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671638662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
671638662
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3476920108
Short name T519
Test name
Test status
Simulation time 58112704 ps
CPU time 0.72 seconds
Started Apr 30 12:22:42 PM PDT 24
Finished Apr 30 12:22:44 PM PDT 24
Peak memory 195972 kb
Host smart-a2f1aeb5-6adf-4922-96a3-d8c95450917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476920108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3476920108
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.881718899
Short name T464
Test name
Test status
Simulation time 39031054 ps
CPU time 0.86 seconds
Started Apr 30 12:22:16 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 196508 kb
Host smart-1489f179-0908-4109-b968-f14c5db4bf04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881718899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.881718899
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1357487212
Short name T364
Test name
Test status
Simulation time 404026936 ps
CPU time 3.34 seconds
Started Apr 30 12:23:46 PM PDT 24
Finished Apr 30 12:23:50 PM PDT 24
Peak memory 197888 kb
Host smart-01f91aa7-2e23-48a6-a4a4-20daad7f6da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357487212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1357487212
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.401281437
Short name T584
Test name
Test status
Simulation time 37891312 ps
CPU time 0.76 seconds
Started Apr 30 12:22:09 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 195824 kb
Host smart-75fcb702-7c59-429c-a117-ac24489b7dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401281437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.401281437
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4107554881
Short name T478
Test name
Test status
Simulation time 29488664 ps
CPU time 0.79 seconds
Started Apr 30 12:23:42 PM PDT 24
Finished Apr 30 12:23:43 PM PDT 24
Peak memory 195832 kb
Host smart-d413fb21-c873-4ba6-9b2c-1d9ad56bc86f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107554881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4107554881
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2979570816
Short name T557
Test name
Test status
Simulation time 14803453461 ps
CPU time 97.38 seconds
Started Apr 30 12:23:29 PM PDT 24
Finished Apr 30 12:25:07 PM PDT 24
Peak memory 197320 kb
Host smart-8e9296f8-5b90-4f63-90a8-59c5b6774ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979570816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2979570816
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1086549863
Short name T305
Test name
Test status
Simulation time 43739596 ps
CPU time 0.62 seconds
Started Apr 30 12:22:29 PM PDT 24
Finished Apr 30 12:22:30 PM PDT 24
Peak memory 193916 kb
Host smart-603652bb-813b-4314-a4fb-982cd9f4a06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086549863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1086549863
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4156423505
Short name T640
Test name
Test status
Simulation time 132920755 ps
CPU time 0.86 seconds
Started Apr 30 12:22:35 PM PDT 24
Finished Apr 30 12:22:36 PM PDT 24
Peak memory 196088 kb
Host smart-c79ed6bd-c5b3-4fd9-81a8-6416abf72bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156423505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4156423505
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1412332618
Short name T576
Test name
Test status
Simulation time 3434774226 ps
CPU time 26.79 seconds
Started Apr 30 12:22:33 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 196876 kb
Host smart-01c93b12-e4fd-4c68-a570-29bf969b7d0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412332618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1412332618
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3885623263
Short name T170
Test name
Test status
Simulation time 193556446 ps
CPU time 0.68 seconds
Started Apr 30 12:23:47 PM PDT 24
Finished Apr 30 12:23:49 PM PDT 24
Peak memory 193404 kb
Host smart-e0b66d70-f83f-421a-bb9f-1e34871a8dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885623263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3885623263
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.597417722
Short name T367
Test name
Test status
Simulation time 103623603 ps
CPU time 0.89 seconds
Started Apr 30 12:22:34 PM PDT 24
Finished Apr 30 12:22:36 PM PDT 24
Peak memory 197360 kb
Host smart-661460ac-eec2-4f98-9994-bc1c49909345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597417722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.597417722
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3780796691
Short name T387
Test name
Test status
Simulation time 118823150 ps
CPU time 1.41 seconds
Started Apr 30 12:22:34 PM PDT 24
Finished Apr 30 12:22:36 PM PDT 24
Peak memory 196316 kb
Host smart-a18fbcb0-01f3-4c56-87ed-39d5c9117228
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780796691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3780796691
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3058681897
Short name T617
Test name
Test status
Simulation time 699025382 ps
CPU time 2.93 seconds
Started Apr 30 12:22:34 PM PDT 24
Finished Apr 30 12:22:38 PM PDT 24
Peak memory 196864 kb
Host smart-ce1e0cc6-2c93-4541-ac57-506c02540804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058681897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3058681897
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1089993243
Short name T304
Test name
Test status
Simulation time 19565490 ps
CPU time 0.66 seconds
Started Apr 30 12:22:36 PM PDT 24
Finished Apr 30 12:22:38 PM PDT 24
Peak memory 194616 kb
Host smart-804dfad6-4183-4e0d-94d6-63a972355160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089993243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1089993243
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2619795977
Short name T509
Test name
Test status
Simulation time 55195511 ps
CPU time 1.05 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 196816 kb
Host smart-ab3caf29-30cc-4af1-ba6b-d7c0cd050e17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619795977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2619795977
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1822369085
Short name T412
Test name
Test status
Simulation time 123958538 ps
CPU time 1.67 seconds
Started Apr 30 12:22:42 PM PDT 24
Finished Apr 30 12:22:45 PM PDT 24
Peak memory 197716 kb
Host smart-e2ce5e57-21c9-449b-8bb3-f338b49425e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822369085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1822369085
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3050593111
Short name T574
Test name
Test status
Simulation time 567012962 ps
CPU time 1.43 seconds
Started Apr 30 12:22:22 PM PDT 24
Finished Apr 30 12:22:24 PM PDT 24
Peak memory 196152 kb
Host smart-409edf78-6a00-49c3-8969-813dbac3d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050593111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3050593111
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4121438374
Short name T17
Test name
Test status
Simulation time 204645727 ps
CPU time 1.05 seconds
Started Apr 30 12:23:52 PM PDT 24
Finished Apr 30 12:23:54 PM PDT 24
Peak memory 195596 kb
Host smart-f419bbda-1229-4678-b7dc-0d9cc7f469c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121438374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4121438374
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2543513589
Short name T713
Test name
Test status
Simulation time 21475625488 ps
CPU time 134.82 seconds
Started Apr 30 12:22:34 PM PDT 24
Finished Apr 30 12:24:49 PM PDT 24
Peak memory 198008 kb
Host smart-5df8ecc7-ecf0-4a8d-ab26-76e703724343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543513589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2543513589
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.929100753
Short name T552
Test name
Test status
Simulation time 334095447502 ps
CPU time 1800.89 seconds
Started Apr 30 12:22:42 PM PDT 24
Finished Apr 30 12:52:44 PM PDT 24
Peak memory 198120 kb
Host smart-50980df1-383c-49ef-8213-3ab22ed2a2b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=929100753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.929100753
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1728246891
Short name T712
Test name
Test status
Simulation time 46192173 ps
CPU time 0.62 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 193788 kb
Host smart-59f97867-7328-4d97-b4f9-3ede41687810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728246891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1728246891
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2032161401
Short name T158
Test name
Test status
Simulation time 44296507 ps
CPU time 0.78 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 195232 kb
Host smart-05d96f6e-3e17-49c8-94fe-67fb3d21cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032161401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2032161401
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3020556962
Short name T410
Test name
Test status
Simulation time 1516068132 ps
CPU time 19.22 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:24 PM PDT 24
Peak memory 197912 kb
Host smart-afed4c39-0f4f-42cc-b633-f442be367e27
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020556962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3020556962
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3198027120
Short name T313
Test name
Test status
Simulation time 58697415 ps
CPU time 0.61 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 194616 kb
Host smart-40a93aa9-83b8-4100-bc68-b9bf8502cdff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198027120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3198027120
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2666750322
Short name T570
Test name
Test status
Simulation time 41975973 ps
CPU time 0.88 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:05 PM PDT 24
Peak memory 197324 kb
Host smart-df822021-7a9d-4ed6-b89f-e494e25351a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666750322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2666750322
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4271146169
Short name T563
Test name
Test status
Simulation time 70146417 ps
CPU time 2.64 seconds
Started Apr 30 12:22:40 PM PDT 24
Finished Apr 30 12:22:43 PM PDT 24
Peak memory 196320 kb
Host smart-f3ce044d-246b-4d86-87e4-15ca5c98c993
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271146169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4271146169
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2959558224
Short name T417
Test name
Test status
Simulation time 293594685 ps
CPU time 2.21 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:07 PM PDT 24
Peak memory 195652 kb
Host smart-15fe334c-07e4-4a34-817d-7fcbe80c0329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959558224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2959558224
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1821414857
Short name T294
Test name
Test status
Simulation time 65872997 ps
CPU time 1.1 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:06 PM PDT 24
Peak memory 195920 kb
Host smart-0dcae1da-3b83-40e9-a0be-86f34ac2860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821414857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1821414857
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.690676008
Short name T162
Test name
Test status
Simulation time 214639907 ps
CPU time 1.21 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 197008 kb
Host smart-d5bb2d18-4b46-4301-a0b7-fd015b567390
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690676008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.690676008
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2916064700
Short name T352
Test name
Test status
Simulation time 238202064 ps
CPU time 3.02 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:07 PM PDT 24
Peak memory 197752 kb
Host smart-a5ff2590-7dbe-44d0-ae6d-a1cd4f3867d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916064700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2916064700
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1282199850
Short name T707
Test name
Test status
Simulation time 42527934 ps
CPU time 0.93 seconds
Started Apr 30 12:22:29 PM PDT 24
Finished Apr 30 12:22:30 PM PDT 24
Peak memory 195456 kb
Host smart-a314bd74-586e-4bdd-abd9-2c89c5918bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282199850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1282199850
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4034410449
Short name T12
Test name
Test status
Simulation time 171542873 ps
CPU time 0.93 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 196428 kb
Host smart-b6aaca38-335c-428e-a43e-f9afd5dacffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034410449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4034410449
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2407145847
Short name T19
Test name
Test status
Simulation time 84006753209 ps
CPU time 228.69 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:26:27 PM PDT 24
Peak memory 198356 kb
Host smart-de5974a4-6646-4bed-b6fe-53b7e08b6abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407145847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2407145847
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3500503752
Short name T598
Test name
Test status
Simulation time 15773619 ps
CPU time 0.6 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 193840 kb
Host smart-cce8b9a9-94c2-4662-b5de-89527c3d2ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500503752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3500503752
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2356067358
Short name T425
Test name
Test status
Simulation time 13698995 ps
CPU time 0.6 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 193816 kb
Host smart-e78c82c0-4011-4512-8562-9d04dcabad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356067358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2356067358
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.225099214
Short name T372
Test name
Test status
Simulation time 468314936 ps
CPU time 12.83 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 195428 kb
Host smart-7270e379-d022-4db9-a7cd-e4cad9b5a000
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225099214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.225099214
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2823606783
Short name T642
Test name
Test status
Simulation time 33262473 ps
CPU time 0.65 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 194444 kb
Host smart-b0d64a67-de10-4633-a305-39c42ccf9332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823606783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2823606783
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.736532510
Short name T461
Test name
Test status
Simulation time 63288183 ps
CPU time 1.04 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:54 PM PDT 24
Peak memory 195692 kb
Host smart-109f2f09-9165-43ca-bac1-af6799450564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736532510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.736532510
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2058263919
Short name T203
Test name
Test status
Simulation time 170094868 ps
CPU time 3.43 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:41 PM PDT 24
Peak memory 198080 kb
Host smart-91e7c7ba-a580-4f5d-b66b-9f5b3a86e0f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058263919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2058263919
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3906683065
Short name T702
Test name
Test status
Simulation time 408268063 ps
CPU time 1.41 seconds
Started Apr 30 12:22:37 PM PDT 24
Finished Apr 30 12:22:39 PM PDT 24
Peak memory 196108 kb
Host smart-1fcd3521-f16d-42be-bece-88418712bcee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906683065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3906683065
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.248091832
Short name T504
Test name
Test status
Simulation time 122400694 ps
CPU time 1.22 seconds
Started Apr 30 12:22:38 PM PDT 24
Finished Apr 30 12:22:40 PM PDT 24
Peak memory 196368 kb
Host smart-0b066bc5-b6cd-4137-97fd-2fc35c960f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248091832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.248091832
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1404605284
Short name T307
Test name
Test status
Simulation time 18283457 ps
CPU time 0.68 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:06 PM PDT 24
Peak memory 194168 kb
Host smart-23b9fcaf-e8fe-4aaf-bb0e-97ac5802ae01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404605284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1404605284
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2027382409
Short name T378
Test name
Test status
Simulation time 383048682 ps
CPU time 2.91 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 197684 kb
Host smart-7dcbe6ef-f933-4f4d-8d3e-42841997769a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027382409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2027382409
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3018511286
Short name T11
Test name
Test status
Simulation time 156644620 ps
CPU time 0.99 seconds
Started Apr 30 12:23:47 PM PDT 24
Finished Apr 30 12:23:49 PM PDT 24
Peak memory 193928 kb
Host smart-a5b58209-9d1d-47b5-aaee-b41a26da60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018511286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3018511286
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1417804477
Short name T249
Test name
Test status
Simulation time 354410360 ps
CPU time 1.38 seconds
Started Apr 30 12:23:47 PM PDT 24
Finished Apr 30 12:23:50 PM PDT 24
Peak memory 194964 kb
Host smart-f6808554-7ac4-4075-a2ca-d94fd2dea041
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417804477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1417804477
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.701823316
Short name T432
Test name
Test status
Simulation time 13309224505 ps
CPU time 94.97 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:24:26 PM PDT 24
Peak memory 198060 kb
Host smart-451febe4-74a4-4d0d-bd27-046af5f9b49d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701823316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.701823316
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.179232961
Short name T312
Test name
Test status
Simulation time 25749310 ps
CPU time 0.57 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 194852 kb
Host smart-5a3ca2c4-4d8b-4da8-a260-ab3102f958ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179232961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.179232961
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3218645474
Short name T243
Test name
Test status
Simulation time 19654128 ps
CPU time 0.61 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:22:56 PM PDT 24
Peak memory 193896 kb
Host smart-85e3eac8-aa2c-470d-a205-542e14de4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218645474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3218645474
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3063074513
Short name T701
Test name
Test status
Simulation time 405693618 ps
CPU time 13.57 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:23:12 PM PDT 24
Peak memory 196816 kb
Host smart-0c9bad14-5879-459f-99c6-9de7fcce5d4f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063074513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3063074513
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.225299896
Short name T516
Test name
Test status
Simulation time 78319598 ps
CPU time 1 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:54 PM PDT 24
Peak memory 196412 kb
Host smart-ecbbea62-9b22-48c9-ac9e-c24f1aeb3409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225299896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.225299896
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.32001270
Short name T311
Test name
Test status
Simulation time 331538993 ps
CPU time 0.73 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195292 kb
Host smart-93be8ba0-5d00-4d0a-a9ae-183facb7c197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32001270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.32001270
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4263278480
Short name T524
Test name
Test status
Simulation time 344070099 ps
CPU time 3.59 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 197924 kb
Host smart-a3a58de5-55bf-4916-8427-ff49198079ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263278480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4263278480
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2353389366
Short name T593
Test name
Test status
Simulation time 195681652 ps
CPU time 1.17 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 195352 kb
Host smart-7202fa85-1ed7-4f61-af5f-70e9bed7cac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353389366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2353389366
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2899979188
Short name T665
Test name
Test status
Simulation time 59919443 ps
CPU time 1.31 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 197872 kb
Host smart-4f6e83df-20ec-40c3-8338-7603f3913423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899979188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2899979188
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2231094582
Short name T268
Test name
Test status
Simulation time 127195088 ps
CPU time 1.11 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 195652 kb
Host smart-5cc1bd16-f07d-486b-bc8d-ee06d42dda12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231094582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2231094582
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.517757547
Short name T661
Test name
Test status
Simulation time 2128051892 ps
CPU time 4.91 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:22:55 PM PDT 24
Peak memory 197904 kb
Host smart-c8035c04-2ce7-4ef6-a842-44cc801c4acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517757547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.517757547
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2377052435
Short name T507
Test name
Test status
Simulation time 169853081 ps
CPU time 0.97 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 195432 kb
Host smart-0b87f645-5bb9-415e-8ba6-ef7eb7cb6c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377052435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2377052435
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.139898635
Short name T236
Test name
Test status
Simulation time 162750392 ps
CPU time 0.89 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 196220 kb
Host smart-d68387a2-c443-4ce7-b20d-afcaa96a2357
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139898635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.139898635
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3707554667
Short name T380
Test name
Test status
Simulation time 22911792773 ps
CPU time 590.62 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 198156 kb
Host smart-ffe0e58f-971f-462b-8066-fb1dbbc5984e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3707554667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3707554667
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2264923848
Short name T281
Test name
Test status
Simulation time 38597736 ps
CPU time 0.57 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 193420 kb
Host smart-bd00a2fa-51f2-4a63-b1a3-1c49a023a1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264923848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2264923848
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2630071474
Short name T426
Test name
Test status
Simulation time 29924568 ps
CPU time 0.89 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 195640 kb
Host smart-c3351e6d-3712-48aa-b551-dd395a74a725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630071474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2630071474
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3940057580
Short name T244
Test name
Test status
Simulation time 2436679823 ps
CPU time 15.15 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 196248 kb
Host smart-c1188cc8-99e9-4bc8-9e9b-019ba9aba317
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940057580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3940057580
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.754668324
Short name T502
Test name
Test status
Simulation time 32433625 ps
CPU time 0.68 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 194668 kb
Host smart-658be8e1-6911-4113-88c2-f10cc6e30997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754668324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.754668324
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.4275204551
Short name T180
Test name
Test status
Simulation time 71562098 ps
CPU time 0.77 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 195476 kb
Host smart-d1643ffa-c79f-485b-97ca-f31686874383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275204551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.4275204551
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2668014903
Short name T631
Test name
Test status
Simulation time 266735515 ps
CPU time 3.08 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 196200 kb
Host smart-a0c6aa1f-ee63-46b0-8867-c0479f803fe0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668014903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2668014903
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.291554103
Short name T69
Test name
Test status
Simulation time 220910344 ps
CPU time 2.13 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 196644 kb
Host smart-26690bd0-b030-4afa-84b4-18879bcc4973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291554103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
291554103
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2365724277
Short name T190
Test name
Test status
Simulation time 122221731 ps
CPU time 1.19 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 196948 kb
Host smart-ad8ebea3-630c-4a0e-ad9f-a909b85409da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365724277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2365724277
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3118380871
Short name T514
Test name
Test status
Simulation time 60112908 ps
CPU time 1.08 seconds
Started Apr 30 12:22:49 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 196756 kb
Host smart-aefaa483-6667-4e6e-86ef-8aacc09414e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118380871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3118380871
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.458378241
Short name T649
Test name
Test status
Simulation time 249745431 ps
CPU time 2.21 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 197844 kb
Host smart-79451ff4-1f5f-47c5-a747-aac111e59e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458378241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.458378241
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1498669292
Short name T183
Test name
Test status
Simulation time 143955108 ps
CPU time 0.85 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 195388 kb
Host smart-1a2598c7-4f1e-49e2-8e20-557e2afd7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498669292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1498669292
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.61069357
Short name T324
Test name
Test status
Simulation time 170724721 ps
CPU time 1.25 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 196640 kb
Host smart-4f3fed95-5db8-4cc3-acf7-b7d22e5989fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61069357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.61069357
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2552472564
Short name T551
Test name
Test status
Simulation time 4560396975 ps
CPU time 45.9 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:23:44 PM PDT 24
Peak memory 198072 kb
Host smart-421a2327-031d-474e-8231-d84a1357bf42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552472564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2552472564
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2784968159
Short name T370
Test name
Test status
Simulation time 235834292869 ps
CPU time 1076.51 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:40:53 PM PDT 24
Peak memory 198080 kb
Host smart-7ace9737-1e84-44fa-bb44-1f9078bbf7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2784968159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2784968159
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1611111131
Short name T298
Test name
Test status
Simulation time 23062370 ps
CPU time 0.56 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 193760 kb
Host smart-493a145a-3b3c-4cfe-99a6-d88ec9bef317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611111131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1611111131
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1608213588
Short name T579
Test name
Test status
Simulation time 193006329 ps
CPU time 0.97 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 197184 kb
Host smart-017ee05f-9983-4066-beed-8594b10914ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608213588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1608213588
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2297115553
Short name T641
Test name
Test status
Simulation time 288016867 ps
CPU time 15.18 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195348 kb
Host smart-c3a7f3af-106b-49a9-a147-f2f1f7c2594c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297115553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2297115553
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3879843481
Short name T26
Test name
Test status
Simulation time 158335713 ps
CPU time 0.85 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 195888 kb
Host smart-fadb62dc-2cfe-4264-8915-04895235dc19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879843481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3879843481
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1475500004
Short name T423
Test name
Test status
Simulation time 17249394 ps
CPU time 0.75 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 194280 kb
Host smart-2ed18fad-6af3-4fe8-b70a-84b446aea3e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475500004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1475500004
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2407067207
Short name T262
Test name
Test status
Simulation time 163948054 ps
CPU time 3.08 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 197948 kb
Host smart-131cf2aa-c396-4143-932b-a91e95a464b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407067207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2407067207
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3461404787
Short name T141
Test name
Test status
Simulation time 107394659 ps
CPU time 0.9 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 194792 kb
Host smart-b4e6d5ed-4150-4e84-8ac0-9f8e0a9d6263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461404787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3461404787
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.305002820
Short name T382
Test name
Test status
Simulation time 582625009 ps
CPU time 0.87 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 196604 kb
Host smart-6e8458fb-c8bb-49d4-b63b-a297630159d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305002820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.305002820
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4105232423
Short name T122
Test name
Test status
Simulation time 94478705 ps
CPU time 0.73 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:22:59 PM PDT 24
Peak memory 195156 kb
Host smart-20a0c29f-a8e4-40dc-a145-b95cbe307510
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105232423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4105232423
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2015061243
Short name T368
Test name
Test status
Simulation time 275662471 ps
CPU time 3.3 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 197652 kb
Host smart-3f11ed82-9fb6-46db-b45f-0de220e902ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015061243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2015061243
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1025199668
Short name T132
Test name
Test status
Simulation time 48703409 ps
CPU time 1.03 seconds
Started Apr 30 12:22:51 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 195704 kb
Host smart-10043957-f26d-44df-91b8-b9f3c36753d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025199668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1025199668
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3445155675
Short name T250
Test name
Test status
Simulation time 63354111 ps
CPU time 1.13 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 195748 kb
Host smart-91c92a0a-2ea8-4ca6-b277-1b791ef08be1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445155675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3445155675
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.136751960
Short name T257
Test name
Test status
Simulation time 12290767581 ps
CPU time 59.72 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:23:56 PM PDT 24
Peak memory 198024 kb
Host smart-74c67921-9d1a-4d60-9e80-d08e07ed682f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136751960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.136751960
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1596512318
Short name T241
Test name
Test status
Simulation time 15203370 ps
CPU time 0.58 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:05 PM PDT 24
Peak memory 193808 kb
Host smart-6d3cd4fe-d717-45d0-9881-95706045d554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596512318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1596512318
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.629116864
Short name T140
Test name
Test status
Simulation time 23071073 ps
CPU time 0.8 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:22:50 PM PDT 24
Peak memory 195224 kb
Host smart-458ba225-9980-4a5b-85d0-bce04a37a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629116864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.629116864
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2423500349
Short name T523
Test name
Test status
Simulation time 408942122 ps
CPU time 3.7 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 196092 kb
Host smart-0e43c86b-c5a9-4dc3-925b-44da3098744a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423500349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2423500349
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2797565143
Short name T668
Test name
Test status
Simulation time 341905163 ps
CPU time 1.06 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 196320 kb
Host smart-b1300fc6-0158-4a35-a85f-67287b01632f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797565143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2797565143
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2903255333
Short name T513
Test name
Test status
Simulation time 176616808 ps
CPU time 0.96 seconds
Started Apr 30 12:22:50 PM PDT 24
Finished Apr 30 12:22:52 PM PDT 24
Peak memory 195952 kb
Host smart-e30dac5f-1a18-49f0-a637-c73527347471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903255333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2903255333
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2494901765
Short name T285
Test name
Test status
Simulation time 90133898 ps
CPU time 3.38 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 197908 kb
Host smart-a94cec8d-7b3e-468a-a0fc-ad32c8270eb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494901765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2494901765
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.733561388
Short name T613
Test name
Test status
Simulation time 172339020 ps
CPU time 2.96 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 198004 kb
Host smart-eb03994f-e46c-4e35-83f7-9b71c6baf194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733561388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
733561388
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.182418025
Short name T286
Test name
Test status
Simulation time 52387942 ps
CPU time 1.01 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:22:58 PM PDT 24
Peak memory 195836 kb
Host smart-25b4413d-5c8a-4ecc-8500-03d6beed39ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182418025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.182418025
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.224628298
Short name T681
Test name
Test status
Simulation time 46753960 ps
CPU time 0.98 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 195288 kb
Host smart-4c33e701-2789-4078-a50d-c2058256e234
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224628298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.224628298
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3978782710
Short name T256
Test name
Test status
Simulation time 83661780 ps
CPU time 1.05 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 196112 kb
Host smart-c1e7c745-eb9f-43d6-a44b-9728b6964459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978782710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3978782710
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3885356985
Short name T492
Test name
Test status
Simulation time 238066151 ps
CPU time 1.13 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:22:54 PM PDT 24
Peak memory 196088 kb
Host smart-4906cabb-d766-44d1-ada7-a5fee591f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885356985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3885356985
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2253025776
Short name T493
Test name
Test status
Simulation time 92222734 ps
CPU time 0.98 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 195560 kb
Host smart-945a640d-db9b-4423-87f8-1e10f2b36af8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253025776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2253025776
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1312135139
Short name T611
Test name
Test status
Simulation time 13333489335 ps
CPU time 146.41 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:25:27 PM PDT 24
Peak memory 198048 kb
Host smart-2c834f95-a797-4962-96e4-9f5adb3352ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312135139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1312135139
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.75817560
Short name T399
Test name
Test status
Simulation time 12466206 ps
CPU time 0.62 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 191692 kb
Host smart-e9d32e5e-2af7-48a9-8b8d-25db41d40a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75817560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.75817560
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.982427045
Short name T577
Test name
Test status
Simulation time 68618620 ps
CPU time 0.75 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 194876 kb
Host smart-54e244fd-730b-42a9-a42d-98ca66a89f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982427045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.982427045
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1313107088
Short name T635
Test name
Test status
Simulation time 721883192 ps
CPU time 11.13 seconds
Started Apr 30 12:21:22 PM PDT 24
Finished Apr 30 12:21:33 PM PDT 24
Peak memory 196820 kb
Host smart-7e096b8a-4030-4114-abf5-5aa4e8e0c4ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313107088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1313107088
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2644524502
Short name T2
Test name
Test status
Simulation time 320447671 ps
CPU time 0.92 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 197252 kb
Host smart-f3479980-a322-4879-8f77-fb4e9e2a7523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644524502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2644524502
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1115605816
Short name T498
Test name
Test status
Simulation time 40562574 ps
CPU time 1.11 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 194412 kb
Host smart-44d81324-6977-436c-b9f7-9ad982e3c79d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115605816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1115605816
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.123141348
Short name T467
Test name
Test status
Simulation time 59980267 ps
CPU time 1.19 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 196468 kb
Host smart-129b7e13-fa7b-4ec4-b463-04a942015cd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123141348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.123141348
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.380428536
Short name T172
Test name
Test status
Simulation time 524353856 ps
CPU time 2.14 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 196588 kb
Host smart-14f7e6bf-9056-4846-b131-d4eb82ce4ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380428536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.380428536
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2856015318
Short name T639
Test name
Test status
Simulation time 108858540 ps
CPU time 1.33 seconds
Started Apr 30 12:20:19 PM PDT 24
Finished Apr 30 12:20:20 PM PDT 24
Peak memory 196908 kb
Host smart-43abd9f4-e05e-45ab-89d2-c53a0ef29e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856015318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2856015318
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1515281552
Short name T326
Test name
Test status
Simulation time 20805585 ps
CPU time 0.84 seconds
Started Apr 30 12:20:07 PM PDT 24
Finished Apr 30 12:20:09 PM PDT 24
Peak memory 196708 kb
Host smart-d816192f-d2a0-488a-9aa1-d2c9186692c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515281552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1515281552
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4060404494
Short name T369
Test name
Test status
Simulation time 34162807 ps
CPU time 1.72 seconds
Started Apr 30 12:21:55 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 197620 kb
Host smart-0eb34716-c3c2-4ab6-85db-e494bbae698c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060404494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4060404494
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1132086413
Short name T37
Test name
Test status
Simulation time 126744817 ps
CPU time 0.75 seconds
Started Apr 30 12:23:08 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 213116 kb
Host smart-0fd93668-61c4-487a-9c6a-00a6ba75a971
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132086413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1132086413
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.927562869
Short name T354
Test name
Test status
Simulation time 184008425 ps
CPU time 1.02 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 195080 kb
Host smart-84e7ac42-7251-4a1a-bc09-81080701727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927562869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.927562869
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2053514305
Short name T126
Test name
Test status
Simulation time 44344780 ps
CPU time 1.2 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:22:49 PM PDT 24
Peak memory 195272 kb
Host smart-aac8f218-9c63-4308-b1a5-e0f10ae24c8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053514305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2053514305
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2889440925
Short name T59
Test name
Test status
Simulation time 5624162465 ps
CPU time 85.33 seconds
Started Apr 30 12:21:22 PM PDT 24
Finished Apr 30 12:22:48 PM PDT 24
Peak memory 198200 kb
Host smart-d87301ff-dc30-4ddf-a733-3c85186da34e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889440925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2889440925
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4004011923
Short name T289
Test name
Test status
Simulation time 34583800 ps
CPU time 0.56 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 193620 kb
Host smart-ffc3a3f1-0f8c-4bfb-9949-e61e9ef1bf33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004011923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4004011923
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1473723897
Short name T383
Test name
Test status
Simulation time 34447871 ps
CPU time 0.76 seconds
Started Apr 30 12:23:08 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 195216 kb
Host smart-bc184f1e-da64-4343-8505-8f484b68d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473723897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1473723897
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3963673291
Short name T658
Test name
Test status
Simulation time 1729898778 ps
CPU time 9.05 seconds
Started Apr 30 12:23:10 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 196900 kb
Host smart-e98403f0-f760-4be5-844c-b0b5adbb721f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963673291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3963673291
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.587841701
Short name T525
Test name
Test status
Simulation time 71675384 ps
CPU time 1 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 196284 kb
Host smart-780e8bc1-4927-4dcb-af58-d2024a76388a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587841701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.587841701
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3986232455
Short name T18
Test name
Test status
Simulation time 73525333 ps
CPU time 0.93 seconds
Started Apr 30 12:23:10 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 196704 kb
Host smart-1db3d326-f155-45fe-a426-ac2e85af0f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986232455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3986232455
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1777116300
Short name T58
Test name
Test status
Simulation time 110465742 ps
CPU time 2.2 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 197948 kb
Host smart-752d457d-c9e7-48c0-982b-7a948d3b6daa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777116300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1777116300
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.307221547
Short name T251
Test name
Test status
Simulation time 85539681 ps
CPU time 1.92 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 195948 kb
Host smart-0a856f3e-72b7-4b3d-9b69-e51451fe5c34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307221547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
307221547
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3251010462
Short name T102
Test name
Test status
Simulation time 166964075 ps
CPU time 1.03 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 195572 kb
Host smart-2a48b078-8785-4934-a039-2f1f857f9e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251010462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3251010462
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2573102230
Short name T562
Test name
Test status
Simulation time 37685437 ps
CPU time 1.24 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195740 kb
Host smart-84f755f5-d11a-4439-9851-13eacfd34349
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573102230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2573102230
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.223411069
Short name T508
Test name
Test status
Simulation time 301055238 ps
CPU time 4.98 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 197800 kb
Host smart-f987db50-938a-47e4-9dea-2812471db474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223411069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.223411069
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3196639963
Short name T214
Test name
Test status
Simulation time 37942299 ps
CPU time 0.82 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 195228 kb
Host smart-2005cf69-6f27-4082-b121-8c62d378708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196639963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3196639963
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.125607322
Short name T353
Test name
Test status
Simulation time 149166512 ps
CPU time 0.93 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 195380 kb
Host smart-5e6d3b8a-d5ec-429a-8bf7-226ff8b23257
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125607322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.125607322
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1087198381
Short name T458
Test name
Test status
Simulation time 5653384780 ps
CPU time 75.65 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:24:21 PM PDT 24
Peak memory 198020 kb
Host smart-2c6b2b6b-9ce6-4774-9505-2d2c1687a031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087198381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1087198381
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1698363767
Short name T67
Test name
Test status
Simulation time 42242727961 ps
CPU time 1100.09 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:41:18 PM PDT 24
Peak memory 198104 kb
Host smart-1a394a77-1262-475d-bfc6-cb2e2fd25a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1698363767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1698363767
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2396428421
Short name T496
Test name
Test status
Simulation time 31827874 ps
CPU time 0.63 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:22:59 PM PDT 24
Peak memory 193920 kb
Host smart-b2af9787-eacb-41a2-bfcf-3c1bdee061cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396428421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2396428421
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1090857497
Short name T200
Test name
Test status
Simulation time 24806095 ps
CPU time 0.78 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 195216 kb
Host smart-b95f7592-88b4-4d66-976b-eaca130b6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090857497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1090857497
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3880507929
Short name T628
Test name
Test status
Simulation time 1584405195 ps
CPU time 16.61 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:29 PM PDT 24
Peak memory 197852 kb
Host smart-7a2958b9-0615-4f33-8e66-5b14d436fa44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880507929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3880507929
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.553511074
Short name T106
Test name
Test status
Simulation time 102497490 ps
CPU time 0.86 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 196564 kb
Host smart-f120dba0-5b56-4785-a1a6-458c08e5663a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553511074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.553511074
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3654080164
Short name T156
Test name
Test status
Simulation time 228438090 ps
CPU time 1.05 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 195688 kb
Host smart-eb416350-9f7a-40fd-8e17-69f1598da60a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654080164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3654080164
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.425312610
Short name T698
Test name
Test status
Simulation time 38234007 ps
CPU time 1.71 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:02 PM PDT 24
Peak memory 196952 kb
Host smart-bb8b7b91-4c4c-489d-891c-99ba6a8f09cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425312610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.425312610
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2437156106
Short name T246
Test name
Test status
Simulation time 114563431 ps
CPU time 3.34 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 197940 kb
Host smart-fdf247a0-ce45-4162-bf59-afdc40a080c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437156106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2437156106
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3773639500
Short name T621
Test name
Test status
Simulation time 76936499 ps
CPU time 1.23 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 196088 kb
Host smart-8913ed27-3479-4cb7-b9d8-cd942dffc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773639500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3773639500
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2857229411
Short name T363
Test name
Test status
Simulation time 273868433 ps
CPU time 0.73 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 195352 kb
Host smart-5b44b726-aeff-4406-bd22-0464b8291316
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857229411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2857229411
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1164286951
Short name T555
Test name
Test status
Simulation time 157113897 ps
CPU time 1.87 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 197748 kb
Host smart-01bbde76-ac02-4d00-a7f2-d7f6565a71f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164286951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1164286951
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2394179288
Short name T421
Test name
Test status
Simulation time 120113283 ps
CPU time 1.03 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195332 kb
Host smart-1bbad89a-609f-40f2-9c5f-7f2e83032999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394179288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2394179288
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3260944682
Short name T486
Test name
Test status
Simulation time 91716622 ps
CPU time 1.24 seconds
Started Apr 30 12:23:10 PM PDT 24
Finished Apr 30 12:23:12 PM PDT 24
Peak memory 197608 kb
Host smart-428cbcfb-8e32-4310-8980-1c7ad3af2367
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260944682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3260944682
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3582974091
Short name T277
Test name
Test status
Simulation time 19963038400 ps
CPU time 139.29 seconds
Started Apr 30 12:22:57 PM PDT 24
Finished Apr 30 12:25:17 PM PDT 24
Peak memory 198052 kb
Host smart-fc703a62-e2b8-4137-8673-62b697a6fbe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582974091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3582974091
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.861934856
Short name T139
Test name
Test status
Simulation time 54450069 ps
CPU time 0.58 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 194556 kb
Host smart-6c08f67b-2d3a-4a6f-bc65-78bc853eb493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861934856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.861934856
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1146133377
Short name T549
Test name
Test status
Simulation time 24945336 ps
CPU time 0.69 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 194680 kb
Host smart-8475176a-1d07-4694-8811-43275d4fcad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146133377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1146133377
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2194286471
Short name T622
Test name
Test status
Simulation time 275899078 ps
CPU time 12.61 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:20 PM PDT 24
Peak memory 196328 kb
Host smart-74a500f9-3185-4141-9a86-27b047c7feb7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194286471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2194286471
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1418319617
Short name T678
Test name
Test status
Simulation time 178458859 ps
CPU time 0.87 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195888 kb
Host smart-e174a82a-c72f-4a83-9718-8577aed7bea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418319617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1418319617
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.709073566
Short name T301
Test name
Test status
Simulation time 92320504 ps
CPU time 1.2 seconds
Started Apr 30 12:23:09 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 196988 kb
Host smart-44ea9eff-3fd5-42d9-8e90-5f61c35b7cd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709073566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.709073566
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2951219781
Short name T600
Test name
Test status
Simulation time 93135547 ps
CPU time 1.23 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 196820 kb
Host smart-cbf3444f-93b6-4771-9c7c-5148028ee0b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951219781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2951219781
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1792940272
Short name T121
Test name
Test status
Simulation time 47740214 ps
CPU time 1.12 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 196352 kb
Host smart-a785caf5-61f6-454c-8e89-1c92b1dd6a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792940272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1792940272
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2274565466
Short name T55
Test name
Test status
Simulation time 42727022 ps
CPU time 0.69 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 195316 kb
Host smart-22930ec4-3524-4a08-bc78-ee501dbe3561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274565466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2274565466
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1873001183
Short name T501
Test name
Test status
Simulation time 127008095 ps
CPU time 1.09 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 195640 kb
Host smart-a2955b94-6e1f-4f8d-9ee5-acc04109722a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873001183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1873001183
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4277660395
Short name T409
Test name
Test status
Simulation time 95326406 ps
CPU time 2.58 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:04 PM PDT 24
Peak memory 197824 kb
Host smart-2b49dd34-29c7-405d-9465-05e62b2dfd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277660395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4277660395
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1532220446
Short name T165
Test name
Test status
Simulation time 36538303 ps
CPU time 1.06 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195340 kb
Host smart-24393f13-de8c-4951-9bfe-741be5d40820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532220446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1532220446
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1687631904
Short name T619
Test name
Test status
Simulation time 96341782 ps
CPU time 1.22 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 195384 kb
Host smart-de16077c-4b25-4858-85ec-45e95a3a9a1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687631904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1687631904
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1703656684
Short name T10
Test name
Test status
Simulation time 31903128746 ps
CPU time 185.05 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:26:10 PM PDT 24
Peak memory 197988 kb
Host smart-b23c1ff3-979b-4ddd-994d-6e94d552927b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703656684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1703656684
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3519089261
Short name T348
Test name
Test status
Simulation time 51027939441 ps
CPU time 1347.17 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:45:32 PM PDT 24
Peak memory 198132 kb
Host smart-cd72e28d-0fc7-450b-b610-db9ba14d8417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3519089261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3519089261
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2519092828
Short name T413
Test name
Test status
Simulation time 11416561 ps
CPU time 0.55 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 193776 kb
Host smart-22e2f0f8-bf6f-4d71-a385-b9b3be7950eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519092828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2519092828
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3033550808
Short name T175
Test name
Test status
Simulation time 87859723 ps
CPU time 0.94 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 196444 kb
Host smart-39f739da-629f-4557-86a3-0307dd9eddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033550808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3033550808
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3793234789
Short name T270
Test name
Test status
Simulation time 3079186908 ps
CPU time 17.09 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:26 PM PDT 24
Peak memory 196972 kb
Host smart-4276439e-ca25-47f7-9efb-276376452117
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793234789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3793234789
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3135088459
Short name T153
Test name
Test status
Simulation time 150156136 ps
CPU time 0.77 seconds
Started Apr 30 12:23:08 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 195908 kb
Host smart-c826efc4-a7e8-431b-a14d-a7289eccbc56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135088459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3135088459
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2234689175
Short name T316
Test name
Test status
Simulation time 187350202 ps
CPU time 0.99 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 195444 kb
Host smart-81867657-d5ba-4260-812a-02f192d19e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234689175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2234689175
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2527558647
Short name T164
Test name
Test status
Simulation time 61691720 ps
CPU time 1.27 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 196784 kb
Host smart-938b8afa-6358-4bca-91a3-65d67148df37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527558647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2527558647
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3190514076
Short name T154
Test name
Test status
Simulation time 253965356 ps
CPU time 2.49 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 196344 kb
Host smart-0d674a15-6ab6-43d4-b13f-e00e8af0a94f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190514076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3190514076
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1050374383
Short name T70
Test name
Test status
Simulation time 32535158 ps
CPU time 0.71 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 195272 kb
Host smart-f31c97a5-f2e3-46bc-afd8-78d1e6acd199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050374383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1050374383
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.386538283
Short name T231
Test name
Test status
Simulation time 41722971 ps
CPU time 0.95 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 195812 kb
Host smart-c5976c91-fdf6-40bd-ae76-d1e621df1af0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386538283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.386538283
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3046919225
Short name T391
Test name
Test status
Simulation time 314127200 ps
CPU time 4.18 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 197772 kb
Host smart-ba70248c-dfd9-4b51-890d-ed64872d9a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046919225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3046919225
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3238730912
Short name T589
Test name
Test status
Simulation time 70524643 ps
CPU time 1.19 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 195596 kb
Host smart-6f15fd50-d154-4031-8bb5-327719bf0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238730912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3238730912
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.994724855
Short name T264
Test name
Test status
Simulation time 262334484 ps
CPU time 1.35 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 196716 kb
Host smart-e43cc5da-dc19-42bb-bdce-689d0086c19f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994724855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.994724855
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2915507958
Short name T119
Test name
Test status
Simulation time 19925455284 ps
CPU time 202.13 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:26:37 PM PDT 24
Peak memory 197988 kb
Host smart-2b970716-79a5-4291-bdd3-aa29458f6b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915507958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2915507958
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2494186260
Short name T335
Test name
Test status
Simulation time 12655533 ps
CPU time 0.57 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 193716 kb
Host smart-e5221a3a-94fc-4e12-b8c5-83531c8b4a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494186260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2494186260
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3887915822
Short name T588
Test name
Test status
Simulation time 135312787 ps
CPU time 0.72 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 195152 kb
Host smart-1f127948-cdd4-414b-b024-1b0ea15f795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887915822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3887915822
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1580342719
Short name T52
Test name
Test status
Simulation time 13055060029 ps
CPU time 21.45 seconds
Started Apr 30 12:23:10 PM PDT 24
Finished Apr 30 12:23:32 PM PDT 24
Peak memory 196700 kb
Host smart-09973fcf-39aa-483c-bb13-1b5c64e7104b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580342719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1580342719
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3362784430
Short name T459
Test name
Test status
Simulation time 523037630 ps
CPU time 0.87 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 196700 kb
Host smart-6f37d4de-ba71-4591-bc97-6bd3193349a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362784430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3362784430
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1200424837
Short name T166
Test name
Test status
Simulation time 59408704 ps
CPU time 0.71 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 194196 kb
Host smart-c3aec45b-ee23-4de9-8b34-7bb1e108dcab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200424837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1200424837
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3475816521
Short name T465
Test name
Test status
Simulation time 22814392 ps
CPU time 0.89 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 195308 kb
Host smart-26567141-865c-4ef2-ae9f-f209fc844a87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475816521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3475816521
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3619304821
Short name T147
Test name
Test status
Simulation time 648793239 ps
CPU time 3.32 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:23 PM PDT 24
Peak memory 195808 kb
Host smart-ef6b3a2f-3d5e-4e27-83fd-26a6175a1939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619304821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3619304821
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2217398919
Short name T71
Test name
Test status
Simulation time 63223570 ps
CPU time 0.74 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 195976 kb
Host smart-d9d76e30-af91-46e0-b736-ab8eee91267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217398919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2217398919
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4245063827
Short name T618
Test name
Test status
Simulation time 18178659 ps
CPU time 0.72 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 195240 kb
Host smart-df0bf1fe-082f-4cf7-be62-2c94addf0a30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245063827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4245063827
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3556635314
Short name T202
Test name
Test status
Simulation time 307692633 ps
CPU time 2.55 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:22 PM PDT 24
Peak memory 197252 kb
Host smart-f65b5cea-bcb2-4ffe-9f14-1c95eeebd541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556635314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3556635314
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3614818860
Short name T594
Test name
Test status
Simulation time 82496792 ps
CPU time 1.31 seconds
Started Apr 30 12:23:12 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 195400 kb
Host smart-5b0608b6-2675-43e9-a2f5-dc47f9d43881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614818860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3614818860
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4036768187
Short name T601
Test name
Test status
Simulation time 78375846 ps
CPU time 0.97 seconds
Started Apr 30 12:23:06 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 195412 kb
Host smart-bfb7459b-a96c-41ab-aa42-1746553d4f8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036768187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4036768187
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2552459668
Short name T222
Test name
Test status
Simulation time 6715275509 ps
CPU time 164.26 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:25:59 PM PDT 24
Peak memory 197924 kb
Host smart-20bf8ce7-ad27-4c46-bbb5-3b66dd99517a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552459668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2552459668
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3135493636
Short name T443
Test name
Test status
Simulation time 49158648 ps
CPU time 0.56 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 192788 kb
Host smart-b1684020-67e3-44a5-a186-0a2eb4cfc9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135493636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3135493636
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1878823322
Short name T520
Test name
Test status
Simulation time 311749890 ps
CPU time 0.71 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 193640 kb
Host smart-1f76dd05-cf8a-4542-8df0-d6a7588a736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878823322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1878823322
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2412625680
Short name T206
Test name
Test status
Simulation time 4700690894 ps
CPU time 14.49 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:31 PM PDT 24
Peak memory 195788 kb
Host smart-1ac1a9cc-c812-496a-aa60-65e6272fb0af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412625680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2412625680
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.69991149
Short name T265
Test name
Test status
Simulation time 62263975 ps
CPU time 0.86 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 196648 kb
Host smart-af5fa524-5983-4d16-adba-95796964223e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69991149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.69991149
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4006203104
Short name T475
Test name
Test status
Simulation time 84088476 ps
CPU time 1.19 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 196052 kb
Host smart-94f8e142-f4b0-4bfe-a832-752582dab109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006203104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4006203104
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3855465430
Short name T706
Test name
Test status
Simulation time 71325783 ps
CPU time 2.13 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:21 PM PDT 24
Peak memory 195760 kb
Host smart-d16a42bd-f661-4439-b46c-5f493f1adace
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855465430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3855465430
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.311126981
Short name T625
Test name
Test status
Simulation time 542751447 ps
CPU time 2.7 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 197144 kb
Host smart-9f59bac6-fdc3-4173-a4a6-b3d13c4926ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311126981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
311126981
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.310541134
Short name T645
Test name
Test status
Simulation time 31627039 ps
CPU time 1.14 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 196604 kb
Host smart-d79d7e60-c6a6-4d5f-95df-311c91ba5b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310541134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.310541134
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.550342557
Short name T671
Test name
Test status
Simulation time 120177418 ps
CPU time 1.11 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 194288 kb
Host smart-41ef2528-796f-4057-a0e4-2782e5d7c8a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550342557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.550342557
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3394862766
Short name T302
Test name
Test status
Simulation time 610255617 ps
CPU time 5.05 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:23:28 PM PDT 24
Peak memory 197792 kb
Host smart-ccf87253-09a1-4c1c-9565-a5bcf00016a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394862766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3394862766
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1849348782
Short name T169
Test name
Test status
Simulation time 43732971 ps
CPU time 1.19 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 192796 kb
Host smart-8dbf7d49-2c9d-4dfa-b750-2481cffc99fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849348782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1849348782
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.240227252
Short name T142
Test name
Test status
Simulation time 265021274 ps
CPU time 1.16 seconds
Started Apr 30 12:24:18 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 193100 kb
Host smart-0edef7ee-c1e0-4180-ae04-614838c40a7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240227252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.240227252
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1185255545
Short name T242
Test name
Test status
Simulation time 7821578419 ps
CPU time 35.53 seconds
Started Apr 30 12:23:11 PM PDT 24
Finished Apr 30 12:23:47 PM PDT 24
Peak memory 198080 kb
Host smart-ec1dea5b-04fb-4e49-9fab-d4a26f7a76fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185255545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1185255545
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2181921551
Short name T32
Test name
Test status
Simulation time 278612367754 ps
CPU time 998.31 seconds
Started Apr 30 12:23:13 PM PDT 24
Finished Apr 30 12:39:52 PM PDT 24
Peak memory 198148 kb
Host smart-4edacb7d-1d70-4f4b-a203-c89e02905680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2181921551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2181921551
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1710264465
Short name T503
Test name
Test status
Simulation time 36535476 ps
CPU time 0.6 seconds
Started Apr 30 12:23:13 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 194828 kb
Host smart-06cb6c0d-dd71-4371-aa0f-212aefb678ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710264465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1710264465
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2294289180
Short name T694
Test name
Test status
Simulation time 159261226 ps
CPU time 0.86 seconds
Started Apr 30 12:23:32 PM PDT 24
Finished Apr 30 12:23:34 PM PDT 24
Peak memory 196452 kb
Host smart-ab4daf01-7568-47ff-9ce0-99299dc1ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294289180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2294289180
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1537073231
Short name T229
Test name
Test status
Simulation time 1983806745 ps
CPU time 15.2 seconds
Started Apr 30 12:23:55 PM PDT 24
Finished Apr 30 12:24:11 PM PDT 24
Peak memory 196052 kb
Host smart-a23a2c67-4f5e-4bf6-beb5-aaa8b006cc72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537073231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1537073231
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1073979678
Short name T275
Test name
Test status
Simulation time 51374568 ps
CPU time 0.84 seconds
Started Apr 30 12:23:34 PM PDT 24
Finished Apr 30 12:23:35 PM PDT 24
Peak memory 196540 kb
Host smart-2def1373-4ef9-460d-8447-67be4221d0d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073979678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1073979678
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.975593870
Short name T684
Test name
Test status
Simulation time 545636607 ps
CPU time 0.76 seconds
Started Apr 30 12:23:11 PM PDT 24
Finished Apr 30 12:23:12 PM PDT 24
Peak memory 196116 kb
Host smart-d32d4f8f-9981-4fee-a07e-f276b102bf10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975593870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.975593870
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2778876902
Short name T72
Test name
Test status
Simulation time 292361207 ps
CPU time 2.86 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 197992 kb
Host smart-d02cc663-96d7-4b05-9b86-33666b631c3d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778876902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2778876902
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3407704776
Short name T193
Test name
Test status
Simulation time 485955913 ps
CPU time 3.11 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 195900 kb
Host smart-f0c099b0-078a-428e-a6ab-c4990c85b651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407704776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3407704776
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.897198025
Short name T716
Test name
Test status
Simulation time 291375983 ps
CPU time 1.34 seconds
Started Apr 30 12:23:13 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 196592 kb
Host smart-70279311-83f6-4d21-abaf-5b0fe7150e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897198025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.897198025
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1229416268
Short name T255
Test name
Test status
Simulation time 41925085 ps
CPU time 0.91 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 195512 kb
Host smart-03551943-53f8-4d33-a890-848e128d207c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229416268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1229416268
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4171428631
Short name T644
Test name
Test status
Simulation time 199216202 ps
CPU time 2.27 seconds
Started Apr 30 12:23:13 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 197880 kb
Host smart-74e13782-bcf8-4dd8-8e69-cab9225436bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171428631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4171428631
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2192745091
Short name T194
Test name
Test status
Simulation time 72236543 ps
CPU time 1.22 seconds
Started Apr 30 12:24:31 PM PDT 24
Finished Apr 30 12:24:33 PM PDT 24
Peak memory 195876 kb
Host smart-5a83cf41-ca1f-4175-b34a-02f98feb65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192745091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2192745091
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3139913919
Short name T226
Test name
Test status
Simulation time 474241045 ps
CPU time 1.43 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 194088 kb
Host smart-6e07ea0c-125f-4f8d-a244-779b61e89337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139913919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3139913919
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3629124977
Short name T207
Test name
Test status
Simulation time 41483395973 ps
CPU time 237.52 seconds
Started Apr 30 12:23:25 PM PDT 24
Finished Apr 30 12:27:24 PM PDT 24
Peak memory 198084 kb
Host smart-49ce8ba0-d021-46a1-97b9-f03090909b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629124977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3629124977
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3259589534
Short name T677
Test name
Test status
Simulation time 40529430522 ps
CPU time 338.63 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 195696 kb
Host smart-2d8d8d8e-c831-42a4-aa68-f84c938db761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3259589534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3259589534
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2700789249
Short name T581
Test name
Test status
Simulation time 13119807 ps
CPU time 0.54 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 193476 kb
Host smart-8d1fd26f-57dd-4c42-ba39-e9b2c765b521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700789249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2700789249
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3603555076
Short name T460
Test name
Test status
Simulation time 26238368 ps
CPU time 0.73 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:15 PM PDT 24
Peak memory 195512 kb
Host smart-5dc31393-7c2f-4575-b5f1-5e9c8a9b0067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603555076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3603555076
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.74439848
Short name T29
Test name
Test status
Simulation time 1019266899 ps
CPU time 26.38 seconds
Started Apr 30 12:23:45 PM PDT 24
Finished Apr 30 12:24:12 PM PDT 24
Peak memory 196872 kb
Host smart-8ae17a85-310f-4651-b30e-3920b11258d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74439848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress
.74439848
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3602063998
Short name T403
Test name
Test status
Simulation time 158095615 ps
CPU time 0.99 seconds
Started Apr 30 12:23:51 PM PDT 24
Finished Apr 30 12:23:53 PM PDT 24
Peak memory 196440 kb
Host smart-256e5f42-4b01-4549-8f6a-4ad97f2fa1c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602063998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3602063998
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2416291550
Short name T191
Test name
Test status
Simulation time 187590756 ps
CPU time 0.9 seconds
Started Apr 30 12:23:32 PM PDT 24
Finished Apr 30 12:23:33 PM PDT 24
Peak memory 195720 kb
Host smart-c99275b9-5ce5-4d33-ac09-e7de6918d88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416291550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2416291550
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2729060624
Short name T431
Test name
Test status
Simulation time 80995509 ps
CPU time 3.04 seconds
Started Apr 30 12:23:31 PM PDT 24
Finished Apr 30 12:23:35 PM PDT 24
Peak memory 198036 kb
Host smart-260fac33-fc6a-4663-b8ff-d4e88b851d39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729060624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2729060624
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4031427425
Short name T293
Test name
Test status
Simulation time 248766100 ps
CPU time 2.79 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 196908 kb
Host smart-be62cb23-d222-4413-8e51-a6a992bd7d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031427425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4031427425
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3414107227
Short name T615
Test name
Test status
Simulation time 73908694 ps
CPU time 1.38 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:33 PM PDT 24
Peak memory 196188 kb
Host smart-152a0407-15d1-423d-a21f-08418c820929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414107227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3414107227
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.68289019
Short name T582
Test name
Test status
Simulation time 114468020 ps
CPU time 0.87 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:15 PM PDT 24
Peak memory 196720 kb
Host smart-2b07fc52-3c66-42e9-a4ea-d53d4649cc4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68289019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup_
pulldown.68289019
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.632690942
Short name T518
Test name
Test status
Simulation time 653725664 ps
CPU time 4.23 seconds
Started Apr 30 12:23:22 PM PDT 24
Finished Apr 30 12:23:27 PM PDT 24
Peak memory 197980 kb
Host smart-64b15550-d38f-4983-80f3-9a9a8eb16ba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632690942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.632690942
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1886083442
Short name T195
Test name
Test status
Simulation time 53646222 ps
CPU time 1.25 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:23:25 PM PDT 24
Peak memory 196164 kb
Host smart-eb5fafd7-133a-47b3-b7e5-a5c922eb5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886083442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1886083442
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3125735926
Short name T350
Test name
Test status
Simulation time 71831413 ps
CPU time 1.47 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 195672 kb
Host smart-2a66944d-b73a-40cf-a147-70392e649fce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125735926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3125735926
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.985140147
Short name T134
Test name
Test status
Simulation time 28034320161 ps
CPU time 73.43 seconds
Started Apr 30 12:23:22 PM PDT 24
Finished Apr 30 12:24:41 PM PDT 24
Peak memory 198056 kb
Host smart-470744c1-cc3d-4259-9b59-a2352d9eab8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985140147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.985140147
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3811223216
Short name T487
Test name
Test status
Simulation time 81343820029 ps
CPU time 1204.8 seconds
Started Apr 30 12:23:26 PM PDT 24
Finished Apr 30 12:43:32 PM PDT 24
Peak memory 198112 kb
Host smart-f859e934-c73f-48f2-9ad7-7e49f2f02ad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3811223216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3811223216
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2361911069
Short name T473
Test name
Test status
Simulation time 20172730 ps
CPU time 0.58 seconds
Started Apr 30 12:24:13 PM PDT 24
Finished Apr 30 12:24:14 PM PDT 24
Peak memory 193516 kb
Host smart-73c298c6-17ea-4d73-8dae-ea5e849061bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361911069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2361911069
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.431181733
Short name T160
Test name
Test status
Simulation time 43026579 ps
CPU time 0.61 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 194480 kb
Host smart-524d07aa-c955-40e5-938e-41739b923704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431181733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.431181733
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2633972542
Short name T620
Test name
Test status
Simulation time 8820058532 ps
CPU time 14.55 seconds
Started Apr 30 12:23:24 PM PDT 24
Finished Apr 30 12:23:39 PM PDT 24
Peak memory 197388 kb
Host smart-6c4d9d9a-5efe-4e2e-9285-651b67c7f119
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633972542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2633972542
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2239177514
Short name T247
Test name
Test status
Simulation time 647622334 ps
CPU time 0.69 seconds
Started Apr 30 12:23:26 PM PDT 24
Finished Apr 30 12:23:28 PM PDT 24
Peak memory 194624 kb
Host smart-e2afd251-1bd2-4586-9551-f07972a8c91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239177514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2239177514
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2025251741
Short name T675
Test name
Test status
Simulation time 160711957 ps
CPU time 1.36 seconds
Started Apr 30 12:23:55 PM PDT 24
Finished Apr 30 12:23:58 PM PDT 24
Peak memory 196916 kb
Host smart-f2e14c3d-1c2d-470a-85cd-1ee99a28e1d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025251741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2025251741
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1135697569
Short name T632
Test name
Test status
Simulation time 25537382 ps
CPU time 1.08 seconds
Started Apr 30 12:23:18 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 197388 kb
Host smart-02732ee3-e6cd-474d-820c-007e62fe0eec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135697569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1135697569
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3406028662
Short name T349
Test name
Test status
Simulation time 136366456 ps
CPU time 1.57 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 196076 kb
Host smart-16845c5f-d91f-4033-a1ea-03e1fce77ea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406028662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3406028662
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.489769778
Short name T614
Test name
Test status
Simulation time 65328951 ps
CPU time 0.81 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 192956 kb
Host smart-b1eea54a-cd2c-4585-8b61-7a454df69bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489769778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.489769778
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.854797554
Short name T174
Test name
Test status
Simulation time 141379134 ps
CPU time 1.15 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 195712 kb
Host smart-476fbcf0-f1c0-4021-a3e6-e3c0b8407005
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854797554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.854797554
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2786892744
Short name T345
Test name
Test status
Simulation time 31166997 ps
CPU time 1.31 seconds
Started Apr 30 12:23:41 PM PDT 24
Finished Apr 30 12:23:43 PM PDT 24
Peak memory 197780 kb
Host smart-4a3d2466-da69-41c0-9631-33a9c67092a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786892744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2786892744
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1243560819
Short name T60
Test name
Test status
Simulation time 290819319 ps
CPU time 1.42 seconds
Started Apr 30 12:23:24 PM PDT 24
Finished Apr 30 12:23:26 PM PDT 24
Peak memory 197892 kb
Host smart-0cd4820a-0997-470c-a49a-5850c4e4d734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243560819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1243560819
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.908902267
Short name T276
Test name
Test status
Simulation time 47305215 ps
CPU time 0.92 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:23:25 PM PDT 24
Peak memory 196232 kb
Host smart-bcb5e9ba-a2ec-4dc5-a16c-0873a28d83bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908902267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.908902267
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2900036156
Short name T428
Test name
Test status
Simulation time 16740727476 ps
CPU time 40.9 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:24:07 PM PDT 24
Peak memory 198060 kb
Host smart-7492d9a0-0b7b-44bd-b67c-e55830f09f43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900036156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2900036156
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.262530744
Short name T411
Test name
Test status
Simulation time 49744283 ps
CPU time 0.58 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 194692 kb
Host smart-b970a19f-11f7-4137-92db-8a53bdef5b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262530744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.262530744
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2071220239
Short name T710
Test name
Test status
Simulation time 53199231 ps
CPU time 0.7 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:23:24 PM PDT 24
Peak memory 195188 kb
Host smart-b7813b54-f9e9-4295-8b8d-8e22f4e0d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071220239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2071220239
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4100492346
Short name T402
Test name
Test status
Simulation time 1408919679 ps
CPU time 5.55 seconds
Started Apr 30 12:23:56 PM PDT 24
Finished Apr 30 12:24:03 PM PDT 24
Peak memory 195308 kb
Host smart-8e97a140-df3f-4d59-9467-ce7690fc6aa0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100492346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4100492346
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.909865730
Short name T623
Test name
Test status
Simulation time 54436265 ps
CPU time 0.88 seconds
Started Apr 30 12:23:13 PM PDT 24
Finished Apr 30 12:23:15 PM PDT 24
Peak memory 196012 kb
Host smart-d0c453ec-9d4e-43f3-a24c-ef6c674f3ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909865730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.909865730
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1777617520
Short name T178
Test name
Test status
Simulation time 77793890 ps
CPU time 0.78 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:23:19 PM PDT 24
Peak memory 195444 kb
Host smart-3405beb8-42a1-4251-bb54-ce4a1d19011a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777617520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1777617520
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3332273652
Short name T648
Test name
Test status
Simulation time 97595514 ps
CPU time 2.04 seconds
Started Apr 30 12:23:14 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 197988 kb
Host smart-cbd82a4c-2bb1-43da-9d20-f30bdda60dfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332273652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3332273652
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4146576445
Short name T477
Test name
Test status
Simulation time 147862115 ps
CPU time 2.72 seconds
Started Apr 30 12:23:18 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 197076 kb
Host smart-d63daa4a-6958-4475-b5df-6fb5e021c99f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146576445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4146576445
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.606344764
Short name T708
Test name
Test status
Simulation time 32905838 ps
CPU time 1.22 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:32 PM PDT 24
Peak memory 196600 kb
Host smart-cb144af3-d83e-471f-a8c7-6005de7c6d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606344764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.606344764
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1414078238
Short name T148
Test name
Test status
Simulation time 42938020 ps
CPU time 0.73 seconds
Started Apr 30 12:23:23 PM PDT 24
Finished Apr 30 12:23:24 PM PDT 24
Peak memory 195336 kb
Host smart-e815a43e-696c-42fa-9045-726af913dd25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414078238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1414078238
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1329720312
Short name T232
Test name
Test status
Simulation time 322949122 ps
CPU time 1.76 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:23:20 PM PDT 24
Peak memory 197876 kb
Host smart-b6ad9312-c507-432e-a15e-0d694e767cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329720312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1329720312
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.767081670
Short name T535
Test name
Test status
Simulation time 247207589 ps
CPU time 1.15 seconds
Started Apr 30 12:23:22 PM PDT 24
Finished Apr 30 12:23:24 PM PDT 24
Peak memory 195768 kb
Host smart-20c8c528-08b2-4ddd-b924-12481bd23c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767081670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.767081670
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2870246644
Short name T211
Test name
Test status
Simulation time 86253986 ps
CPU time 1.22 seconds
Started Apr 30 12:23:15 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 195416 kb
Host smart-37c0ecc6-c561-48d2-a04f-df85bb9a28d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870246644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2870246644
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4018008645
Short name T485
Test name
Test status
Simulation time 32358435972 ps
CPU time 78.67 seconds
Started Apr 30 12:23:17 PM PDT 24
Finished Apr 30 12:24:37 PM PDT 24
Peak memory 197732 kb
Host smart-08cdc1e7-d9a5-4afc-b1b2-34699b02e1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018008645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4018008645
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2298679747
Short name T61
Test name
Test status
Simulation time 369015204590 ps
CPU time 1690.69 seconds
Started Apr 30 12:23:11 PM PDT 24
Finished Apr 30 12:51:23 PM PDT 24
Peak memory 198112 kb
Host smart-bc268745-a073-44cd-968d-ac5d9bdaa9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2298679747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2298679747
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3958154931
Short name T591
Test name
Test status
Simulation time 38533458 ps
CPU time 0.56 seconds
Started Apr 30 12:22:07 PM PDT 24
Finished Apr 30 12:22:09 PM PDT 24
Peak memory 193968 kb
Host smart-00effbfb-6e79-42ff-88c2-1fc145e74f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958154931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3958154931
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.923901726
Short name T401
Test name
Test status
Simulation time 190615177 ps
CPU time 0.88 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 195944 kb
Host smart-4bc2b6a1-23a8-4de8-bb87-0f340981590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923901726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.923901726
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1099229668
Short name T237
Test name
Test status
Simulation time 312652832 ps
CPU time 6.89 seconds
Started Apr 30 12:21:55 PM PDT 24
Finished Apr 30 12:22:03 PM PDT 24
Peak memory 197540 kb
Host smart-23cbdbd1-48ff-482d-a4d0-c1c84301f943
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099229668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1099229668
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3972290315
Short name T592
Test name
Test status
Simulation time 27031313 ps
CPU time 0.74 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 192508 kb
Host smart-5948da75-de03-4fce-a1c9-2aefabe8914b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972290315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3972290315
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2235148798
Short name T624
Test name
Test status
Simulation time 370594341 ps
CPU time 1.32 seconds
Started Apr 30 12:19:00 PM PDT 24
Finished Apr 30 12:19:02 PM PDT 24
Peak memory 196068 kb
Host smart-86f12f82-3a0e-455a-8324-d375d55df03b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235148798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2235148798
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2203000933
Short name T719
Test name
Test status
Simulation time 246380600 ps
CPU time 2.58 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 195564 kb
Host smart-e3f1d431-e565-4ae2-9ed8-fcef9acd22a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203000933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2203000933
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.635192669
Short name T219
Test name
Test status
Simulation time 235464963 ps
CPU time 3.36 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 196872 kb
Host smart-522caaff-d082-4e7c-8988-fe6965871025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635192669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.635192669
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2385621082
Short name T205
Test name
Test status
Simulation time 116918971 ps
CPU time 1.23 seconds
Started Apr 30 12:23:20 PM PDT 24
Finished Apr 30 12:23:21 PM PDT 24
Peak memory 195672 kb
Host smart-cabaef17-7669-4094-933b-8d8d8aebdcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385621082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2385621082
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3151537173
Short name T56
Test name
Test status
Simulation time 135419598 ps
CPU time 0.97 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 196588 kb
Host smart-cee56e7d-999a-42bb-91c0-09213a55bd9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151537173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3151537173
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1741885462
Short name T674
Test name
Test status
Simulation time 124280626 ps
CPU time 5.41 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 197456 kb
Host smart-0740cad0-ea2d-4400-9a4a-7a1f9c23a5c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741885462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1741885462
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1034920395
Short name T252
Test name
Test status
Simulation time 77730605 ps
CPU time 1.22 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 193616 kb
Host smart-ef6ed481-2903-41f8-8b29-295f2d920edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034920395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1034920395
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1142975543
Short name T366
Test name
Test status
Simulation time 128502960 ps
CPU time 0.79 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 195692 kb
Host smart-803045c1-ee29-4fb2-a367-baa5a29d7e55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142975543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1142975543
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1572182246
Short name T597
Test name
Test status
Simulation time 26694958386 ps
CPU time 53.99 seconds
Started Apr 30 12:21:30 PM PDT 24
Finished Apr 30 12:22:25 PM PDT 24
Peak memory 197968 kb
Host smart-cc6d11fb-90cb-48ab-b9ff-963bad3c38ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572182246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1572182246
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3432015521
Short name T448
Test name
Test status
Simulation time 21432906654 ps
CPU time 564.12 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 196580 kb
Host smart-1401b7ec-9c18-4f9e-a6dc-b05074c538b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3432015521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3432015521
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.680308042
Short name T184
Test name
Test status
Simulation time 72087601 ps
CPU time 0.54 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 193520 kb
Host smart-a043e5bf-7a04-44d6-ae5f-d2b955cb77fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680308042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.680308042
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1102579387
Short name T176
Test name
Test status
Simulation time 15286933 ps
CPU time 0.65 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:23:03 PM PDT 24
Peak memory 193868 kb
Host smart-49861ad2-d74d-46ea-a459-7b731dd73df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102579387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1102579387
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.998222212
Short name T365
Test name
Test status
Simulation time 900617578 ps
CPU time 7.97 seconds
Started Apr 30 12:21:32 PM PDT 24
Finished Apr 30 12:21:40 PM PDT 24
Peak memory 196524 kb
Host smart-20f60dc1-22fe-485e-a336-c4089039fd1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998222212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.998222212
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2418293793
Short name T377
Test name
Test status
Simulation time 44672321 ps
CPU time 0.74 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 194816 kb
Host smart-68944982-6d22-4b1e-a05f-ae027b572a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418293793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2418293793
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3152647326
Short name T693
Test name
Test status
Simulation time 34144796 ps
CPU time 1.14 seconds
Started Apr 30 12:21:55 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 196084 kb
Host smart-63122f00-76a8-4461-87a6-5cc977732f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152647326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3152647326
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2904857361
Short name T328
Test name
Test status
Simulation time 56886234 ps
CPU time 2.29 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:58 PM PDT 24
Peak memory 196188 kb
Host smart-65e1fc17-2c99-4938-8479-2dc0924a4379
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904857361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2904857361
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.221956276
Short name T397
Test name
Test status
Simulation time 527478521 ps
CPU time 2.52 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:58 PM PDT 24
Peak memory 194584 kb
Host smart-08e370a2-c052-4020-9cae-cd5cbcecbf65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221956276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.221956276
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1887277778
Short name T389
Test name
Test status
Simulation time 33517943 ps
CPU time 0.82 seconds
Started Apr 30 12:21:56 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 196188 kb
Host smart-fb08f0bb-8443-4b38-a99d-43bb1c32c37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887277778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1887277778
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3244376953
Short name T468
Test name
Test status
Simulation time 97614242 ps
CPU time 0.96 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 194804 kb
Host smart-36196103-63f6-48ab-8152-65cfdcc39fec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244376953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3244376953
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2813292689
Short name T659
Test name
Test status
Simulation time 2813033207 ps
CPU time 5.27 seconds
Started Apr 30 12:19:10 PM PDT 24
Finished Apr 30 12:19:16 PM PDT 24
Peak memory 198032 kb
Host smart-a9281c9d-e8d5-4924-a7d4-654c464a0302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813292689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2813292689
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2652223251
Short name T449
Test name
Test status
Simulation time 47463581 ps
CPU time 1.13 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 193404 kb
Host smart-9873b07b-3d53-4f0a-87c9-759331bf58fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652223251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2652223251
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.591129846
Short name T269
Test name
Test status
Simulation time 51968355 ps
CPU time 1.21 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:21:57 PM PDT 24
Peak memory 193404 kb
Host smart-1e8a5854-2882-4e7f-9e86-1a1c61b016ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591129846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.591129846
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2757593300
Short name T30
Test name
Test status
Simulation time 15347852750 ps
CPU time 202.03 seconds
Started Apr 30 12:21:20 PM PDT 24
Finished Apr 30 12:24:42 PM PDT 24
Peak memory 197856 kb
Host smart-f7dd41d2-7df0-4c4e-a79f-113351ca9f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757593300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2757593300
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2817219439
Short name T329
Test name
Test status
Simulation time 132773550535 ps
CPU time 1179.16 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:42:27 PM PDT 24
Peak memory 198008 kb
Host smart-53940f65-ad8f-4b44-a520-8362b1c677e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2817219439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2817219439
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.301447895
Short name T327
Test name
Test status
Simulation time 14468560 ps
CPU time 0.59 seconds
Started Apr 30 12:19:21 PM PDT 24
Finished Apr 30 12:19:22 PM PDT 24
Peak memory 194156 kb
Host smart-d6d8b170-0fb4-4e82-bc70-c52c232ec9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301447895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.301447895
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.220080230
Short name T217
Test name
Test status
Simulation time 37345388 ps
CPU time 0.71 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:09 PM PDT 24
Peak memory 191844 kb
Host smart-88af0bb1-8d0d-466d-aaf1-b8b1a34eb159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220080230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.220080230
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.170517997
Short name T696
Test name
Test status
Simulation time 1733148863 ps
CPU time 14.51 seconds
Started Apr 30 12:21:23 PM PDT 24
Finished Apr 30 12:21:38 PM PDT 24
Peak memory 198020 kb
Host smart-7e419580-973f-4613-9e52-ab752465a019
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170517997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.170517997
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2977878217
Short name T379
Test name
Test status
Simulation time 689686539 ps
CPU time 0.99 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 196960 kb
Host smart-88865cdf-f2df-4fd4-ae2b-a19edceaddc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977878217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2977878217
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3143705179
Short name T484
Test name
Test status
Simulation time 89114780 ps
CPU time 1.26 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 194676 kb
Host smart-95c4791a-85ac-451b-8c79-6599d27290aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143705179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3143705179
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1854671318
Short name T238
Test name
Test status
Simulation time 85180932 ps
CPU time 3.06 seconds
Started Apr 30 12:23:51 PM PDT 24
Finished Apr 30 12:23:55 PM PDT 24
Peak memory 198004 kb
Host smart-caa5ed63-c4ce-4151-854d-067c2f10b7a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854671318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1854671318
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.871510403
Short name T53
Test name
Test status
Simulation time 446689668 ps
CPU time 3.11 seconds
Started Apr 30 12:22:23 PM PDT 24
Finished Apr 30 12:22:27 PM PDT 24
Peak memory 196760 kb
Host smart-b8abc2d0-0a6a-47f7-a75e-aa9f59c2ea4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871510403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.871510403
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3214832076
Short name T319
Test name
Test status
Simulation time 21907341 ps
CPU time 0.84 seconds
Started Apr 30 12:23:51 PM PDT 24
Finished Apr 30 12:23:53 PM PDT 24
Peak memory 196400 kb
Host smart-795761b8-64b3-459e-8469-098b7c4e4bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214832076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3214832076
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2246880189
Short name T124
Test name
Test status
Simulation time 52303371 ps
CPU time 1.02 seconds
Started Apr 30 12:19:59 PM PDT 24
Finished Apr 30 12:20:00 PM PDT 24
Peak memory 195988 kb
Host smart-fd2b6bbe-de8f-4937-bb5e-4552f8085627
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246880189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2246880189
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.415255910
Short name T700
Test name
Test status
Simulation time 46129839 ps
CPU time 2.19 seconds
Started Apr 30 12:21:22 PM PDT 24
Finished Apr 30 12:21:25 PM PDT 24
Peak memory 197956 kb
Host smart-a838f3e1-a311-497d-8dc2-1faf9d55ac29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415255910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.415255910
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2682265085
Short name T374
Test name
Test status
Simulation time 31883657 ps
CPU time 0.89 seconds
Started Apr 30 12:22:44 PM PDT 24
Finished Apr 30 12:22:46 PM PDT 24
Peak memory 194516 kb
Host smart-62771051-fef2-4b81-bfda-b0e69ef3450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682265085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2682265085
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.419790118
Short name T223
Test name
Test status
Simulation time 28214307 ps
CPU time 0.82 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 195916 kb
Host smart-884837cb-6689-4d09-b9ca-5b267a6e1348
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419790118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.419790118
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1647458580
Short name T22
Test name
Test status
Simulation time 73969643784 ps
CPU time 207.6 seconds
Started Apr 30 12:21:46 PM PDT 24
Finished Apr 30 12:25:14 PM PDT 24
Peak memory 198132 kb
Host smart-ab0d0023-29da-4c74-9378-ef87c21cfb58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647458580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1647458580
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1022303370
Short name T271
Test name
Test status
Simulation time 170059688 ps
CPU time 0.54 seconds
Started Apr 30 12:22:31 PM PDT 24
Finished Apr 30 12:22:32 PM PDT 24
Peak memory 194404 kb
Host smart-1daa66f9-9c41-4879-9dc4-403a21d60d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022303370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1022303370
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4025897221
Short name T630
Test name
Test status
Simulation time 177759613 ps
CPU time 0.77 seconds
Started Apr 30 12:17:34 PM PDT 24
Finished Apr 30 12:17:35 PM PDT 24
Peak memory 195520 kb
Host smart-376a63f0-d851-46a9-9e23-608ad625b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025897221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4025897221
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2656095019
Short name T606
Test name
Test status
Simulation time 1997912981 ps
CPU time 17.91 seconds
Started Apr 30 12:17:47 PM PDT 24
Finished Apr 30 12:18:06 PM PDT 24
Peak memory 196236 kb
Host smart-1de95969-1d0f-4490-af9d-f1eb98c72427
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656095019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2656095019
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2106743773
Short name T189
Test name
Test status
Simulation time 127722428 ps
CPU time 0.88 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 195636 kb
Host smart-4bb3dd35-0305-4a30-ab43-7b9837497f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106743773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2106743773
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2421949120
Short name T564
Test name
Test status
Simulation time 110984495 ps
CPU time 1 seconds
Started Apr 30 12:17:31 PM PDT 24
Finished Apr 30 12:17:33 PM PDT 24
Peak memory 195972 kb
Host smart-1420d62c-f861-4df7-bfb4-e566b1a40a6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421949120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2421949120
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.713377914
Short name T197
Test name
Test status
Simulation time 571020052 ps
CPU time 1.51 seconds
Started Apr 30 12:17:36 PM PDT 24
Finished Apr 30 12:17:38 PM PDT 24
Peak memory 196692 kb
Host smart-3c54a559-e51e-45e2-9736-f5b8f9a7e1dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713377914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.713377914
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2852396924
Short name T385
Test name
Test status
Simulation time 288029662 ps
CPU time 2.71 seconds
Started Apr 30 12:17:31 PM PDT 24
Finished Apr 30 12:17:35 PM PDT 24
Peak memory 197216 kb
Host smart-022e91e2-33b8-4dc6-a6c7-d93539f84aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852396924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2852396924
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.772518224
Short name T261
Test name
Test status
Simulation time 111910442 ps
CPU time 1.15 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 196760 kb
Host smart-2fbfcef9-ab4b-4fd8-bc33-96e1625783be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772518224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.772518224
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1011628035
Short name T616
Test name
Test status
Simulation time 105514570 ps
CPU time 0.77 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:23:17 PM PDT 24
Peak memory 197032 kb
Host smart-f4e00ef7-5b0d-4ce0-8478-f1237f279787
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011628035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1011628035
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1079589170
Short name T476
Test name
Test status
Simulation time 442959721 ps
CPU time 5.6 seconds
Started Apr 30 12:17:33 PM PDT 24
Finished Apr 30 12:17:39 PM PDT 24
Peak memory 197840 kb
Host smart-899396e8-abc3-4b7c-a474-cbfa9c01b11f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079589170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1079589170
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2658832214
Short name T357
Test name
Test status
Simulation time 129088901 ps
CPU time 1.06 seconds
Started Apr 30 12:23:55 PM PDT 24
Finished Apr 30 12:23:57 PM PDT 24
Peak memory 195124 kb
Host smart-2b7fc195-823b-4cf3-9748-7b31286bf7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658832214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2658832214
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.250104244
Short name T457
Test name
Test status
Simulation time 61955044 ps
CPU time 1.21 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 196628 kb
Host smart-a4d5da78-7c04-45c7-831f-375fedf9ef3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250104244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.250104244
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1856800607
Short name T331
Test name
Test status
Simulation time 13108456156 ps
CPU time 179.05 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:23:43 PM PDT 24
Peak memory 198168 kb
Host smart-196c8206-ca54-4c4a-a1a7-f43103703d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856800607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1856800607
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.234686355
Short name T171
Test name
Test status
Simulation time 40231358 ps
CPU time 0.56 seconds
Started Apr 30 12:17:50 PM PDT 24
Finished Apr 30 12:17:51 PM PDT 24
Peak memory 193800 kb
Host smart-7bf09109-ef44-4bd8-bc15-503ee87ff893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234686355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.234686355
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2359554990
Short name T666
Test name
Test status
Simulation time 43361028 ps
CPU time 0.8 seconds
Started Apr 30 12:17:46 PM PDT 24
Finished Apr 30 12:17:48 PM PDT 24
Peak memory 195908 kb
Host smart-b7a85cd9-2755-44d4-8e33-ac0649e17a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359554990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2359554990
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.723143265
Short name T537
Test name
Test status
Simulation time 753978222 ps
CPU time 21.28 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:18:19 PM PDT 24
Peak memory 196756 kb
Host smart-71e85476-e80a-4f8f-8e1e-e75a444621ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723143265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.723143265
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1574220968
Short name T192
Test name
Test status
Simulation time 125363482 ps
CPU time 0.96 seconds
Started Apr 30 12:17:48 PM PDT 24
Finished Apr 30 12:17:49 PM PDT 24
Peak memory 197764 kb
Host smart-e6f43acc-6312-4d01-9f29-f17a248d64d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574220968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1574220968
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4046965648
Short name T209
Test name
Test status
Simulation time 71925545 ps
CPU time 1.24 seconds
Started Apr 30 12:18:25 PM PDT 24
Finished Apr 30 12:18:27 PM PDT 24
Peak memory 196008 kb
Host smart-34b8933e-e5ce-408c-84d6-a1cdf47bc638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046965648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4046965648
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1497906203
Short name T480
Test name
Test status
Simulation time 141471623 ps
CPU time 3.06 seconds
Started Apr 30 12:17:47 PM PDT 24
Finished Apr 30 12:17:51 PM PDT 24
Peak memory 196500 kb
Host smart-b6ba0891-8e99-4df8-a8f9-06ca0f84fbc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497906203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1497906203
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1977674363
Short name T125
Test name
Test status
Simulation time 47395794 ps
CPU time 1.04 seconds
Started Apr 30 12:17:39 PM PDT 24
Finished Apr 30 12:17:41 PM PDT 24
Peak memory 195876 kb
Host smart-4d308a1a-4431-4c52-9e46-4a39bf8b7099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977674363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1977674363
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1239720282
Short name T466
Test name
Test status
Simulation time 245310557 ps
CPU time 1.06 seconds
Started Apr 30 12:17:47 PM PDT 24
Finished Apr 30 12:17:49 PM PDT 24
Peak memory 195768 kb
Host smart-8935e301-d8da-4360-820b-049badaad56d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239720282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1239720282
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.903540005
Short name T435
Test name
Test status
Simulation time 1322257799 ps
CPU time 6.01 seconds
Started Apr 30 12:17:57 PM PDT 24
Finished Apr 30 12:18:04 PM PDT 24
Peak memory 197920 kb
Host smart-5e8f5848-b34b-4d4c-a89d-82172e737d1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903540005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.903540005
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1459301621
Short name T146
Test name
Test status
Simulation time 166139709 ps
CPU time 0.83 seconds
Started Apr 30 12:17:38 PM PDT 24
Finished Apr 30 12:17:40 PM PDT 24
Peak memory 195192 kb
Host smart-ead5103d-eaa3-489a-88d3-fbbb7019a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459301621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1459301621
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3313920144
Short name T280
Test name
Test status
Simulation time 43636762 ps
CPU time 1.21 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:13 PM PDT 24
Peak memory 195908 kb
Host smart-529edbbb-c1fa-46f8-9d80-3321a6faaad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313920144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3313920144
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3436042544
Short name T634
Test name
Test status
Simulation time 48246117210 ps
CPU time 208.71 seconds
Started Apr 30 12:17:48 PM PDT 24
Finished Apr 30 12:21:17 PM PDT 24
Peak memory 197848 kb
Host smart-58f2506b-e8be-4752-8fa3-273223f19261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436042544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3436042544
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.642962
Short name T865
Test name
Test status
Simulation time 572501406 ps
CPU time 1.48 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 195708 kb
Host smart-f155e554-d26c-4668-9fa1-9994ee7d8173
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=642962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.642962
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2995163216
Short name T890
Test name
Test status
Simulation time 89578845 ps
CPU time 1.56 seconds
Started Apr 30 12:30:17 PM PDT 24
Finished Apr 30 12:30:19 PM PDT 24
Peak memory 196724 kb
Host smart-efe342b3-cb61-4fcb-b1f8-ed256522550c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995163216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2995163216
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1296681109
Short name T936
Test name
Test status
Simulation time 138008663 ps
CPU time 1.2 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 196484 kb
Host smart-9cd99e1c-66e3-4b73-9fbe-79f3f3c03531
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1296681109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1296681109
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743057897
Short name T918
Test name
Test status
Simulation time 51988252 ps
CPU time 1.37 seconds
Started Apr 30 12:30:23 PM PDT 24
Finished Apr 30 12:30:25 PM PDT 24
Peak memory 197828 kb
Host smart-c3d3cf3b-a8be-4b44-9e93-25b0de276c18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743057897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.743057897
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3189958268
Short name T908
Test name
Test status
Simulation time 71477567 ps
CPU time 1.25 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:22 PM PDT 24
Peak memory 195892 kb
Host smart-16d20f56-d73c-445e-b766-5dbbe019538c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3189958268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3189958268
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701384553
Short name T851
Test name
Test status
Simulation time 211766869 ps
CPU time 1.39 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:22 PM PDT 24
Peak memory 196768 kb
Host smart-3680b3d0-d5dd-4ace-b51c-bc36dfaea44a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701384553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3701384553
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1525866619
Short name T872
Test name
Test status
Simulation time 93769780 ps
CPU time 1.31 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 196908 kb
Host smart-e7626b6c-d998-46b3-b4cf-80556d223246
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1525866619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1525866619
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3368545402
Short name T924
Test name
Test status
Simulation time 74256310 ps
CPU time 1.2 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:37 PM PDT 24
Peak memory 196100 kb
Host smart-bfe0c8db-cc64-4cc7-af02-88fa8ae1aa8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368545402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3368545402
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1754521871
Short name T911
Test name
Test status
Simulation time 66164045 ps
CPU time 0.85 seconds
Started Apr 30 12:30:19 PM PDT 24
Finished Apr 30 12:30:20 PM PDT 24
Peak memory 195520 kb
Host smart-c145e7d9-3bab-4e17-9a6a-63e9543cb404
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1754521871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1754521871
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1135669727
Short name T869
Test name
Test status
Simulation time 111684494 ps
CPU time 1.12 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:32 PM PDT 24
Peak memory 196808 kb
Host smart-f0fc6169-1b30-4fc4-8a92-43c2a00c0a77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135669727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1135669727
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2973401153
Short name T887
Test name
Test status
Simulation time 32741674 ps
CPU time 1.01 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:34 PM PDT 24
Peak memory 196808 kb
Host smart-23a336ca-bb4a-4a13-935b-636888efc2f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2973401153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2973401153
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664955264
Short name T916
Test name
Test status
Simulation time 118747169 ps
CPU time 0.97 seconds
Started Apr 30 12:30:39 PM PDT 24
Finished Apr 30 12:30:41 PM PDT 24
Peak memory 196680 kb
Host smart-c67a9594-d6db-4c53-8efe-6554a79cec49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664955264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2664955264
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2540538486
Short name T854
Test name
Test status
Simulation time 189766840 ps
CPU time 1.35 seconds
Started Apr 30 12:30:19 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 198168 kb
Host smart-34e32cb6-b940-4920-b60d-bd26e426a902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2540538486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2540538486
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.732303186
Short name T931
Test name
Test status
Simulation time 101068736 ps
CPU time 1.19 seconds
Started Apr 30 12:30:18 PM PDT 24
Finished Apr 30 12:30:19 PM PDT 24
Peak memory 195888 kb
Host smart-9e8e9876-8c66-422d-8480-b3ca9a68756f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732303186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.732303186
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3445016186
Short name T907
Test name
Test status
Simulation time 379375093 ps
CPU time 1.41 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:22 PM PDT 24
Peak memory 196584 kb
Host smart-b61f4887-09eb-4797-8477-9f236164f7b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3445016186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3445016186
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1089229715
Short name T920
Test name
Test status
Simulation time 45931435 ps
CPU time 1.32 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 198048 kb
Host smart-e17968f3-5abf-4326-8580-a1a787de28ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089229715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1089229715
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1126527346
Short name T904
Test name
Test status
Simulation time 168041410 ps
CPU time 1.13 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:32 PM PDT 24
Peak memory 198112 kb
Host smart-b54bcfa3-f288-49e6-b325-f5fae70c2241
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1126527346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1126527346
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3113474049
Short name T934
Test name
Test status
Simulation time 56111526 ps
CPU time 1.14 seconds
Started Apr 30 12:30:23 PM PDT 24
Finished Apr 30 12:30:25 PM PDT 24
Peak memory 198024 kb
Host smart-1a9ebc08-38d7-4c70-a678-e3b2b0876f59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113474049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3113474049
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4103326225
Short name T939
Test name
Test status
Simulation time 82105528 ps
CPU time 0.73 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 194444 kb
Host smart-dc331dbd-9746-494e-a8e5-c914a1a6da39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4103326225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4103326225
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1397261030
Short name T941
Test name
Test status
Simulation time 422610580 ps
CPU time 1.4 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:22 PM PDT 24
Peak memory 196840 kb
Host smart-98daeaf4-b73c-4742-bcc4-c13258803031
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397261030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1397261030
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2394737959
Short name T895
Test name
Test status
Simulation time 95301139 ps
CPU time 1.08 seconds
Started Apr 30 12:30:22 PM PDT 24
Finished Apr 30 12:30:24 PM PDT 24
Peak memory 196820 kb
Host smart-3e71622d-edd1-4eb6-8324-e64206caa736
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2394737959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2394737959
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509040635
Short name T913
Test name
Test status
Simulation time 34845496 ps
CPU time 0.87 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:42 PM PDT 24
Peak memory 196740 kb
Host smart-c5bec352-4c78-4055-9540-6ba1d58c2a83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509040635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.509040635
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2172356172
Short name T871
Test name
Test status
Simulation time 43469754 ps
CPU time 0.95 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:36 PM PDT 24
Peak memory 196608 kb
Host smart-dede3005-9009-4092-8c0b-6df21738ebfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2172356172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2172356172
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.146980489
Short name T849
Test name
Test status
Simulation time 37195782 ps
CPU time 1.03 seconds
Started Apr 30 12:30:22 PM PDT 24
Finished Apr 30 12:30:24 PM PDT 24
Peak memory 197000 kb
Host smart-121dab70-0359-46b3-af12-5d48fb6ff0dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146980489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.146980489
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1383821762
Short name T886
Test name
Test status
Simulation time 141363689 ps
CPU time 1.04 seconds
Started Apr 30 12:30:11 PM PDT 24
Finished Apr 30 12:30:13 PM PDT 24
Peak memory 195704 kb
Host smart-89b172b1-6798-4277-a8fe-c9462d23ec27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1383821762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1383821762
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2156073245
Short name T855
Test name
Test status
Simulation time 52413284 ps
CPU time 1.02 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 196764 kb
Host smart-a44728eb-ae29-4fed-86cc-f0e305a6f663
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156073245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2156073245
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4234103198
Short name T923
Test name
Test status
Simulation time 180889245 ps
CPU time 1.08 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 196584 kb
Host smart-3a1915d4-8442-41b4-ba63-8dbae02520f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4234103198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4234103198
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426267649
Short name T863
Test name
Test status
Simulation time 155180426 ps
CPU time 1.22 seconds
Started Apr 30 12:30:19 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 196960 kb
Host smart-d780bf73-0940-4fa3-a120-38bb7a0f31ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426267649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2426267649
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3515273030
Short name T930
Test name
Test status
Simulation time 107569734 ps
CPU time 0.89 seconds
Started Apr 30 12:30:28 PM PDT 24
Finished Apr 30 12:30:29 PM PDT 24
Peak memory 195728 kb
Host smart-85461694-2752-4ee9-ad02-7f163a9d00b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3515273030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3515273030
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2767214333
Short name T862
Test name
Test status
Simulation time 233083987 ps
CPU time 1.1 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 196568 kb
Host smart-1c59d47b-4d8b-4235-8be7-4ba0debf5f6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767214333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2767214333
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3474968403
Short name T889
Test name
Test status
Simulation time 129017913 ps
CPU time 1.17 seconds
Started Apr 30 12:30:21 PM PDT 24
Finished Apr 30 12:30:22 PM PDT 24
Peak memory 196432 kb
Host smart-496d7cb6-1ed1-4ae9-ac95-d06ebc81c86e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3474968403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3474968403
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864856616
Short name T844
Test name
Test status
Simulation time 128388418 ps
CPU time 1.04 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:37 PM PDT 24
Peak memory 196620 kb
Host smart-e3de4055-3a95-4737-8e62-62bab1c1f71d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864856616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3864856616
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2186445184
Short name T900
Test name
Test status
Simulation time 51949176 ps
CPU time 1.06 seconds
Started Apr 30 12:30:21 PM PDT 24
Finished Apr 30 12:30:23 PM PDT 24
Peak memory 195896 kb
Host smart-7e06b32f-e792-4c58-9c66-39d3b2ae695b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2186445184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2186445184
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3403829763
Short name T901
Test name
Test status
Simulation time 67639401 ps
CPU time 1.11 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:44 PM PDT 24
Peak memory 197604 kb
Host smart-5625e2c4-9e88-472a-8be8-a7652eb1e014
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403829763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3403829763
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1859918927
Short name T850
Test name
Test status
Simulation time 74954618 ps
CPU time 1.2 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 195980 kb
Host smart-c1b8139a-219c-4fce-9185-40b8719ba3ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1859918927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1859918927
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503508481
Short name T859
Test name
Test status
Simulation time 454143554 ps
CPU time 1.25 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:33 PM PDT 24
Peak memory 197752 kb
Host smart-82b50f14-befd-4b4c-998c-579230272c11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503508481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2503508481
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3599796762
Short name T866
Test name
Test status
Simulation time 306895045 ps
CPU time 1.41 seconds
Started Apr 30 12:30:21 PM PDT 24
Finished Apr 30 12:30:23 PM PDT 24
Peak memory 196652 kb
Host smart-47e73424-5ab9-4d3e-844a-e8041d10be1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3599796762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3599796762
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1350419788
Short name T897
Test name
Test status
Simulation time 315527344 ps
CPU time 0.89 seconds
Started Apr 30 12:30:19 PM PDT 24
Finished Apr 30 12:30:20 PM PDT 24
Peak memory 195572 kb
Host smart-702ed64f-d7a8-48be-83ef-0f742d0e895f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350419788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1350419788
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1646528922
Short name T921
Test name
Test status
Simulation time 89655113 ps
CPU time 1.25 seconds
Started Apr 30 12:30:22 PM PDT 24
Finished Apr 30 12:30:23 PM PDT 24
Peak memory 198144 kb
Host smart-e166b174-c887-43d8-bb02-5534c4216e51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1646528922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1646528922
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1959519947
Short name T928
Test name
Test status
Simulation time 94021135 ps
CPU time 0.94 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:36 PM PDT 24
Peak memory 196608 kb
Host smart-85e75c63-8afb-47f1-b256-42841b0dbd3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959519947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1959519947
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.579434516
Short name T906
Test name
Test status
Simulation time 55452339 ps
CPU time 1.09 seconds
Started Apr 30 12:30:20 PM PDT 24
Finished Apr 30 12:30:21 PM PDT 24
Peak memory 196484 kb
Host smart-dc6f58ff-63d4-42ba-9e84-7f0d44189b84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=579434516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.579434516
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2691299034
Short name T864
Test name
Test status
Simulation time 419044736 ps
CPU time 1.03 seconds
Started Apr 30 12:30:24 PM PDT 24
Finished Apr 30 12:30:25 PM PDT 24
Peak memory 196476 kb
Host smart-cf3fa37b-cb39-4067-8eab-505e67f22b49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691299034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2691299034
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2062520705
Short name T905
Test name
Test status
Simulation time 55924349 ps
CPU time 1.02 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:32 PM PDT 24
Peak memory 196596 kb
Host smart-09b5a19e-4f7a-4d6b-be49-74435f8405b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2062520705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2062520705
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2427000562
Short name T845
Test name
Test status
Simulation time 186239262 ps
CPU time 1.2 seconds
Started Apr 30 12:30:37 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 196648 kb
Host smart-03461d83-d855-407e-a664-2e620ff1980a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427000562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2427000562
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.211693588
Short name T942
Test name
Test status
Simulation time 46454629 ps
CPU time 1.23 seconds
Started Apr 30 12:30:29 PM PDT 24
Finished Apr 30 12:30:31 PM PDT 24
Peak memory 197088 kb
Host smart-6d33b6fa-cf34-48f9-8f1b-5e142aea6c2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=211693588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.211693588
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316568459
Short name T868
Test name
Test status
Simulation time 55204655 ps
CPU time 1.09 seconds
Started Apr 30 12:30:34 PM PDT 24
Finished Apr 30 12:30:36 PM PDT 24
Peak memory 196904 kb
Host smart-3ddf9f1c-fc37-41b9-a117-07199ce85f28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316568459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.316568459
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.456213257
Short name T909
Test name
Test status
Simulation time 75527295 ps
CPU time 1.23 seconds
Started Apr 30 12:30:23 PM PDT 24
Finished Apr 30 12:30:25 PM PDT 24
Peak memory 196760 kb
Host smart-a6226244-a755-4dbf-a2e9-97703bff5dd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=456213257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.456213257
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4110962187
Short name T929
Test name
Test status
Simulation time 874704334 ps
CPU time 1.26 seconds
Started Apr 30 12:30:10 PM PDT 24
Finished Apr 30 12:30:12 PM PDT 24
Peak memory 196636 kb
Host smart-53de54f8-0f2a-422e-8623-dcb1128a1483
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110962187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4110962187
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.462025084
Short name T938
Test name
Test status
Simulation time 95817215 ps
CPU time 1.03 seconds
Started Apr 30 12:30:30 PM PDT 24
Finished Apr 30 12:30:31 PM PDT 24
Peak memory 196684 kb
Host smart-263edce9-eb11-48e0-ba5a-a86cc41681eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=462025084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.462025084
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3517382351
Short name T853
Test name
Test status
Simulation time 68264700 ps
CPU time 1.33 seconds
Started Apr 30 12:30:43 PM PDT 24
Finished Apr 30 12:30:45 PM PDT 24
Peak memory 195732 kb
Host smart-f9e1a167-f62a-4fa6-a72d-2cc9988a1f60
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517382351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3517382351
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.812761868
Short name T883
Test name
Test status
Simulation time 175027086 ps
CPU time 0.91 seconds
Started Apr 30 12:30:30 PM PDT 24
Finished Apr 30 12:30:31 PM PDT 24
Peak memory 196800 kb
Host smart-8ca5e037-6c23-4452-9e9c-1a787e84f557
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=812761868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.812761868
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.606147517
Short name T873
Test name
Test status
Simulation time 39273631 ps
CPU time 1 seconds
Started Apr 30 12:30:32 PM PDT 24
Finished Apr 30 12:30:34 PM PDT 24
Peak memory 196652 kb
Host smart-85fc4eec-8dbe-4524-bba9-1455f40fc0a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606147517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.606147517
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.930781384
Short name T893
Test name
Test status
Simulation time 95363592 ps
CPU time 0.84 seconds
Started Apr 30 12:30:29 PM PDT 24
Finished Apr 30 12:30:30 PM PDT 24
Peak memory 195652 kb
Host smart-f3eee8fd-addc-4105-be51-5e60124446d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=930781384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.930781384
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867719924
Short name T922
Test name
Test status
Simulation time 38189425 ps
CPU time 0.87 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:42 PM PDT 24
Peak memory 195432 kb
Host smart-e94dcc8a-58b4-45de-b08c-1aff526e2d25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867719924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1867719924
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3570887933
Short name T899
Test name
Test status
Simulation time 26841438 ps
CPU time 0.91 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:36 PM PDT 24
Peak memory 195412 kb
Host smart-0a94fb09-8b8d-4d1f-951c-2b3f25d79b64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3570887933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3570887933
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577115912
Short name T903
Test name
Test status
Simulation time 94491713 ps
CPU time 1.48 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:33 PM PDT 24
Peak memory 196856 kb
Host smart-f1715f94-6cfa-49c5-a840-f4d3862687f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577115912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3577115912
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2602377562
Short name T940
Test name
Test status
Simulation time 91077174 ps
CPU time 1.02 seconds
Started Apr 30 12:30:27 PM PDT 24
Finished Apr 30 12:30:28 PM PDT 24
Peak memory 196628 kb
Host smart-c7d9aa7b-fd81-4a94-9a99-e2d5d4ad6c68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2602377562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2602377562
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1888836380
Short name T935
Test name
Test status
Simulation time 102253802 ps
CPU time 0.99 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 196808 kb
Host smart-fe7ce4e4-ae8a-4d0b-934d-919709363b46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888836380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1888836380
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1164640453
Short name T914
Test name
Test status
Simulation time 238308723 ps
CPU time 1.08 seconds
Started Apr 30 12:30:26 PM PDT 24
Finished Apr 30 12:30:28 PM PDT 24
Peak memory 198048 kb
Host smart-73d288fc-a0fd-457a-b982-3d6ffa4e990d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1164640453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1164640453
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700007346
Short name T917
Test name
Test status
Simulation time 93484326 ps
CPU time 1.2 seconds
Started Apr 30 12:30:37 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 195716 kb
Host smart-cb1b45d7-82d7-4407-8eb1-fe49631b3775
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700007346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2700007346
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1348086445
Short name T852
Test name
Test status
Simulation time 68098629 ps
CPU time 1.01 seconds
Started Apr 30 12:30:34 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 196832 kb
Host smart-96d9804d-4aa1-48e6-8561-fdea5dde5683
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1348086445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1348086445
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3670616101
Short name T875
Test name
Test status
Simulation time 37647106 ps
CPU time 1.03 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:37 PM PDT 24
Peak memory 195960 kb
Host smart-6eb0b430-a23d-401c-955f-6cb2fd7960e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670616101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3670616101
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.255383312
Short name T857
Test name
Test status
Simulation time 48906217 ps
CPU time 1.16 seconds
Started Apr 30 12:30:37 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 198132 kb
Host smart-9b40015c-487a-4692-8f89-12a4a8d1f902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=255383312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.255383312
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2881455705
Short name T937
Test name
Test status
Simulation time 82939368 ps
CPU time 1.23 seconds
Started Apr 30 12:30:27 PM PDT 24
Finished Apr 30 12:30:28 PM PDT 24
Peak memory 196868 kb
Host smart-c72cac62-9c46-413b-8073-e8d10f42e31a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881455705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2881455705
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4131144820
Short name T881
Test name
Test status
Simulation time 204131757 ps
CPU time 1.03 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:42 PM PDT 24
Peak memory 196608 kb
Host smart-75ede76f-d183-4c8d-b9ac-85853b55fbd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4131144820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4131144820
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2114567483
Short name T882
Test name
Test status
Simulation time 81100688 ps
CPU time 0.84 seconds
Started Apr 30 12:30:30 PM PDT 24
Finished Apr 30 12:30:32 PM PDT 24
Peak memory 196124 kb
Host smart-c284a22d-7ebc-46ea-9dbd-38459fea6b38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114567483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2114567483
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1601562408
Short name T925
Test name
Test status
Simulation time 380755234 ps
CPU time 1.32 seconds
Started Apr 30 12:30:28 PM PDT 24
Finished Apr 30 12:30:30 PM PDT 24
Peak memory 195672 kb
Host smart-daa43236-b704-4c26-ad64-2e121cc76ef8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1601562408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1601562408
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408090028
Short name T870
Test name
Test status
Simulation time 35353495 ps
CPU time 0.95 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 196804 kb
Host smart-e2b6105f-6ce8-4694-9d06-04571c13291f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408090028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1408090028
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4195913662
Short name T861
Test name
Test status
Simulation time 77819796 ps
CPU time 1.14 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:18 PM PDT 24
Peak memory 195700 kb
Host smart-fc3ec0e0-aebc-419d-9a66-9fc61680d9e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4195913662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4195913662
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951152783
Short name T932
Test name
Test status
Simulation time 34131417 ps
CPU time 0.7 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:17 PM PDT 24
Peak memory 195416 kb
Host smart-c3815b45-a38e-454d-af62-e5ec62ecd489
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951152783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3951152783
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4099075597
Short name T884
Test name
Test status
Simulation time 79281124 ps
CPU time 0.69 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 194448 kb
Host smart-4f3c145d-4808-4ebe-8112-c7bc3b6e4209
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4099075597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4099075597
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.96637116
Short name T874
Test name
Test status
Simulation time 146191517 ps
CPU time 1.1 seconds
Started Apr 30 12:30:32 PM PDT 24
Finished Apr 30 12:30:34 PM PDT 24
Peak memory 195912 kb
Host smart-1c5859cd-402a-4564-ac8d-c2326d0a4d54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96637116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.96637116
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4254499269
Short name T880
Test name
Test status
Simulation time 308253682 ps
CPU time 0.88 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 196556 kb
Host smart-8e8ea3b2-535a-4c12-87de-6ed37cef9da7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4254499269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4254499269
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3038981940
Short name T902
Test name
Test status
Simulation time 167057780 ps
CPU time 1.5 seconds
Started Apr 30 12:30:35 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 198472 kb
Host smart-81fd5c2a-4c0e-473c-9c0e-a5994dfc6c5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038981940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3038981940
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3959728105
Short name T876
Test name
Test status
Simulation time 164888629 ps
CPU time 1.16 seconds
Started Apr 30 12:30:28 PM PDT 24
Finished Apr 30 12:30:29 PM PDT 24
Peak memory 195728 kb
Host smart-51467426-a8da-4c34-9146-17fb8b57dcd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3959728105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3959728105
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3363114636
Short name T927
Test name
Test status
Simulation time 64458643 ps
CPU time 1.24 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 197192 kb
Host smart-46a9f7db-02bf-477c-96a4-03381302df11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363114636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3363114636
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3390335909
Short name T856
Test name
Test status
Simulation time 78037260 ps
CPU time 0.98 seconds
Started Apr 30 12:30:29 PM PDT 24
Finished Apr 30 12:30:31 PM PDT 24
Peak memory 196624 kb
Host smart-fd6d1962-8e1f-4b09-802f-6d01ce94f367
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3390335909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3390335909
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1927156148
Short name T910
Test name
Test status
Simulation time 228816643 ps
CPU time 1.09 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 198184 kb
Host smart-a893e524-a366-4e51-8548-76c9796aa494
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927156148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1927156148
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2791843342
Short name T879
Test name
Test status
Simulation time 358776676 ps
CPU time 1.42 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 196820 kb
Host smart-8e5d6948-b10f-40a9-a158-dfbbb0f4aeae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2791843342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2791843342
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23385163
Short name T848
Test name
Test status
Simulation time 77414204 ps
CPU time 1.39 seconds
Started Apr 30 12:30:25 PM PDT 24
Finished Apr 30 12:30:27 PM PDT 24
Peak memory 196856 kb
Host smart-b1aad8b2-9d2c-4f0c-97c1-8a60c77e8b14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.23385163
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2384098979
Short name T858
Test name
Test status
Simulation time 57374483 ps
CPU time 0.95 seconds
Started Apr 30 12:30:29 PM PDT 24
Finished Apr 30 12:30:31 PM PDT 24
Peak memory 196476 kb
Host smart-d0056b51-5355-46b4-b173-4dc53eb2c46f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2384098979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2384098979
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3405436550
Short name T912
Test name
Test status
Simulation time 68755933 ps
CPU time 1.3 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 198120 kb
Host smart-16e44dfb-b869-4929-969d-56656e2cd6be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405436550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3405436550
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1786490418
Short name T933
Test name
Test status
Simulation time 56451294 ps
CPU time 1.07 seconds
Started Apr 30 12:30:32 PM PDT 24
Finished Apr 30 12:30:34 PM PDT 24
Peak memory 196532 kb
Host smart-5fc265a5-7963-42dd-9bd0-ffa99d887728
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1786490418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1786490418
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1989808373
Short name T888
Test name
Test status
Simulation time 1077456258 ps
CPU time 1.27 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 196772 kb
Host smart-3c130833-3bf0-4864-ab88-d13bb87646f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989808373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1989808373
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2127259440
Short name T867
Test name
Test status
Simulation time 157880494 ps
CPU time 1.27 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:35 PM PDT 24
Peak memory 195868 kb
Host smart-7a4e6e16-739f-4d66-9d99-6e2ee69dce93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2127259440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2127259440
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353273828
Short name T860
Test name
Test status
Simulation time 1419262121 ps
CPU time 1.33 seconds
Started Apr 30 12:30:38 PM PDT 24
Finished Apr 30 12:30:40 PM PDT 24
Peak memory 196944 kb
Host smart-30556026-8cf8-4150-80a1-378b4362e3f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353273828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2353273828
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3539530830
Short name T898
Test name
Test status
Simulation time 98301872 ps
CPU time 0.94 seconds
Started Apr 30 12:30:28 PM PDT 24
Finished Apr 30 12:30:29 PM PDT 24
Peak memory 196188 kb
Host smart-8bc5ba14-591a-4ff7-82b6-55cfa798a778
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3539530830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3539530830
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623320825
Short name T891
Test name
Test status
Simulation time 183270322 ps
CPU time 1.13 seconds
Started Apr 30 12:30:28 PM PDT 24
Finished Apr 30 12:30:29 PM PDT 24
Peak memory 195628 kb
Host smart-66acad74-3635-4e10-942b-619195cc5e4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623320825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.623320825
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3657220247
Short name T847
Test name
Test status
Simulation time 197390861 ps
CPU time 1.29 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 196848 kb
Host smart-4858ed36-ff3d-4af0-b81b-bc72d0975f99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3657220247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3657220247
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1820616851
Short name T843
Test name
Test status
Simulation time 90291766 ps
CPU time 0.88 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:33 PM PDT 24
Peak memory 195480 kb
Host smart-40c03675-1417-467e-bf31-142b39264d83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820616851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1820616851
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2869986461
Short name T896
Test name
Test status
Simulation time 63973369 ps
CPU time 1.14 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 196588 kb
Host smart-432598e3-0946-46e0-a996-f9b3f83bb310
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2869986461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2869986461
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864447845
Short name T877
Test name
Test status
Simulation time 177501964 ps
CPU time 1.44 seconds
Started Apr 30 12:30:12 PM PDT 24
Finished Apr 30 12:30:14 PM PDT 24
Peak memory 198104 kb
Host smart-b3efc38e-6ccf-432b-834d-db08c41407fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864447845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3864447845
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1688934811
Short name T894
Test name
Test status
Simulation time 105852264 ps
CPU time 1.34 seconds
Started Apr 30 12:30:15 PM PDT 24
Finished Apr 30 12:30:17 PM PDT 24
Peak memory 196888 kb
Host smart-7efe1e92-7b65-4e69-a87c-bf6b8f86d12e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1688934811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1688934811
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1804761106
Short name T878
Test name
Test status
Simulation time 149636278 ps
CPU time 1.18 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:18 PM PDT 24
Peak memory 196708 kb
Host smart-5a5924f3-1c76-4d8e-bc43-1133eb8fedba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804761106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1804761106
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2893237441
Short name T846
Test name
Test status
Simulation time 65431457 ps
CPU time 1.09 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:18 PM PDT 24
Peak memory 196796 kb
Host smart-e588bee7-ef62-4bcf-a004-083a84c38e86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2893237441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2893237441
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1537728477
Short name T915
Test name
Test status
Simulation time 82950518 ps
CPU time 1.15 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 196612 kb
Host smart-65c3d44d-699f-46f3-8ece-b8b22f15fbd1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537728477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1537728477
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.196482595
Short name T892
Test name
Test status
Simulation time 476493974 ps
CPU time 1.35 seconds
Started Apr 30 12:30:24 PM PDT 24
Finished Apr 30 12:30:26 PM PDT 24
Peak memory 197020 kb
Host smart-76dc6d10-6a90-46ec-b403-1751923c21a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=196482595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.196482595
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3115091077
Short name T885
Test name
Test status
Simulation time 274719907 ps
CPU time 1.1 seconds
Started Apr 30 12:30:09 PM PDT 24
Finished Apr 30 12:30:11 PM PDT 24
Peak memory 195632 kb
Host smart-9f50aba5-3c0c-4e15-9540-e290ce529fd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115091077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3115091077
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1103841412
Short name T919
Test name
Test status
Simulation time 44726519 ps
CPU time 1.05 seconds
Started Apr 30 12:30:16 PM PDT 24
Finished Apr 30 12:30:17 PM PDT 24
Peak memory 197448 kb
Host smart-978c4363-2acd-43bf-895f-2a545ca06bda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103841412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1103841412
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1083198012
Short name T926
Test name
Test status
Simulation time 51479089 ps
CPU time 0.96 seconds
Started Apr 30 12:30:22 PM PDT 24
Finished Apr 30 12:30:24 PM PDT 24
Peak memory 196672 kb
Host smart-eb2a26a3-b4e7-441d-81f0-34d6d1a47703
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083198012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1083198012
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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