Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3981884	1			T24	1		T25	60		T26	1
all_pins[1]	3981884	1			T24	1		T25	60		T26	1
all_pins[2]	3981884	1			T24	1		T25	60		T26	1
all_pins[3]	3981884	1			T24	1		T25	60		T26	1
all_pins[4]	3981884	1			T24	1		T25	60		T26	1
all_pins[5]	3981884	1			T24	1		T25	60		T26	1
all_pins[6]	3981884	1			T24	1		T25	60		T26	1
all_pins[7]	3981884	1			T24	1		T25	60		T26	1
all_pins[8]	3981884	1			T24	1		T25	60		T26	1
all_pins[9]	3981884	1			T24	1		T25	60		T26	1
all_pins[10]	3981884	1			T24	1		T25	60		T26	1
all_pins[11]	3981884	1			T24	1		T25	60		T26	1
all_pins[12]	3981884	1			T24	1		T25	60		T26	1
all_pins[13]	3981884	1			T24	1		T25	60		T26	1
all_pins[14]	3981884	1			T24	1		T25	60		T26	1
all_pins[15]	3981884	1			T24	1		T25	60		T26	1
all_pins[16]	3981884	1			T24	1		T25	60		T26	1
all_pins[17]	3981884	1			T24	1		T25	60		T26	1
all_pins[18]	3981884	1			T24	1		T25	60		T26	1
all_pins[19]	3981884	1			T24	1		T25	60		T26	1
all_pins[20]	3981884	1			T24	1		T25	60		T26	1
all_pins[21]	3981884	1			T24	1		T25	60		T26	1
all_pins[22]	3981884	1			T24	1		T25	60		T26	1
all_pins[23]	3981884	1			T24	1		T25	60		T26	1
all_pins[24]	3981884	1			T24	1		T25	60		T26	1
all_pins[25]	3981884	1			T24	1		T25	60		T26	1
all_pins[26]	3981884	1			T24	1		T25	60		T26	1
all_pins[27]	3981884	1			T24	1		T25	60		T26	1
all_pins[28]	3981884	1			T24	1		T25	60		T26	1
all_pins[29]	3981884	1			T24	1		T25	60		T26	1
all_pins[30]	3981884	1			T24	1		T25	60		T26	1
all_pins[31]	3981884	1			T24	1		T25	60		T26	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	79138025	1			T24	32		T25	996		T26	32
values[0x1]	48282263	1			T25	924		T1	326765		T13	664
transitions[0x0=>0x1]	28916685	1			T25	475		T1	195137		T13	372
transitions[0x1=>0x0]	28916532	1			T25	475		T1	195136		T13	371

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2466882	1			T24	1		T25	35		T26	1
all_pins[0]	values[0x1]	1515002	1			T25	25		T1	10073		T13	24
all_pins[0]	transitions[0x0=>0x1]	938150	1			T25	13		T1	6390		T13	15
all_pins[0]	transitions[0x1=>0x0]	928326	1			T25	19		T1	6618		T13	8
all_pins[1]	values[0x0]	2475193	1			T24	1		T25	23		T26	1
all_pins[1]	values[0x1]	1506691	1			T25	37		T1	10192		T13	23
all_pins[1]	transitions[0x0=>0x1]	898894	1			T25	25		T1	6178		T13	15
all_pins[1]	transitions[0x1=>0x0]	907205	1			T25	13		T1	6059		T13	16
all_pins[2]	values[0x0]	2473281	1			T24	1		T25	29		T26	1
all_pins[2]	values[0x1]	1508603	1			T25	31		T1	10620		T13	15
all_pins[2]	transitions[0x0=>0x1]	903112	1			T25	15		T1	6217		T13	9
all_pins[2]	transitions[0x1=>0x0]	901200	1			T25	21		T1	5789		T13	17
all_pins[3]	values[0x0]	2473846	1			T24	1		T25	33		T26	1
all_pins[3]	values[0x1]	1508038	1			T25	27		T1	10364		T13	17
all_pins[3]	transitions[0x0=>0x1]	901152	1			T25	11		T1	6119		T13	13
all_pins[3]	transitions[0x1=>0x0]	901717	1			T25	15		T1	6375		T13	11
all_pins[4]	values[0x0]	2473868	1			T24	1		T25	26		T26	1
all_pins[4]	values[0x1]	1508016	1			T25	34		T1	10099		T13	30
all_pins[4]	transitions[0x0=>0x1]	900312	1			T25	19		T1	5875		T13	19
all_pins[4]	transitions[0x1=>0x0]	900334	1			T25	12		T1	6140		T13	6
all_pins[5]	values[0x0]	2472812	1			T24	1		T25	40		T26	1
all_pins[5]	values[0x1]	1509072	1			T25	20		T1	10389		T13	22
all_pins[5]	transitions[0x0=>0x1]	903569	1			T25	7		T1	6334		T13	5
all_pins[5]	transitions[0x1=>0x0]	902513	1			T25	21		T1	6044		T13	13
all_pins[6]	values[0x0]	2475368	1			T24	1		T25	36		T26	1
all_pins[6]	values[0x1]	1506516	1			T25	24		T1	10289		T13	27
all_pins[6]	transitions[0x0=>0x1]	901538	1			T25	16		T1	6111		T13	20
all_pins[6]	transitions[0x1=>0x0]	904094	1			T25	12		T1	6211		T13	15
all_pins[7]	values[0x0]	2470279	1			T24	1		T25	30		T26	1
all_pins[7]	values[0x1]	1511605	1			T25	30		T1	10461		T13	23
all_pins[7]	transitions[0x0=>0x1]	905750	1			T25	17		T1	6198		T13	13
all_pins[7]	transitions[0x1=>0x0]	900661	1			T25	11		T1	6026		T13	17
all_pins[8]	values[0x0]	2478024	1			T24	1		T25	33		T26	1
all_pins[8]	values[0x1]	1503860	1			T25	27		T1	10001		T13	17
all_pins[8]	transitions[0x0=>0x1]	898668	1			T25	14		T1	5745		T13	8
all_pins[8]	transitions[0x1=>0x0]	906413	1			T25	17		T1	6205		T13	14
all_pins[9]	values[0x0]	2475104	1			T24	1		T25	30		T26	1
all_pins[9]	values[0x1]	1506780	1			T25	30		T1	10503		T13	14
all_pins[9]	transitions[0x0=>0x1]	905359	1			T25	17		T1	6426		T13	10
all_pins[9]	transitions[0x1=>0x0]	902439	1			T25	14		T1	5924		T13	13
all_pins[10]	values[0x0]	2471976	1			T24	1		T25	39		T26	1
all_pins[10]	values[0x1]	1509908	1			T25	21		T1	10500		T13	19
all_pins[10]	transitions[0x0=>0x1]	904431	1			T25	11		T1	6157		T13	13
all_pins[10]	transitions[0x1=>0x0]	901303	1			T25	20		T1	6160		T13	8
all_pins[11]	values[0x0]	2470428	1			T24	1		T25	31		T26	1
all_pins[11]	values[0x1]	1511456	1			T25	29		T1	10054		T13	17
all_pins[11]	transitions[0x0=>0x1]	901582	1			T25	20		T1	5712		T13	8
all_pins[11]	transitions[0x1=>0x0]	900034	1			T25	12		T1	6158		T13	10
all_pins[12]	values[0x0]	2470047	1			T24	1		T25	34		T26	1
all_pins[12]	values[0x1]	1511837	1			T25	26		T1	10306		T13	23
all_pins[12]	transitions[0x0=>0x1]	903883	1			T25	13		T1	6264		T13	16
all_pins[12]	transitions[0x1=>0x0]	903502	1			T25	16		T1	6012		T13	10
all_pins[13]	values[0x0]	2471638	1			T24	1		T25	29		T26	1
all_pins[13]	values[0x1]	1510246	1			T25	31		T1	10089		T13	19
all_pins[13]	transitions[0x0=>0x1]	904131	1			T25	14		T1	6033		T13	5
all_pins[13]	transitions[0x1=>0x0]	905722	1			T25	9		T1	6250		T13	9
all_pins[14]	values[0x0]	2475233	1			T24	1		T25	33		T26	1
all_pins[14]	values[0x1]	1506651	1			T25	27		T1	10422		T13	17
all_pins[14]	transitions[0x0=>0x1]	904192	1			T25	16		T1	6363		T13	11
all_pins[14]	transitions[0x1=>0x0]	907787	1			T25	20		T1	6030		T13	13
all_pins[15]	values[0x0]	2471547	1			T24	1		T25	31		T26	1
all_pins[15]	values[0x1]	1510337	1			T25	29		T1	9927		T13	23
all_pins[15]	transitions[0x0=>0x1]	902408	1			T25	12		T1	5897		T13	15
all_pins[15]	transitions[0x1=>0x0]	898722	1			T25	10		T1	6392		T13	9
all_pins[16]	values[0x0]	2472342	1			T24	1		T25	31		T26	1
all_pins[16]	values[0x1]	1509542	1			T25	29		T1	9982		T13	23
all_pins[16]	transitions[0x0=>0x1]	902778	1			T25	14		T1	6045		T13	12
all_pins[16]	transitions[0x1=>0x0]	903573	1			T25	14		T1	5990		T13	12
all_pins[17]	values[0x0]	2467222	1			T24	1		T25	25		T26	1
all_pins[17]	values[0x1]	1514662	1			T25	35		T1	9741		T13	28
all_pins[17]	transitions[0x0=>0x1]	907319	1			T25	19		T1	5779		T13	13
all_pins[17]	transitions[0x1=>0x0]	902199	1			T25	13		T1	6020		T13	8
all_pins[18]	values[0x0]	2472435	1			T24	1		T25	22		T26	1
all_pins[18]	values[0x1]	1509449	1			T25	38		T1	10170		T13	16
all_pins[18]	transitions[0x0=>0x1]	899252	1			T25	17		T1	6160		T13	7
all_pins[18]	transitions[0x1=>0x0]	904465	1			T25	14		T1	5731		T13	19
all_pins[19]	values[0x0]	2474777	1			T24	1		T25	36		T26	1
all_pins[19]	values[0x1]	1507107	1			T25	24		T1	10423		T13	21
all_pins[19]	transitions[0x0=>0x1]	903184	1			T25	8		T1	6312		T13	13
all_pins[19]	transitions[0x1=>0x0]	905526	1			T25	22		T1	6059		T13	8
all_pins[20]	values[0x0]	2470723	1			T24	1		T25	39		T26	1
all_pins[20]	values[0x1]	1511161	1			T25	21		T1	10195		T13	18
all_pins[20]	transitions[0x0=>0x1]	904692	1			T25	11		T1	6017		T13	9
all_pins[20]	transitions[0x1=>0x0]	900638	1			T25	14		T1	6245		T13	12
all_pins[21]	values[0x0]	2472851	1			T24	1		T25	32		T26	1
all_pins[21]	values[0x1]	1509033	1			T25	28		T1	10227		T13	12
all_pins[21]	transitions[0x0=>0x1]	901464	1			T25	16		T1	6088		T13	5
all_pins[21]	transitions[0x1=>0x0]	903592	1			T25	9		T1	6056		T13	11
all_pins[22]	values[0x0]	2470180	1			T24	1		T25	30		T26	1
all_pins[22]	values[0x1]	1511704	1			T25	30		T1	9613		T13	20
all_pins[22]	transitions[0x0=>0x1]	903036	1			T25	16		T1	5633		T13	13
all_pins[22]	transitions[0x1=>0x0]	900365	1			T25	14		T1	6247		T13	5
all_pins[23]	values[0x0]	2474310	1			T24	1		T25	36		T26	1
all_pins[23]	values[0x1]	1507574	1			T25	24		T1	10368		T13	26
all_pins[23]	transitions[0x0=>0x1]	901389	1			T25	14		T1	6330		T13	16
all_pins[23]	transitions[0x1=>0x0]	905519	1			T25	20		T1	5575		T13	10
all_pins[24]	values[0x0]	2475639	1			T24	1		T25	26		T26	1
all_pins[24]	values[0x1]	1506245	1			T25	34		T1	10293		T13	19
all_pins[24]	transitions[0x0=>0x1]	903771	1			T25	22		T1	5909		T13	9
all_pins[24]	transitions[0x1=>0x0]	905100	1			T25	12		T1	5984		T13	16
all_pins[25]	values[0x0]	2476597	1			T24	1		T25	27		T26	1
all_pins[25]	values[0x1]	1505287	1			T25	33		T1	10116		T13	20
all_pins[25]	transitions[0x0=>0x1]	901333	1			T25	20		T1	5810		T13	10
all_pins[25]	transitions[0x1=>0x0]	902291	1			T25	21		T1	5987		T13	9
all_pins[26]	values[0x0]	2470130	1			T24	1		T25	27		T26	1
all_pins[26]	values[0x1]	1511754	1			T25	33		T1	10213		T13	29
all_pins[26]	transitions[0x0=>0x1]	907436	1			T25	12		T1	6116		T13	17
all_pins[26]	transitions[0x1=>0x0]	900969	1			T25	12		T1	6019		T13	8
all_pins[27]	values[0x0]	2471577	1			T24	1		T25	35		T26	1
all_pins[27]	values[0x1]	1510307	1			T25	25		T1	10364		T13	22
all_pins[27]	transitions[0x0=>0x1]	901881	1			T25	10		T1	6288		T13	8
all_pins[27]	transitions[0x1=>0x0]	903328	1			T25	18		T1	6137		T13	15
all_pins[28]	values[0x0]	2478016	1			T24	1		T25	33		T26	1
all_pins[28]	values[0x1]	1503868	1			T25	27		T1	10146		T13	21
all_pins[28]	transitions[0x0=>0x1]	898734	1			T25	14		T1	6024		T13	8
all_pins[28]	transitions[0x1=>0x0]	905173	1			T25	12		T1	6242		T13	9
all_pins[29]	values[0x0]	2476593	1			T24	1		T25	31		T26	1
all_pins[29]	values[0x1]	1505291	1			T25	29		T1	10065		T13	21
all_pins[29]	transitions[0x0=>0x1]	901240	1			T25	13		T1	6040		T13	14
all_pins[29]	transitions[0x1=>0x0]	899817	1			T25	11		T1	6121		T13	14
all_pins[30]	values[0x0]	2472554	1			T24	1		T25	25		T26	1
all_pins[30]	values[0x1]	1509330	1			T25	35		T1	10258		T13	20
all_pins[30]	transitions[0x0=>0x1]	902615	1			T25	15		T1	6322		T13	12
all_pins[30]	transitions[0x1=>0x0]	898576	1			T25	9		T1	6129		T13	13
all_pins[31]	values[0x0]	2476553	1			T24	1		T25	29		T26	1
all_pins[31]	values[0x1]	1505331	1			T25	31		T1	10302		T13	18
all_pins[31]	transitions[0x0=>0x1]	899430	1			T25	14		T1	6245		T13	11
all_pins[31]	transitions[0x1=>0x0]	903429	1			T25	18		T1	6201		T13	13