Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[1]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[2]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[3]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[4]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[5]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[6]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[7]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[8]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[9]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[10]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[11]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[12]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[13]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[14]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[15]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[16]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[17]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[18]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[19]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[20]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[21]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[22]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[23]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[24]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[25]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[26]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[27]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[28]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[29]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[30]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[31]	13277501	1			T24	1		T25	28951		T26	639

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250013189

1

T24

32

T25

464260

T26

14227

auto[1]

174866843

1

T25

462172

T26

6221

T1

201994

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343035270

1

T24

32

T25

926432

T26

12520

auto[1]

81844762

1

T26

7928

T1

705993

T12

6478

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319229094

1

T24

32

T25

926432

T26

12544

auto[1]

105650938

1

T26

7904

T1

918380

T12

11084

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4924902	1			T24	1		T25	14340		T26	226
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3763083	1			T25	14611		T26	75		T1	35700
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1288038	1			T26	126		T1	11148		T12	146
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1584340	1			T26	90		T1	1245		T12	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	439161	1			T1	16589		T12	159		T14	191
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1277977	1			T26	122		T1	10731		T12	75
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4937124	1			T24	1		T25	13378		T26	195
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3750909	1			T25	15573		T26	71		T1	35845
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1288888	1			T26	118		T1	11079		T12	98
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1587998	1			T26	133		T1	1200		T12	30
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	438612	1			T1	16417		T12	228		T14	275
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1273970	1			T26	122		T1	11025		T12	82
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4937497	1			T24	1		T25	14208		T26	218
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3748052	1			T25	14743		T26	70		T1	36046
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1289931	1			T26	144		T1	11309		T12	76
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1588981	1			T26	87		T1	1139		T12	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	439069	1			T1	16615		T12	238		T14	282
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1273971	1			T26	120		T1	10292		T12	103
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4930607	1			T24	1		T25	14361		T26	187
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3759750	1			T25	14590		T26	71		T1	35362
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1281797	1			T26	93		T1	10869		T12	63
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1589827	1			T26	152		T1	1262		T12	37
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	439690	1			T1	16790		T12	283		T14	251
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1275830	1			T26	136		T1	11132		T12	150
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4933075	1			T24	1		T25	13814		T26	173
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3758076	1			T25	15137		T26	58		T1	35036
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1285454	1			T26	108		T1	11046		T12	155
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1585625	1			T26	164		T1	1303		T12	40
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	439969	1			T1	16896		T12	186		T14	231
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1275302	1			T26	136		T1	11380		T12	109
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4936648	1			T24	1		T25	14461		T26	181
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3751774	1			T25	14490		T26	79		T1	35529
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1285720	1			T26	116		T1	10784		T12	122
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1586623	1			T26	147		T1	1201		T12	37
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	439675	1			T1	17191		T12	225		T14	140
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1277061	1			T26	116		T1	10834		T12	95
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4939410	1			T24	1		T25	13731		T26	218
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3748710	1			T25	15220		T26	68		T1	35716
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1290163	1			T26	130		T1	10508		T12	135
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1587187	1			T26	85		T1	1183		T12	31
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	438743	1			T1	16848		T12	191		T14	182
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1273288	1			T26	138		T1	10988		T12	52
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4944248	1			T24	1		T25	14527		T26	175
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3744761	1			T25	14424		T26	74		T1	35551
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1284368	1			T26	98		T1	11223		T12	95
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1586978	1			T26	150		T1	1174		T12	23
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	439207	1			T1	16532		T12	233		T14	216
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1277939	1			T26	142		T1	11099		T12	102
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4942887	1			T24	1		T25	14940		T26	195
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3750434	1			T25	14011		T26	64		T1	35572
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1284360	1			T26	140		T1	11278		T12	164
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1586959	1			T26	112		T1	1183		T12	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	437859	1			T1	16253		T12	109		T14	235
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1275002	1			T26	128		T1	11023		T12	82
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4936583	1			T24	1		T25	14993		T26	198
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3746562	1			T25	13958		T26	74		T1	35348
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1287284	1			T26	116		T1	11316		T12	138
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1588053	1			T26	138		T1	1218		T12	28
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	438220	1			T1	16205		T12	195		T14	284
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1280799	1			T26	113		T1	11150		T12	68
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4928521	1			T24	1		T25	14440		T26	186
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3762101	1			T25	14511		T26	70		T1	35800
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1287502	1			T26	120		T1	11268		T12	82
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1586353	1			T26	122		T1	1074		T12	29
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	438551	1			T1	16290		T12	223		T14	263
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1274473	1			T26	141		T1	11024		T12	120
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4939344	1			T24	1		T25	13362		T26	202
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3753587	1			T25	15589		T26	72		T1	35278
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1283113	1			T26	106		T1	11123		T12	140
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1590695	1			T26	132		T1	1277		T12	26
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	439474	1			T1	17291		T12	181		T14	299
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1271288	1			T26	127		T1	10782		T12	45
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4931178	1			T24	1		T25	13463		T26	200
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3759143	1			T25	15488		T26	78		T1	35717
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1285913	1			T26	125		T1	11557		T12	64
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1586874	1			T26	136		T1	1128		T12	36
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	438933	1			T1	16277		T12	257		T14	286
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1275460	1			T26	100		T1	10543		T12	161
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4925931	1			T24	1		T25	15078		T26	208
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3760516	1			T25	13873		T26	74		T1	35818
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1288316	1			T26	146		T1	11021		T12	111
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1585857	1			T26	104		T1	1214		T12	33
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	438077	1			T1	16322		T12	191		T14	221
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1278804	1			T26	107		T1	11205		T12	92
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4935204	1			T24	1		T25	14040		T26	197
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3755056	1			T25	14911		T26	67		T1	35834
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1289999	1			T26	144		T1	11000		T12	109
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1583974	1			T26	90		T1	1264		T12	33
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	438464	1			T1	16652		T12	264		T14	292
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1274804	1			T26	141		T1	10738		T12	63
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4942285	1			T24	1		T25	15371		T26	194
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3740573	1			T25	13580		T26	62		T1	35200
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1286376	1			T26	132		T1	10964		T12	119
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1591765	1			T26	107		T1	1229		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	442190	1			T1	17098		T12	189		T14	243
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1274312	1			T26	144		T1	11062		T12	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4943543	1			T24	1		T25	14272		T26	193
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3743596	1			T25	14679		T26	65		T1	35681
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1288620	1			T26	130		T1	10843		T12	104
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1588044	1			T26	116		T1	1260		T12	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	440478	1			T1	17050		T12	239		T14	295
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1273220	1			T26	135		T1	10779		T12	128
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4947032	1			T24	1		T25	14677		T26	229
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3744206	1			T25	14274		T26	73		T1	35619
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1278099	1			T26	126		T1	11386		T12	117
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1591720	1			T26	108		T1	1228		T12	36
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	442980	1			T1	16230		T12	200		T14	304
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1273464	1			T26	103		T1	11035		T12	107
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4962579	1			T24	1		T25	15039		T26	203
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3741215	1			T25	13912		T26	81		T1	35493
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1285069	1			T26	111		T1	11200		T12	142
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1584989	1			T26	130		T1	1213		T12	37
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	437715	1			T1	16539		T12	199		T14	203
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1265934	1			T26	114		T1	10895		T12	142
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4940769	1			T24	1		T25	14386		T26	175
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3752574	1			T25	14565		T26	89		T1	35401
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1285186	1			T26	131		T1	11100		T12	108
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1591002	1			T26	126		T1	1247		T12	20
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	437928	1			T1	16810		T12	215		T14	238
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1270042	1			T26	118		T1	10974		T12	74
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4948070	1			T24	1		T25	14595		T26	191
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3752777	1			T25	14356		T26	62		T1	35709
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1283287	1			T26	154		T1	11203		T12	126
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1587637	1			T26	90		T1	1125		T12	27
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	436933	1			T1	16364		T12	207		T14	238
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1268797	1			T26	142		T1	10885		T12	82
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4933106	1			T24	1		T25	14812		T26	215
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3756566	1			T25	14139		T26	69		T1	35364
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1279070	1			T26	96		T1	11466		T12	82
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1598575	1			T26	134		T1	1240		T12	39
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	438894	1			T1	16424		T12	246		T14	202
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1271290	1			T26	125		T1	10922		T12	95
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4945013	1			T24	1		T25	13778		T26	191
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3744876	1			T25	15173		T26	72		T1	34904
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1280014	1			T26	120		T1	11126		T12	113
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1592817	1			T26	168		T1	1362		T12	25
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	441666	1			T1	17199		T12	220		T14	283
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1273115	1			T26	88		T1	10939		T12	66
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4938909	1			T24	1		T25	14028		T26	207
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3752362	1			T25	14923		T26	68		T1	36118
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1278781	1			T26	112		T1	11185		T12	71
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1593793	1			T26	136		T1	1080		T12	33
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	441356	1			T1	16272		T12	285		T14	252
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1272300	1			T26	116		T1	10751		T12	103
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4938492	1			T24	1		T25	14712		T26	176
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3760543	1			T25	14239		T26	64		T1	35960
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1279141	1			T26	127		T1	11259		T12	92
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1591463	1			T26	146		T1	1164		T12	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	439925	1			T1	16683		T12	288		T14	171
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1267937	1			T26	126		T1	10588		T12	96
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4941082	1			T24	1		T25	15107		T26	212
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3757190	1			T25	13844		T26	64		T1	36106
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1279360	1			T26	92		T1	10996		T12	124
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1592730	1			T26	123		T1	1092		T12	30
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	438270	1			T1	16230		T12	222		T14	283
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1268869	1			T26	148		T1	10997		T12	98
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4946460	1			T24	1		T25	14981		T26	195
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3746514	1			T25	13970		T26	65		T1	35383
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1283198	1			T26	131		T1	10944		T12	98
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1590551	1			T26	114		T1	1234		T12	25
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	438260	1			T1	16556		T12	186		T14	316
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1272518	1			T26	134		T1	11232		T12	108
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4938831	1			T24	1		T25	13943		T26	210
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3756434	1			T25	15008		T26	68		T1	35421
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1280819	1			T26	129		T1	11188		T12	87
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1590994	1			T26	124		T1	1281		T12	38
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	439848	1			T1	16598		T12	321		T14	233
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1270575	1			T26	108		T1	11082		T12	109
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4937425	1			T24	1		T25	15705		T26	207
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3760909	1			T25	13246		T26	73		T1	35673
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1278449	1			T26	144		T1	11474		T12	79
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1590420	1			T26	110		T1	1270		T12	31
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	437395	1			T1	16258		T12	269		T14	236
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1272903	1			T26	105		T1	10873		T12	96
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4952840	1			T24	1		T25	14884		T26	203
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3741311	1			T25	14067		T26	66		T1	35660
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1283104	1			T26	134		T1	11141		T12	88
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1589106	1			T26	118		T1	1131		T12	21
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	440903	1			T1	16595		T12	176		T14	229
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1270237	1			T26	118		T1	10909		T12	97
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4942824	1			T24	1		T25	15223		T26	198
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3744161	1			T25	13728		T26	75		T1	36357
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1284047	1			T26	138		T1	11407		T12	95
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1594905	1			T26	114		T1	1046		T12	33
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	439248	1			T1	15867		T12	211		T14	250
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1272316	1			T26	114		T1	10766		T12	110
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4936449	1			T24	1		T25	15611		T26	195
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3761130	1			T25	13340		T26	61		T1	35885
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1287309	1			T26	112		T1	11057		T12	98
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1586711	1			T26	119		T1	1251		T12	28
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	435712	1			T1	16396		T12	248		T14	227
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1270190	1			T26	152		T1	10890		T12	73

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal