Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[1]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[2]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[3]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[4]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[5]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[6]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[7]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[8]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[9]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[10]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[11]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[12]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[13]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[14]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[15]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[16]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[17]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[18]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[19]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[20]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[21]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[22]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[23]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[24]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[25]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[26]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[27]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[28]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[29]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[30]	13277501	1			T24	1		T25	28951		T26	639
bins_for_gpio_bits[31]	13277501	1			T24	1		T25	28951		T26	639

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250013189

1

T24

32

T25

464260

T26

14227

auto[1]

174866843

1

T25

462172

T26

6221

T1

201994

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250005403

1

T24

32

T25

464260

T26

14218

auto[1]

174874629

1

T25

462172

T26

6230

T1

201971

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7567703	1			T24	1		T25	14340		T26	418
bins_for_gpio_bits[0]	auto[0]	auto[1]	229295	1			T26	24		T1	2046		T12	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	229577	1			T26	24		T1	2040		T12	25
bins_for_gpio_bits[0]	auto[1]	auto[1]	5250926	1			T25	14611		T26	173		T1	60974
bins_for_gpio_bits[1]	auto[0]	auto[0]	7584662	1			T24	1		T25	13378		T26	411
bins_for_gpio_bits[1]	auto[0]	auto[1]	229101	1			T26	35		T1	2034		T12	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	229348	1			T26	35		T1	2026		T12	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	5234390	1			T25	15573		T26	158		T1	61253
bins_for_gpio_bits[2]	auto[0]	auto[0]	7587038	1			T24	1		T25	14208		T26	417
bins_for_gpio_bits[2]	auto[0]	auto[1]	229140	1			T26	32		T1	2059		T12	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	229371	1			T26	32		T1	2050		T12	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	5231952	1			T25	14743		T26	158		T1	60894
bins_for_gpio_bits[3]	auto[0]	auto[0]	7572621	1			T24	1		T25	14361		T26	401
bins_for_gpio_bits[3]	auto[0]	auto[1]	229390	1			T26	31		T1	2055		T12	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	229610	1			T26	31		T1	2050		T12	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	5245880	1			T25	14590		T26	176		T1	61229
bins_for_gpio_bits[4]	auto[0]	auto[0]	7575141	1			T24	1		T25	13814		T26	410
bins_for_gpio_bits[4]	auto[0]	auto[1]	228767	1			T26	35		T1	2026		T12	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	229013	1			T26	35		T1	2020		T12	24
bins_for_gpio_bits[4]	auto[1]	auto[1]	5244580	1			T25	15137		T26	159		T1	61286
bins_for_gpio_bits[5]	auto[0]	auto[0]	7579627	1			T24	1		T25	14461		T26	417
bins_for_gpio_bits[5]	auto[0]	auto[1]	229153	1			T26	27		T1	1987		T12	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	229364	1			T26	27		T1	1980		T12	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	5239357	1			T25	14490		T26	168		T1	61567
bins_for_gpio_bits[6]	auto[0]	auto[0]	7587512	1			T24	1		T25	13731		T26	400
bins_for_gpio_bits[6]	auto[0]	auto[1]	229020	1			T26	33		T1	1977		T12	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	229248	1			T26	33		T1	1971		T12	17
bins_for_gpio_bits[6]	auto[1]	auto[1]	5231721	1			T25	15220		T26	173		T1	61575
bins_for_gpio_bits[7]	auto[0]	auto[0]	7585159	1			T24	1		T25	14527		T26	391
bins_for_gpio_bits[7]	auto[0]	auto[1]	230157	1			T26	32		T1	2048		T12	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	230435	1			T26	32		T1	2040		T12	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	5231750	1			T25	14424		T26	184		T1	61134
bins_for_gpio_bits[8]	auto[0]	auto[0]	7584990	1			T24	1		T25	14940		T26	420
bins_for_gpio_bits[8]	auto[0]	auto[1]	228999	1			T26	27		T1	2042		T12	20
bins_for_gpio_bits[8]	auto[1]	auto[0]	229216	1			T26	27		T1	2030		T12	20
bins_for_gpio_bits[8]	auto[1]	auto[1]	5234296	1			T25	14011		T26	165		T1	60806
bins_for_gpio_bits[9]	auto[0]	auto[0]	7582170	1			T24	1		T25	14993		T26	424
bins_for_gpio_bits[9]	auto[0]	auto[1]	229499	1			T26	27		T1	2022		T12	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	229750	1			T26	28		T1	2015		T12	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	5236082	1			T25	13958		T26	160		T1	60681
bins_for_gpio_bits[10]	auto[0]	auto[0]	7572857	1			T24	1		T25	14440		T26	391
bins_for_gpio_bits[10]	auto[0]	auto[1]	229254	1			T26	36		T1	2013		T12	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	229519	1			T26	37		T1	2003		T12	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	5245871	1			T25	14511		T26	175		T1	61101
bins_for_gpio_bits[11]	auto[0]	auto[0]	7583968	1			T24	1		T25	13362		T26	411
bins_for_gpio_bits[11]	auto[0]	auto[1]	228924	1			T26	28		T1	2045		T12	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	229184	1			T26	29		T1	2041		T12	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	5235425	1			T25	15589		T26	171		T1	61306
bins_for_gpio_bits[12]	auto[0]	auto[0]	7574007	1			T24	1		T25	13463		T26	431
bins_for_gpio_bits[12]	auto[0]	auto[1]	229702	1			T26	30		T1	2063		T12	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	229958	1			T26	30		T1	2057		T12	12
bins_for_gpio_bits[12]	auto[1]	auto[1]	5243834	1			T25	15488		T26	148		T1	60474
bins_for_gpio_bits[13]	auto[0]	auto[0]	7569966	1			T24	1		T25	15078		T26	428
bins_for_gpio_bits[13]	auto[0]	auto[1]	229917	1			T26	29		T1	2067		T12	18
bins_for_gpio_bits[13]	auto[1]	auto[0]	230138	1			T26	30		T1	2060		T12	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	5247480	1			T25	13873		T26	152		T1	61278
bins_for_gpio_bits[14]	auto[0]	auto[0]	7579641	1			T24	1		T25	14040		T26	397
bins_for_gpio_bits[14]	auto[0]	auto[1]	229289	1			T26	33		T1	2025		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	229536	1			T26	34		T1	2019		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5239035	1			T25	14911		T26	175		T1	61199
bins_for_gpio_bits[15]	auto[0]	auto[0]	7590749	1			T24	1		T25	15371		T26	401
bins_for_gpio_bits[15]	auto[0]	auto[1]	229450	1			T26	32		T1	1981		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	229677	1			T26	32		T1	1978		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	5227625	1			T25	13580		T26	174		T1	61379
bins_for_gpio_bits[16]	auto[0]	auto[0]	7590314	1			T24	1		T25	14272		T26	403
bins_for_gpio_bits[16]	auto[0]	auto[1]	229641	1			T26	35		T1	2050		T12	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	229893	1			T26	36		T1	2040		T12	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	5227653	1			T25	14679		T26	165		T1	61460
bins_for_gpio_bits[17]	auto[0]	auto[0]	7587424	1			T24	1		T25	14677		T26	436
bins_for_gpio_bits[17]	auto[0]	auto[1]	229208	1			T26	26		T1	2100		T12	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	229427	1			T26	27		T1	2090		T12	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	5231442	1			T25	14274		T26	150		T1	60784
bins_for_gpio_bits[18]	auto[0]	auto[0]	7603259	1			T24	1		T25	15039		T26	413
bins_for_gpio_bits[18]	auto[0]	auto[1]	229126	1			T26	31		T1	2083		T12	24
bins_for_gpio_bits[18]	auto[1]	auto[0]	229378	1			T26	31		T1	2076		T12	24
bins_for_gpio_bits[18]	auto[1]	auto[1]	5215738	1			T25	13912		T26	164		T1	60844
bins_for_gpio_bits[19]	auto[0]	auto[0]	7587358	1			T24	1		T25	14386		T26	404
bins_for_gpio_bits[19]	auto[0]	auto[1]	229403	1			T26	28		T1	2023		T12	17
bins_for_gpio_bits[19]	auto[1]	auto[0]	229599	1			T26	28		T1	2012		T12	17
bins_for_gpio_bits[19]	auto[1]	auto[1]	5231141	1			T25	14565		T26	179		T1	61162
bins_for_gpio_bits[20]	auto[0]	auto[0]	7589914	1			T24	1		T25	14595		T26	403
bins_for_gpio_bits[20]	auto[0]	auto[1]	228863	1			T26	32		T1	2019		T12	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	229080	1			T26	32		T1	2015		T12	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	5229644	1			T25	14356		T26	172		T1	60939
bins_for_gpio_bits[21]	auto[0]	auto[0]	7580719	1			T24	1		T25	14812		T26	413
bins_for_gpio_bits[21]	auto[0]	auto[1]	229775	1			T26	31		T1	2120		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	230032	1			T26	32		T1	2107		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	5236975	1			T25	14139		T26	163		T1	60590
bins_for_gpio_bits[22]	auto[0]	auto[0]	7587826	1			T24	1		T25	13778		T26	448
bins_for_gpio_bits[22]	auto[0]	auto[1]	229754	1			T26	31		T1	2069		T12	19
bins_for_gpio_bits[22]	auto[1]	auto[0]	230018	1			T26	31		T1	2064		T12	19
bins_for_gpio_bits[22]	auto[1]	auto[1]	5229903	1			T25	15173		T26	129		T1	60973
bins_for_gpio_bits[23]	auto[0]	auto[0]	7581659	1			T24	1		T25	14028		T26	420
bins_for_gpio_bits[23]	auto[0]	auto[1]	229592	1			T26	35		T1	2073		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	229824	1			T26	35		T1	2068		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	5236426	1			T25	14923		T26	149		T1	61068
bins_for_gpio_bits[24]	auto[0]	auto[0]	7579759	1			T24	1		T25	14712		T26	420
bins_for_gpio_bits[24]	auto[0]	auto[1]	229180	1			T26	29		T1	2047		T12	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	229337	1			T26	29		T1	2037		T12	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	5239225	1			T25	14239		T26	161		T1	61184
bins_for_gpio_bits[25]	auto[0]	auto[0]	7584201	1			T24	1		T25	15107		T26	396
bins_for_gpio_bits[25]	auto[0]	auto[1]	228697	1			T26	31		T1	2071		T12	19
bins_for_gpio_bits[25]	auto[1]	auto[0]	228971	1			T26	31		T1	2065		T12	19
bins_for_gpio_bits[25]	auto[1]	auto[1]	5235632	1			T25	13844		T26	181		T1	61262
bins_for_gpio_bits[26]	auto[0]	auto[0]	7590213	1			T24	1		T25	14981		T26	410
bins_for_gpio_bits[26]	auto[0]	auto[1]	229711	1			T26	30		T1	2045		T12	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	229996	1			T26	30		T1	2039		T12	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	5227581	1			T25	13970		T26	169		T1	61126
bins_for_gpio_bits[27]	auto[0]	auto[0]	7581532	1			T24	1		T25	13943		T26	432
bins_for_gpio_bits[27]	auto[0]	auto[1]	228789	1			T26	31		T1	1987		T12	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	229112	1			T26	31		T1	1982		T12	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	5238068	1			T25	15008		T26	145		T1	61114
bins_for_gpio_bits[28]	auto[0]	auto[0]	7576532	1			T24	1		T25	15705		T26	431
bins_for_gpio_bits[28]	auto[0]	auto[1]	229520	1			T26	29		T1	2089		T12	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	229762	1			T26	30		T1	2083		T12	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5241687	1			T25	13246		T26	149		T1	60715
bins_for_gpio_bits[29]	auto[0]	auto[0]	7595576	1			T24	1		T25	14884		T26	426
bins_for_gpio_bits[29]	auto[0]	auto[1]	229227	1			T26	29		T1	2070		T12	20
bins_for_gpio_bits[29]	auto[1]	auto[0]	229474	1			T26	29		T1	2065		T12	20
bins_for_gpio_bits[29]	auto[1]	auto[1]	5223224	1			T25	14067		T26	155		T1	61094
bins_for_gpio_bits[30]	auto[0]	auto[0]	7591813	1			T24	1		T25	15223		T26	413
bins_for_gpio_bits[30]	auto[0]	auto[1]	229721	1			T26	37		T1	2119		T12	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	229963	1			T26	37		T1	2113		T12	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	5226004	1			T25	13728		T26	152		T1	60871
bins_for_gpio_bits[31]	auto[0]	auto[0]	7580697	1			T24	1		T25	15611		T26	388
bins_for_gpio_bits[31]	auto[0]	auto[1]	229532	1			T26	38		T1	2102		T12	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	229772	1			T26	38		T1	2091		T12	19
bins_for_gpio_bits[31]	auto[1]	auto[1]	5237500	1			T25	13340		T26	175		T1	61069