Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884093 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5621689 |
1 |
|
|
T1 |
37903 |
|
T17 |
211 |
|
T19 |
483 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11154622 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
2351160 |
1 |
|
|
T1 |
24267 |
|
T17 |
47 |
|
T19 |
293 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884082 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5621700 |
1 |
|
|
T1 |
39163 |
|
T17 |
93 |
|
T19 |
604 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1635000 |
1 |
|
|
T1 |
8081 |
|
T17 |
18 |
|
T19 |
210 |
| auto[1] |
auto[0] |
auto[1] |
1172155 |
1 |
|
|
T1 |
13043 |
|
T17 |
25 |
|
T19 |
186 |
| auto[1] |
auto[1] |
auto[0] |
1635540 |
1 |
|
|
T1 |
6815 |
|
T17 |
28 |
|
T19 |
101 |
| auto[1] |
auto[1] |
auto[1] |
1179005 |
1 |
|
|
T1 |
11224 |
|
T17 |
22 |
|
T19 |
107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |