Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878581 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5627201 |
1 |
|
|
T1 |
40107 |
|
T17 |
218 |
|
T19 |
463 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11165767 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
2340015 |
1 |
|
|
T1 |
25282 |
|
T17 |
102 |
|
T19 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904686 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5601096 |
1 |
|
|
T1 |
40752 |
|
T17 |
201 |
|
T19 |
437 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1616834 |
1 |
|
|
T1 |
7678 |
|
T17 |
32 |
|
T19 |
119 |
| auto[1] |
auto[0] |
auto[1] |
1163525 |
1 |
|
|
T1 |
12595 |
|
T17 |
35 |
|
T19 |
150 |
| auto[1] |
auto[1] |
auto[0] |
1644247 |
1 |
|
|
T1 |
7792 |
|
T17 |
67 |
|
T19 |
85 |
| auto[1] |
auto[1] |
auto[1] |
1176490 |
1 |
|
|
T1 |
12687 |
|
T17 |
67 |
|
T19 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |