Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889258 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5616524 |
1 |
|
|
T1 |
40430 |
|
T17 |
208 |
|
T19 |
317 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11164619 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
2341163 |
1 |
|
|
T1 |
25305 |
|
T17 |
87 |
|
T19 |
183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898973 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5606809 |
1 |
|
|
T1 |
40473 |
|
T17 |
147 |
|
T19 |
357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1637944 |
1 |
|
|
T1 |
7601 |
|
T17 |
26 |
|
T19 |
124 |
| auto[1] |
auto[0] |
auto[1] |
1170011 |
1 |
|
|
T1 |
12591 |
|
T17 |
36 |
|
T19 |
141 |
| auto[1] |
auto[1] |
auto[0] |
1627702 |
1 |
|
|
T1 |
7567 |
|
T17 |
34 |
|
T19 |
50 |
| auto[1] |
auto[1] |
auto[1] |
1171152 |
1 |
|
|
T1 |
12714 |
|
T17 |
51 |
|
T19 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |