Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7866839 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5638943 |
1 |
|
|
T1 |
40227 |
|
T17 |
85 |
|
T19 |
522 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11154713 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
2351069 |
1 |
|
|
T1 |
23718 |
|
T17 |
49 |
|
T19 |
107 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7890920 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5614862 |
1 |
|
|
T1 |
37815 |
|
T17 |
105 |
|
T19 |
244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1624076 |
1 |
|
|
T1 |
7303 |
|
T17 |
56 |
|
T19 |
53 |
| auto[1] |
auto[0] |
auto[1] |
1171074 |
1 |
|
|
T1 |
11881 |
|
T17 |
49 |
|
T19 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1639717 |
1 |
|
|
T1 |
6794 |
|
T19 |
84 |
|
T35 |
47 |
| auto[1] |
auto[1] |
auto[1] |
1179995 |
1 |
|
|
T1 |
11837 |
|
T19 |
82 |
|
T23 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |