Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891000 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5614782 |
1 |
|
|
T1 |
40661 |
|
T17 |
198 |
|
T19 |
592 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12779323 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
726459 |
1 |
|
|
T1 |
5162 |
|
T17 |
29 |
|
T19 |
63 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881021 |
1 |
|
|
T24 |
1 |
|
T25 |
28951 |
|
T26 |
391 |
| auto[1] |
5624761 |
1 |
|
|
T1 |
40980 |
|
T17 |
137 |
|
T19 |
330 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2450885 |
1 |
|
|
T1 |
16394 |
|
T17 |
48 |
|
T19 |
136 |
| auto[1] |
auto[0] |
auto[1] |
363970 |
1 |
|
|
T1 |
2269 |
|
T17 |
13 |
|
T19 |
30 |
| auto[1] |
auto[1] |
auto[0] |
2447417 |
1 |
|
|
T1 |
19424 |
|
T17 |
60 |
|
T19 |
131 |
| auto[1] |
auto[1] |
auto[1] |
362489 |
1 |
|
|
T1 |
2893 |
|
T17 |
16 |
|
T19 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |