Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4347497	1			T22	86		T23	37175		T24	1
all_pins[1]	4347497	1			T22	86		T23	37175		T24	1
all_pins[2]	4347497	1			T22	86		T23	37175		T24	1
all_pins[3]	4347497	1			T22	86		T23	37175		T24	1
all_pins[4]	4347497	1			T22	86		T23	37175		T24	1
all_pins[5]	4347497	1			T22	86		T23	37175		T24	1
all_pins[6]	4347497	1			T22	86		T23	37175		T24	1
all_pins[7]	4347497	1			T22	86		T23	37175		T24	1
all_pins[8]	4347497	1			T22	86		T23	37175		T24	1
all_pins[9]	4347497	1			T22	86		T23	37175		T24	1
all_pins[10]	4347497	1			T22	86		T23	37175		T24	1
all_pins[11]	4347497	1			T22	86		T23	37175		T24	1
all_pins[12]	4347497	1			T22	86		T23	37175		T24	1
all_pins[13]	4347497	1			T22	86		T23	37175		T24	1
all_pins[14]	4347497	1			T22	86		T23	37175		T24	1
all_pins[15]	4347497	1			T22	86		T23	37175		T24	1
all_pins[16]	4347497	1			T22	86		T23	37175		T24	1
all_pins[17]	4347497	1			T22	86		T23	37175		T24	1
all_pins[18]	4347497	1			T22	86		T23	37175		T24	1
all_pins[19]	4347497	1			T22	86		T23	37175		T24	1
all_pins[20]	4347497	1			T22	86		T23	37175		T24	1
all_pins[21]	4347497	1			T22	86		T23	37175		T24	1
all_pins[22]	4347497	1			T22	86		T23	37175		T24	1
all_pins[23]	4347497	1			T22	86		T23	37175		T24	1
all_pins[24]	4347497	1			T22	86		T23	37175		T24	1
all_pins[25]	4347497	1			T22	86		T23	37175		T24	1
all_pins[26]	4347497	1			T22	86		T23	37175		T24	1
all_pins[27]	4347497	1			T22	86		T23	37175		T24	1
all_pins[28]	4347497	1			T22	86		T23	37175		T24	1
all_pins[29]	4347497	1			T22	86		T23	37175		T24	1
all_pins[30]	4347497	1			T22	86		T23	37175		T24	1
all_pins[31]	4347497	1			T22	86		T23	37175		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	86389194	1			T22	1436		T23	733810		T24	32
values[0x1]	52730710	1			T22	1316		T23	455790		T25	171995
transitions[0x0=>0x1]	31581308	1			T22	648		T23	270700		T25	102912
transitions[0x1=>0x0]	31581161	1			T22	648		T23	270700		T25	102912

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2703936	1			T22	42		T23	23392		T24	1
all_pins[0]	values[0x1]	1643561	1			T22	44		T23	13783		T25	53204
all_pins[0]	transitions[0x0=>0x1]	1020292	1			T22	22		T23	8817		T25	33100
all_pins[0]	transitions[0x1=>0x0]	1020394	1			T22	17		T23	9156		T25	34017
all_pins[1]	values[0x0]	2699476	1			T22	51		T23	22596		T24	1
all_pins[1]	values[0x1]	1648021	1			T22	35		T23	14579		T25	53098
all_pins[1]	transitions[0x0=>0x1]	989837	1			T22	10		T23	8982		T25	31782
all_pins[1]	transitions[0x1=>0x0]	985377	1			T22	19		T23	8186		T25	31888
all_pins[2]	values[0x0]	2694950	1			T22	47		T23	22950		T24	1
all_pins[2]	values[0x1]	1652547	1			T22	39		T23	14225		T25	53856
all_pins[2]	transitions[0x0=>0x1]	989401	1			T22	19		T23	8201		T25	32812
all_pins[2]	transitions[0x1=>0x0]	984875	1			T22	15		T23	8555		T25	32054
all_pins[3]	values[0x0]	2700166	1			T22	48		T23	22696		T24	1
all_pins[3]	values[0x1]	1647331	1			T22	38		T23	14479		T25	53200
all_pins[3]	transitions[0x0=>0x1]	984870	1			T22	17		T23	8391		T25	31831
all_pins[3]	transitions[0x1=>0x0]	990086	1			T22	18		T23	8137		T25	32487
all_pins[4]	values[0x0]	2695604	1			T22	45		T23	23166		T24	1
all_pins[4]	values[0x1]	1651893	1			T22	41		T23	14009		T25	54372
all_pins[4]	transitions[0x0=>0x1]	987969	1			T22	22		T23	8140		T25	32673
all_pins[4]	transitions[0x1=>0x0]	983407	1			T22	19		T23	8610		T25	31501
all_pins[5]	values[0x0]	2694894	1			T22	42		T23	23126		T24	1
all_pins[5]	values[0x1]	1652603	1			T22	44		T23	14049		T25	54071
all_pins[5]	transitions[0x0=>0x1]	987884	1			T22	26		T23	8591		T25	31571
all_pins[5]	transitions[0x1=>0x0]	987174	1			T22	23		T23	8551		T25	31872
all_pins[6]	values[0x0]	2697468	1			T22	38		T23	22795		T24	1
all_pins[6]	values[0x1]	1650029	1			T22	48		T23	14380		T25	54571
all_pins[6]	transitions[0x0=>0x1]	985384	1			T22	22		T23	8665		T25	32153
all_pins[6]	transitions[0x1=>0x0]	987958	1			T22	18		T23	8334		T25	31653
all_pins[7]	values[0x0]	2703183	1			T22	47		T23	23024		T24	1
all_pins[7]	values[0x1]	1644314	1			T22	39		T23	14151		T25	53608
all_pins[7]	transitions[0x0=>0x1]	981987	1			T22	14		T23	8340		T25	31487
all_pins[7]	transitions[0x1=>0x0]	987702	1			T22	23		T23	8569		T25	32450
all_pins[8]	values[0x0]	2700459	1			T22	50		T23	22976		T24	1
all_pins[8]	values[0x1]	1647038	1			T22	36		T23	14199		T25	53004
all_pins[8]	transitions[0x0=>0x1]	987533	1			T22	19		T23	8392		T25	31809
all_pins[8]	transitions[0x1=>0x0]	984809	1			T22	22		T23	8344		T25	32413
all_pins[9]	values[0x0]	2701208	1			T22	51		T23	23167		T24	1
all_pins[9]	values[0x1]	1646289	1			T22	35		T23	14008		T25	53578
all_pins[9]	transitions[0x0=>0x1]	983581	1			T22	20		T23	8325		T25	32337
all_pins[9]	transitions[0x1=>0x0]	984330	1			T22	21		T23	8516		T25	31763
all_pins[10]	values[0x0]	2701163	1			T22	45		T23	22651		T24	1
all_pins[10]	values[0x1]	1646334	1			T22	41		T23	14524		T25	54186
all_pins[10]	transitions[0x0=>0x1]	982109	1			T22	25		T23	8789		T25	32638
all_pins[10]	transitions[0x1=>0x0]	982064	1			T22	19		T23	8273		T25	32030
all_pins[11]	values[0x0]	2700095	1			T22	41		T23	22642		T24	1
all_pins[11]	values[0x1]	1647402	1			T22	45		T23	14533		T25	53806
all_pins[11]	transitions[0x0=>0x1]	987030	1			T22	24		T23	8602		T25	32034
all_pins[11]	transitions[0x1=>0x0]	985962	1			T22	20		T23	8593		T25	32414
all_pins[12]	values[0x0]	2701532	1			T22	45		T23	23106		T24	1
all_pins[12]	values[0x1]	1645965	1			T22	41		T23	14069		T25	53287
all_pins[12]	transitions[0x0=>0x1]	986207	1			T22	21		T23	8249		T25	31776
all_pins[12]	transitions[0x1=>0x0]	987644	1			T22	25		T23	8713		T25	32295
all_pins[13]	values[0x0]	2696430	1			T22	41		T23	22115		T24	1
all_pins[13]	values[0x1]	1651067	1			T22	45		T23	15060		T25	53662
all_pins[13]	transitions[0x0=>0x1]	988511	1			T22	24		T23	9019		T25	32187
all_pins[13]	transitions[0x1=>0x0]	983409	1			T22	20		T23	8028		T25	31812
all_pins[14]	values[0x0]	2696738	1			T22	55		T23	23243		T24	1
all_pins[14]	values[0x1]	1650759	1			T22	31		T23	13932		T25	53880
all_pins[14]	transitions[0x0=>0x1]	982685	1			T22	13		T23	7934		T25	32281
all_pins[14]	transitions[0x1=>0x0]	982993	1			T22	27		T23	9062		T25	32063
all_pins[15]	values[0x0]	2703364	1			T22	44		T23	23097		T24	1
all_pins[15]	values[0x1]	1644133	1			T22	42		T23	14078		T25	53212
all_pins[15]	transitions[0x0=>0x1]	981948	1			T22	25		T23	8519		T25	31739
all_pins[15]	transitions[0x1=>0x0]	988574	1			T22	14		T23	8373		T25	32407
all_pins[16]	values[0x0]	2693865	1			T22	47		T23	23062		T24	1
all_pins[16]	values[0x1]	1653632	1			T22	39		T23	14113		T25	54549
all_pins[16]	transitions[0x0=>0x1]	991006	1			T22	17		T23	8378		T25	32748
all_pins[16]	transitions[0x1=>0x0]	981507	1			T22	20		T23	8343		T25	31411
all_pins[17]	values[0x0]	2703073	1			T22	44		T23	23308		T24	1
all_pins[17]	values[0x1]	1644424	1			T22	42		T23	13867		T25	53536
all_pins[17]	transitions[0x0=>0x1]	983420	1			T22	21		T23	8276		T25	31741
all_pins[17]	transitions[0x1=>0x0]	992628	1			T22	18		T23	8522		T25	32754
all_pins[18]	values[0x0]	2706214	1			T22	39		T23	22499		T24	1
all_pins[18]	values[0x1]	1641283	1			T22	47		T23	14676		T25	53404
all_pins[18]	transitions[0x0=>0x1]	981532	1			T22	23		T23	8921		T25	32206
all_pins[18]	transitions[0x1=>0x0]	984673	1			T22	18		T23	8112		T25	32338
all_pins[19]	values[0x0]	2696624	1			T22	49		T23	22530		T24	1
all_pins[19]	values[0x1]	1650873	1			T22	37		T23	14645		T25	53837
all_pins[19]	transitions[0x0=>0x1]	990987	1			T22	20		T23	8643		T25	32106
all_pins[19]	transitions[0x1=>0x0]	981397	1			T22	30		T23	8674		T25	31673
all_pins[20]	values[0x0]	2696255	1			T22	49		T23	22985		T24	1
all_pins[20]	values[0x1]	1651242	1			T22	37		T23	14190		T25	54716
all_pins[20]	transitions[0x0=>0x1]	985737	1			T22	20		T23	8222		T25	32726
all_pins[20]	transitions[0x1=>0x0]	985368	1			T22	20		T23	8677		T25	31847
all_pins[21]	values[0x0]	2696954	1			T22	36		T23	22886		T24	1
all_pins[21]	values[0x1]	1650543	1			T22	50		T23	14289		T25	54608
all_pins[21]	transitions[0x0=>0x1]	985406	1			T22	28		T23	8478		T25	32207
all_pins[21]	transitions[0x1=>0x0]	986105	1			T22	15		T23	8379		T25	32315
all_pins[22]	values[0x0]	2703908	1			T22	46		T23	23324		T24	1
all_pins[22]	values[0x1]	1643589	1			T22	40		T23	13851		T25	53647
all_pins[22]	transitions[0x0=>0x1]	983221	1			T22	15		T23	8174		T25	31402
all_pins[22]	transitions[0x1=>0x0]	990175	1			T22	25		T23	8612		T25	32363
all_pins[23]	values[0x0]	2695198	1			T22	46		T23	22609		T24	1
all_pins[23]	values[0x1]	1652299	1			T22	40		T23	14566		T25	53396
all_pins[23]	transitions[0x0=>0x1]	989153	1			T22	18		T23	8738		T25	32024
all_pins[23]	transitions[0x1=>0x0]	980443	1			T22	18		T23	8023		T25	32275
all_pins[24]	values[0x0]	2704181	1			T22	39		T23	23219		T24	1
all_pins[24]	values[0x1]	1643316	1			T22	47		T23	13956		T25	53098
all_pins[24]	transitions[0x0=>0x1]	981294	1			T22	24		T23	8184		T25	32063
all_pins[24]	transitions[0x1=>0x0]	990277	1			T22	17		T23	8794		T25	32361
all_pins[25]	values[0x0]	2699797	1			T22	43		T23	23647		T24	1
all_pins[25]	values[0x1]	1647700	1			T22	43		T23	13528		T25	53469
all_pins[25]	transitions[0x0=>0x1]	989149	1			T22	16		T23	7932		T25	32265
all_pins[25]	transitions[0x1=>0x0]	984765	1			T22	20		T23	8360		T25	31894
all_pins[26]	values[0x0]	2700677	1			T22	33		T23	22626		T24	1
all_pins[26]	values[0x1]	1646820	1			T22	53		T23	14549		T25	52714
all_pins[26]	transitions[0x0=>0x1]	984051	1			T22	26		T23	8888		T25	32006
all_pins[26]	transitions[0x1=>0x0]	984931	1			T22	16		T23	7867		T25	32761
all_pins[27]	values[0x0]	2697796	1			T22	47		T23	22921		T24	1
all_pins[27]	values[0x1]	1649701	1			T22	39		T23	14254		T25	53761
all_pins[27]	transitions[0x0=>0x1]	988361	1			T22	17		T23	8353		T25	32907
all_pins[27]	transitions[0x1=>0x0]	985480	1			T22	31		T23	8648		T25	31860
all_pins[28]	values[0x0]	2696468	1			T22	49		T23	22882		T24	1
all_pins[28]	values[0x1]	1651029	1			T22	37		T23	14293		T25	53341
all_pins[28]	transitions[0x0=>0x1]	986336	1			T22	19		T23	8460		T25	32092
all_pins[28]	transitions[0x1=>0x0]	985008	1			T22	21		T23	8421		T25	32512
all_pins[29]	values[0x0]	2703900	1			T22	50		T23	22609		T24	1
all_pins[29]	values[0x1]	1643597	1			T22	36		T23	14566		T25	54247
all_pins[29]	transitions[0x0=>0x1]	982073	1			T22	19		T23	8501		T25	32390
all_pins[29]	transitions[0x1=>0x0]	989505	1			T22	20		T23	8228		T25	31484
all_pins[30]	values[0x0]	2699931	1			T22	40		T23	22908		T24	1
all_pins[30]	values[0x1]	1647566	1			T22	46		T23	14267		T25	54914
all_pins[30]	transitions[0x0=>0x1]	986157	1			T22	27		T23	8191		T25	32450
all_pins[30]	transitions[0x1=>0x0]	982188	1			T22	17		T23	8490		T25	31783
all_pins[31]	values[0x0]	2703687	1			T22	47		T23	23053		T24	1
all_pins[31]	values[0x1]	1643810	1			T22	39		T23	14122		T25	54121
all_pins[31]	transitions[0x0=>0x1]	986197	1			T22	15		T23	8405		T25	31582
all_pins[31]	transitions[0x1=>0x0]	989953	1			T22	22		T23	8550		T25	32375