Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[1]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[2]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[3]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[4]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[5]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[6]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[7]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[8]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[9]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[10]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[11]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[12]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[13]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[14]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[15]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[16]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[17]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[18]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[19]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[20]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[21]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[22]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[23]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[24]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[25]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[26]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[27]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[28]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[29]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[30]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[31]	14476251	1			T22	1308		T23	112881		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282377663

1

T22

20838

T23

232301

T24

32

auto[1]

180862369

1

T22

21018

T23

128918

T25

436300

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368945305

1

T22

41856

T23

286614

T24

32

auto[1]

94294727

1

T23

746049

T25

269830

T27

4753

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341654898

1

T22

41856

T23

266301

T24

32

auto[1]

121585134

1

T23

949182

T25

355770

T27

10193

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5407803	1			T22	643		T23	43578		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3784884	1			T22	665		T23	27539		T25	89645
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1476873	1			T23	11765		T25	43599		T27	83
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1943274	1			T23	17346		T25	63274		T27	28
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	388062	1			T23	1154		T25	4841		T27	228
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1475355	1			T23	11499		T25	41883		T27	75
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5410072	1			T22	698		T23	43981		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3785446	1			T22	610		T23	27524		T25	89113
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1478894	1			T23	12218		T25	42103		T27	52
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1941638	1			T23	16626		T25	64810		T27	32
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	388508	1			T23	1027		T25	5104		T27	214
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1471693	1			T23	11505		T25	42238		T27	104
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5401827	1			T22	703		T23	43982		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3789773	1			T22	605		T23	27876		T25	89737
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1477598	1			T23	11467		T25	43055		T27	77
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1946175	1			T23	17095		T25	64348		T27	38
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	389881	1			T23	1027		T25	4794		T27	172
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1470997	1			T23	11434		T25	41723		T27	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5395095	1			T22	595		T23	43535		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3795564	1			T22	713		T23	27610		T25	89496
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1484612	1			T23	11332		T25	42542		T27	66
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1943674	1			T23	17112		T25	64141		T27	26
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	390221	1			T23	1162		T25	4909		T27	229
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1467085	1			T23	12130		T25	41959		T27	83
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5404201	1			T22	611		T23	43880		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3789987	1			T22	697		T23	27557		T25	89700
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1481239	1			T23	12086		T25	42253		T27	56
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1941300	1			T23	17052		T25	63704		T27	25
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	387505	1			T23	1122		T25	4766		T27	224
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1472019	1			T23	11184		T25	42807		T27	62
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5397821	1			T22	608		T23	43705		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3795642	1			T22	700		T23	27427		T25	89409
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1484781	1			T23	11481		T25	42445		T27	69
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1938924	1			T23	17044		T25	63738		T27	23
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	386273	1			T23	1232		T25	4816		T27	186
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1472810	1			T23	11992		T25	41077		T27	76
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5401145	1			T22	661		T23	44379		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3785459	1			T22	647		T23	27466		T25	89305
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1484198	1			T23	11875		T25	41367		T27	53
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1944642	1			T23	16957		T25	65655		T27	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	389175	1			T23	1026		T25	4914		T27	242
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1471632	1			T23	11178		T25	42336		T27	95
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5401480	1			T22	631		T23	44182		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3794491	1			T22	677		T23	27448		T25	89634
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1479037	1			T23	11749		T25	41988		T27	87
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1940134	1			T23	16912		T25	64194		T27	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	388777	1			T23	1201		T25	4714		T27	260
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1472332	1			T23	11389		T25	42533		T27	69
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5390806	1			T22	645		T23	44168		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3799448	1			T22	663		T23	27399		T25	89585
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1478772	1			T23	11316		T25	42992		T27	67
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1947661	1			T23	17112		T25	63105		T27	35
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	388164	1			T23	1079		T25	4906		T27	226
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1471400	1			T23	11807		T25	41905		T27	61
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5394991	1			T22	620		T23	43899		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3801996	1			T22	688		T23	27702		T25	89493
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1476050	1			T23	11572		T25	42947		T27	90
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1945950	1			T23	17093		T25	64296		T27	38
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	385911	1			T23	1007		T25	4927		T27	222
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1471353	1			T23	11608		T25	42765		T27	86
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5402497	1			T22	761		T23	44319		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3791536	1			T22	547		T23	27287		T25	89559
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1483969	1			T23	11839		T25	43400		T27	92
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1938786	1			T23	17100		T25	62511		T27	29
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	386381	1			T23	1047		T25	4719		T27	154
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1473082	1			T23	11289		T25	42652		T27	66
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5400972	1			T22	642		T23	44009		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3798424	1			T22	666		T23	27638		T25	89246
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1479237	1			T23	11587		T25	43651		T27	87
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1940041	1			T23	16663		T25	63768		T27	35
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	388693	1			T23	1099		T25	4821		T27	182
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1468884	1			T23	11885		T25	41676		T27	94
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5395573	1			T22	588		T23	44499		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3802265	1			T22	720		T23	27633		T25	88901
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1484991	1			T23	11737		T25	42135		T27	67
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1938605	1			T23	16584		T25	64830		T27	34
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	386840	1			T23	1044		T25	5216		T27	224
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1467977	1			T23	11384		T25	43000		T27	80
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5403629	1			T22	686		T23	43977		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3794164	1			T22	622		T23	27478		T25	89506
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1479870	1			T23	12000		T25	42098		T27	56
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1942100	1			T23	16651		T25	63395		T27	40
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	386926	1			T23	1048		T25	4946		T27	223
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1469562	1			T23	11727		T25	42104		T27	86
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5399707	1			T22	659		T23	44096		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3797447	1			T22	649		T23	27313		T25	89669
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1480998	1			T23	12078		T25	42353		T27	104
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1938628	1			T23	16830		T25	63603		T27	18
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	386759	1			T23	1216		T25	4798		T27	163
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1472712	1			T23	11348		T25	41953		T27	87
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5404021	1			T22	739		T23	44236		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3791998	1			T22	569		T23	27700		T25	89454
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1485510	1			T23	11923		T25	42783		T27	31
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1935704	1			T23	16306		T25	63553		T27	26
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	388460	1			T23	1086		T25	4720		T27	281
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1470558	1			T23	11630		T25	41732		T27	86
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5410139	1			T22	627		T23	43838		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3793799	1			T22	681		T23	27464		T25	89863
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1473976	1			T23	11442		T25	42164		T27	71
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1946625	1			T23	17287		T25	64472		T27	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	388678	1			T23	1132		T25	4806		T27	196
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1463034	1			T23	11718		T25	41789		T27	63
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5395105	1			T22	660		T23	43388		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3800307	1			T22	648		T23	27535		T25	89128
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1477179	1			T23	11806		T25	42485		T27	78
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1949852	1			T23	16996		T25	64244		T27	30
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	388005	1			T23	1093		T25	4781		T27	232
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1465803	1			T23	12063		T25	41644		T27	98
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5399404	1			T22	709		T23	43811		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3801960	1			T22	599		T23	27538		T25	89214
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1475730	1			T23	11673		T25	41561		T27	62
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1949190	1			T23	17318		T25	65773		T27	35
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	389468	1			T23	1177		T25	5065		T27	255
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1460499	1			T23	11364		T25	40824		T27	82
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5399985	1			T22	586		T23	43812		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3800235	1			T22	722		T23	27364		T25	89547
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1477814	1			T23	11922		T25	42168		T27	69
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1947149	1			T23	16997		T25	65084		T27	26
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	388757	1			T23	1147		T25	4834		T27	199
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1462311	1			T23	11639		T25	41748		T27	64
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5401893	1			T22	626		T23	44090		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3800175	1			T22	682		T23	27655		T25	89735
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1479189	1			T23	11488		T25	42755		T27	87
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1946100	1			T23	16837		T25	64661		T27	13
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	388021	1			T23	1008		T25	4779		T27	145
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1460873	1			T23	11803		T25	40842		T27	49
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5412967	1			T22	595		T23	44071		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3795913	1			T22	713		T23	27824		T25	89163
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1481350	1			T23	11485		T25	42320		T27	80
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1937684	1			T23	16959		T25	64520		T27	37
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	386957	1			T23	1082		T25	4797		T27	226
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1461380	1			T23	11460		T25	41608		T27	99
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5395143	1			T22	636		T23	43999		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3801249	1			T22	672		T23	27524		T25	89515
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1480657	1			T23	11955		T25	41146		T27	70
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1942903	1			T23	16764		T25	65465		T27	22
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	388021	1			T23	1144		T25	4899		T27	199
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1468278	1			T23	11495		T25	42759		T27	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5401690	1			T22	590		T23	43191		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3798289	1			T22	718		T23	27736		T25	89193
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1474221	1			T23	11635		T25	41229		T27	98
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1947290	1			T23	16861		T25	65099		T27	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	389550	1			T23	1203		T25	4912		T27	178
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1465211	1			T23	12255		T25	41728		T27	76
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5397767	1			T22	685		T23	44251		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3802066	1			T22	623		T23	27747		T25	89551
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1472211	1			T23	11742		T25	41997		T27	57
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1945782	1			T23	16513		T25	65023		T27	30
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	385844	1			T23	956		T25	5054		T27	302
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1472581	1			T23	11672		T25	42899		T27	20
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5403574	1			T22	667		T23	44122		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3797600	1			T22	641		T23	27365		T25	89448
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1475496	1			T23	11557		T25	42863		T27	70
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1946915	1			T23	17037		T25	63756		T27	35
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	386970	1			T23	1123		T25	4967		T27	232
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1465696	1			T23	11677		T25	42658		T27	69
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5399195	1			T22	624		T23	44163		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3799799	1			T22	684		T23	27598		T25	89561
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1481876	1			T23	11513		T25	42336		T27	88
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1942551	1			T23	17108		T25	64072		T27	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	387534	1			T23	1060		T25	4716		T27	193
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1465296	1			T23	11439		T25	41787		T27	84
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5398735	1			T22	708		T23	43740		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3801588	1			T22	600		T23	27624		T25	89660
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1475917	1			T23	11534		T25	41614		T27	60
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1949798	1			T23	17213		T25	64431		T27	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	388076	1			T23	1148		T25	4948		T27	274
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1462137	1			T23	11622		T25	42441		T27	63
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5401963	1			T22	610		T23	44155		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3798770	1			T22	698		T23	27771		T25	88988
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1478166	1			T23	11416		T25	41486		T27	58
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1946898	1			T23	16545		T25	64765		T27	25
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	388552	1			T23	1082		T25	4877		T27	227
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1461902	1			T23	11912		T25	41947		T27	83
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5406768	1			T22	664		T23	44051		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3800139	1			T22	644		T23	27755		T25	89653
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1477799	1			T23	11537		T25	41778		T27	103
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1947015	1			T23	17044		T25	64855		T27	25
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	387172	1			T23	1052		T25	4901		T27	236
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1457358	1			T23	11442		T25	42270		T27	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5404105	1			T22	680		T23	43742		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3790766	1			T22	628		T23	27577		T25	89530
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1478525	1			T23	11902		T25	42093		T27	100
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1949550	1			T23	16802		T25	63869		T27	22
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	389028	1			T23	1022		T25	4741		T27	147
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1464277	1			T23	11836		T25	41959		T27	73
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5395508	1			T22	681		T23	43779		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3804904	1			T22	627		T23	27495		T25	89465
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1476499	1			T23	11581		T25	41950		T27	91
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1946310	1			T23	17407		T25	64356		T27	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	387624	1			T23	1169		T25	4701		T27	211
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1465406	1			T23	11450		T25	41404		T27	83

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal