Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[1]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[2]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[3]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[4]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[5]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[6]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[7]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[8]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[9]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[10]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[11]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[12]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[13]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[14]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[15]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[16]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[17]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[18]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[19]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[20]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[21]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[22]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[23]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[24]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[25]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[26]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[27]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[28]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[29]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[30]	14476251	1			T22	1308		T23	112881		T24	1
bins_for_gpio_bits[31]	14476251	1			T22	1308		T23	112881		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282377663

1

T22

20838

T23

232301

T24

32

auto[1]

180862369

1

T22

21018

T23

128918

T25

436300

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282368551

1

T22

20838

T23

232274

T24

32

auto[1]

180871481

1

T22

21018

T23

128945

T25

436306

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8564949	1			T22	643		T23	70616		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	262699	1			T23	2063		T25	7503		T27	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	263001	1			T23	2073		T25	7504		T27	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	5385602	1			T22	665		T23	38129		T25	128866
bins_for_gpio_bits[1]	auto[0]	auto[0]	8567484	1			T22	698		T23	70790		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	262820	1			T23	2025		T25	7426		T27	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	263120	1			T23	2035		T25	7430		T27	8
bins_for_gpio_bits[1]	auto[1]	auto[1]	5382827	1			T22	610		T23	38031		T25	129029
bins_for_gpio_bits[2]	auto[0]	auto[0]	8562642	1			T22	703		T23	70589		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	262688	1			T23	1945		T25	7394		T27	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	262958	1			T23	1955		T25	7396		T27	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	5387963	1			T22	605		T23	38392		T25	128860
bins_for_gpio_bits[3]	auto[0]	auto[0]	8560628	1			T22	595		T23	69824		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	262470	1			T23	2148		T25	7452		T27	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	262753	1			T23	2155		T25	7453		T27	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	5390400	1			T22	713		T23	38754		T25	128912
bins_for_gpio_bits[4]	auto[0]	auto[0]	8563918	1			T22	611		T23	70971		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	262507	1			T23	2041		T25	7413		T27	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	262822	1			T23	2047		T25	7416		T27	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	5387004	1			T22	697		T23	37822		T25	129860
bins_for_gpio_bits[5]	auto[0]	auto[0]	8558266	1			T22	608		T23	70169		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	263004	1			T23	2050		T25	7328		T27	11
bins_for_gpio_bits[5]	auto[1]	auto[0]	263260	1			T23	2061		T25	7328		T27	11
bins_for_gpio_bits[5]	auto[1]	auto[1]	5391721	1			T22	700		T23	38601		T25	127974
bins_for_gpio_bits[6]	auto[0]	auto[0]	8566920	1			T22	661		T23	71247		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	262734	1			T23	1958		T25	7407		T27	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	263065	1			T23	1964		T25	7408		T27	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	5383532	1			T22	647		T23	37712		T25	129148
bins_for_gpio_bits[7]	auto[0]	auto[0]	8557169	1			T22	631		T23	70788		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	263253	1			T23	2047		T25	7453		T27	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	263482	1			T23	2055		T25	7453		T27	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	5392347	1			T22	677		T23	37991		T25	129428
bins_for_gpio_bits[8]	auto[0]	auto[0]	8554322	1			T22	645		T23	70497		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	262628	1			T23	2088		T25	7369		T27	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	262917	1			T23	2099		T25	7371		T27	9
bins_for_gpio_bits[8]	auto[1]	auto[1]	5396384	1			T22	663		T23	38197		T25	129027
bins_for_gpio_bits[9]	auto[0]	auto[0]	8554457	1			T22	620		T23	70486		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	262243	1			T23	2069		T25	7466		T27	13
bins_for_gpio_bits[9]	auto[1]	auto[0]	262534	1			T23	2078		T25	7467		T27	13
bins_for_gpio_bits[9]	auto[1]	auto[1]	5397017	1			T22	688		T23	38248		T25	129719
bins_for_gpio_bits[10]	auto[0]	auto[0]	8561974	1			T22	761		T23	71248		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	262980	1			T23	2004		T25	7482		T27	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	263278	1			T23	2010		T25	7486		T27	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	5388019	1			T22	547		T23	37619		T25	129448
bins_for_gpio_bits[11]	auto[0]	auto[0]	8557811	1			T22	642		T23	70181		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	262172	1			T23	2068		T25	7343		T27	15
bins_for_gpio_bits[11]	auto[1]	auto[0]	262439	1			T23	2078		T25	7343		T27	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	5393829	1			T22	666		T23	38554		T25	128400
bins_for_gpio_bits[12]	auto[0]	auto[0]	8556702	1			T22	588		T23	70775		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	262169	1			T23	2031		T25	7465		T27	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	262467	1			T23	2045		T25	7466		T27	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	5394913	1			T22	720		T23	38030		T25	129652
bins_for_gpio_bits[13]	auto[0]	auto[0]	8562548	1			T22	686		T23	70583		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	262768	1			T23	2036		T25	7398		T27	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	263051	1			T23	2045		T25	7401		T27	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	5387884	1			T22	622		T23	38217		T25	129158
bins_for_gpio_bits[14]	auto[0]	auto[0]	8556528	1			T22	659		T23	70912		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	262541	1			T23	2081		T25	7370		T27	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	262805	1			T23	2092		T25	7371		T27	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5394377	1			T22	649		T23	37796		T25	129050
bins_for_gpio_bits[15]	auto[0]	auto[0]	8562472	1			T22	739		T23	70437		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	262458	1			T23	2021		T25	7349		T27	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	262763	1			T23	2028		T25	7352		T27	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	5388558	1			T22	569		T23	38395		T25	128557
bins_for_gpio_bits[16]	auto[0]	auto[0]	8567767	1			T22	627		T23	70433		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	262729	1			T23	2129		T25	7370		T27	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	262973	1			T23	2134		T25	7373		T27	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	5382782	1			T22	681		T23	38185		T25	129088
bins_for_gpio_bits[17]	auto[0]	auto[0]	8559298	1			T22	660		T23	70045		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	262548	1			T23	2135		T25	7316		T27	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	262838	1			T23	2145		T25	7318		T27	18
bins_for_gpio_bits[17]	auto[1]	auto[1]	5391567	1			T22	648		T23	38556		T25	128237
bins_for_gpio_bits[18]	auto[0]	auto[0]	8561841	1			T22	709		T23	70730		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	262204	1			T23	2063		T25	7346		T27	13
bins_for_gpio_bits[18]	auto[1]	auto[0]	262483	1			T23	2072		T25	7348		T27	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	5389723	1			T22	599		T23	38016		T25	127757
bins_for_gpio_bits[19]	auto[0]	auto[0]	8562423	1			T22	586		T23	70658		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	262267	1			T23	2064		T25	7381		T27	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	262525	1			T23	2073		T25	7382		T27	11
bins_for_gpio_bits[19]	auto[1]	auto[1]	5389036	1			T22	722		T23	38086		T25	128748
bins_for_gpio_bits[20]	auto[0]	auto[0]	8563924	1			T22	626		T23	70388		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	262963	1			T23	2016		T25	7382		T27	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	263258	1			T23	2027		T25	7382		T27	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	5386106	1			T22	682		T23	38450		T25	127974
bins_for_gpio_bits[21]	auto[0]	auto[0]	8569480	1			T22	595		T23	70436		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	262242	1			T23	2072		T25	7408		T27	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	262521	1			T23	2079		T25	7411		T27	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	5382008	1			T22	713		T23	38294		T25	128160
bins_for_gpio_bits[22]	auto[0]	auto[0]	8555891	1			T22	636		T23	70683		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	262529	1			T23	2025		T25	7413		T27	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	262812	1			T23	2035		T25	7414		T27	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	5395019	1			T22	672		T23	38138		T25	129760
bins_for_gpio_bits[23]	auto[0]	auto[0]	8560353	1			T22	590		T23	69573		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	262530	1			T23	2108		T25	7427		T27	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	262848	1			T23	2114		T25	7430		T27	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	5390520	1			T22	718		T23	39086		T25	128406
bins_for_gpio_bits[24]	auto[0]	auto[0]	8552533	1			T22	685		T23	70512		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	262894	1			T23	1986		T25	7454		T27	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	263227	1			T23	1994		T25	7454		T27	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	5397597	1			T22	623		T23	38389		T25	130050
bins_for_gpio_bits[25]	auto[0]	auto[0]	8562756	1			T22	667		T23	70629		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	262977	1			T23	2079		T25	7462		T27	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	263229	1			T23	2087		T25	7464		T27	11
bins_for_gpio_bits[25]	auto[1]	auto[1]	5387289	1			T22	641		T23	38086		T25	129611
bins_for_gpio_bits[26]	auto[0]	auto[0]	8560717	1			T22	624		T23	70752		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	262649	1			T23	2019		T25	7314		T27	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	262905	1			T23	2032		T25	7315		T27	17
bins_for_gpio_bits[26]	auto[1]	auto[1]	5389980	1			T22	684		T23	38078		T25	128750
bins_for_gpio_bits[27]	auto[0]	auto[0]	8561840	1			T22	708		T23	70397		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	262336	1			T23	2082		T25	7452		T27	11
bins_for_gpio_bits[27]	auto[1]	auto[0]	262610	1			T23	2090		T25	7455		T27	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	5389465	1			T22	600		T23	38312		T25	129597
bins_for_gpio_bits[28]	auto[0]	auto[0]	8564080	1			T22	610		T23	70027		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	262631	1			T23	2083		T25	7419		T27	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	262947	1			T23	2089		T25	7420		T27	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5386593	1			T22	698		T23	38682		T25	128393
bins_for_gpio_bits[29]	auto[0]	auto[0]	8569292	1			T22	664		T23	70567		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	261997	1			T23	2059		T25	7401		T27	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	262290	1			T23	2065		T25	7403		T27	18
bins_for_gpio_bits[29]	auto[1]	auto[1]	5382672	1			T22	644		T23	38190		T25	129423
bins_for_gpio_bits[30]	auto[0]	auto[0]	8568979	1			T22	680		T23	70357		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	262918	1			T23	2084		T25	7420		T27	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	263201	1			T23	2089		T25	7423		T27	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	5381153	1			T22	628		T23	38351		T25	128810
bins_for_gpio_bits[31]	auto[0]	auto[0]	8555540	1			T22	681		T23	70719		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	262499	1			T23	2042		T25	7411		T27	11
bins_for_gpio_bits[31]	auto[1]	auto[0]	262777	1			T23	2048		T25	7412		T27	11
bins_for_gpio_bits[31]	auto[1]	auto[1]	5395435	1			T22	627		T23	38072		T25	128159