Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8389813 |
1 |
|
|
T22 |
1308 |
|
T23 |
65470 |
|
T24 |
1 |
| auto[1] |
6253079 |
1 |
|
|
T23 |
52626 |
|
T25 |
196652 |
|
T1 |
40829 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13855460 |
1 |
|
|
T22 |
1308 |
|
T23 |
111168 |
|
T24 |
1 |
| auto[1] |
787432 |
1 |
|
|
T23 |
6928 |
|
T25 |
26213 |
|
T1 |
4877 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426050 |
1 |
|
|
T22 |
1308 |
|
T23 |
66588 |
|
T24 |
1 |
| auto[1] |
6216842 |
1 |
|
|
T23 |
51508 |
|
T25 |
198759 |
|
T1 |
38436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2725708 |
1 |
|
|
T23 |
22126 |
|
T25 |
88510 |
|
T1 |
17012 |
| auto[1] |
auto[0] |
auto[1] |
395345 |
1 |
|
|
T23 |
3485 |
|
T25 |
13406 |
|
T1 |
2455 |
| auto[1] |
auto[1] |
auto[0] |
2703702 |
1 |
|
|
T23 |
22454 |
|
T25 |
84036 |
|
T1 |
16547 |
| auto[1] |
auto[1] |
auto[1] |
392087 |
1 |
|
|
T23 |
3443 |
|
T25 |
12807 |
|
T1 |
2422 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349911 |
1 |
|
|
T22 |
1308 |
|
T23 |
64984 |
|
T24 |
1 |
| auto[1] |
6292981 |
1 |
|
|
T23 |
53112 |
|
T25 |
206102 |
|
T1 |
39963 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13848569 |
1 |
|
|
T22 |
1308 |
|
T23 |
111231 |
|
T24 |
1 |
| auto[1] |
794323 |
1 |
|
|
T23 |
6865 |
|
T25 |
26629 |
|
T1 |
5301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8377192 |
1 |
|
|
T22 |
1308 |
|
T23 |
64894 |
|
T24 |
1 |
| auto[1] |
6265700 |
1 |
|
|
T23 |
53202 |
|
T25 |
202686 |
|
T1 |
40865 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2719823 |
1 |
|
|
T23 |
22859 |
|
T25 |
86802 |
|
T1 |
18156 |
| auto[1] |
auto[0] |
auto[1] |
394071 |
1 |
|
|
T23 |
3449 |
|
T25 |
13112 |
|
T1 |
2738 |
| auto[1] |
auto[1] |
auto[0] |
2751554 |
1 |
|
|
T23 |
23478 |
|
T25 |
89255 |
|
T1 |
17408 |
| auto[1] |
auto[1] |
auto[1] |
400252 |
1 |
|
|
T23 |
3416 |
|
T25 |
13517 |
|
T1 |
2563 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8398217 |
1 |
|
|
T22 |
1308 |
|
T23 |
65436 |
|
T24 |
1 |
| auto[1] |
6244675 |
1 |
|
|
T23 |
52660 |
|
T25 |
209919 |
|
T1 |
39525 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13849005 |
1 |
|
|
T22 |
1308 |
|
T23 |
111453 |
|
T24 |
1 |
| auto[1] |
793887 |
1 |
|
|
T23 |
6643 |
|
T25 |
25105 |
|
T1 |
5200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8379998 |
1 |
|
|
T22 |
1308 |
|
T23 |
67422 |
|
T24 |
1 |
| auto[1] |
6262894 |
1 |
|
|
T23 |
50674 |
|
T25 |
193700 |
|
T1 |
39583 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2753752 |
1 |
|
|
T23 |
21179 |
|
T25 |
80311 |
|
T1 |
18134 |
| auto[1] |
auto[0] |
auto[1] |
400027 |
1 |
|
|
T23 |
3236 |
|
T25 |
11820 |
|
T1 |
2732 |
| auto[1] |
auto[1] |
auto[0] |
2715255 |
1 |
|
|
T23 |
22852 |
|
T25 |
88284 |
|
T1 |
16249 |
| auto[1] |
auto[1] |
auto[1] |
393860 |
1 |
|
|
T23 |
3407 |
|
T25 |
13285 |
|
T1 |
2468 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8382536 |
1 |
|
|
T22 |
1308 |
|
T23 |
63427 |
|
T24 |
1 |
| auto[1] |
6260356 |
1 |
|
|
T23 |
54669 |
|
T25 |
204525 |
|
T1 |
40357 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13849744 |
1 |
|
|
T22 |
1308 |
|
T23 |
111384 |
|
T24 |
1 |
| auto[1] |
793148 |
1 |
|
|
T23 |
6712 |
|
T25 |
28126 |
|
T1 |
5428 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8378001 |
1 |
|
|
T22 |
1308 |
|
T23 |
67519 |
|
T24 |
1 |
| auto[1] |
6264891 |
1 |
|
|
T23 |
50577 |
|
T25 |
212088 |
|
T1 |
41445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2733319 |
1 |
|
|
T23 |
20796 |
|
T25 |
89119 |
|
T1 |
18460 |
| auto[1] |
auto[0] |
auto[1] |
396535 |
1 |
|
|
T23 |
3194 |
|
T25 |
13392 |
|
T1 |
2877 |
| auto[1] |
auto[1] |
auto[0] |
2738424 |
1 |
|
|
T23 |
23069 |
|
T25 |
94843 |
|
T1 |
17557 |
| auto[1] |
auto[1] |
auto[1] |
396613 |
1 |
|
|
T23 |
3518 |
|
T25 |
14734 |
|
T1 |
2551 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8374049 |
1 |
|
|
T22 |
1308 |
|
T23 |
65288 |
|
T24 |
1 |
| auto[1] |
6268843 |
1 |
|
|
T23 |
52808 |
|
T25 |
201374 |
|
T1 |
39778 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13850570 |
1 |
|
|
T22 |
1308 |
|
T23 |
111463 |
|
T24 |
1 |
| auto[1] |
792322 |
1 |
|
|
T23 |
6633 |
|
T25 |
25021 |
|
T1 |
5234 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8384584 |
1 |
|
|
T22 |
1308 |
|
T23 |
66841 |
|
T24 |
1 |
| auto[1] |
6258308 |
1 |
|
|
T23 |
51255 |
|
T25 |
192795 |
|
T1 |
40049 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2729097 |
1 |
|
|
T23 |
22232 |
|
T25 |
83651 |
|
T1 |
17800 |
| auto[1] |
auto[0] |
auto[1] |
395830 |
1 |
|
|
T23 |
3322 |
|
T25 |
12448 |
|
T1 |
2596 |
| auto[1] |
auto[1] |
auto[0] |
2736889 |
1 |
|
|
T23 |
22390 |
|
T25 |
84123 |
|
T1 |
17015 |
| auto[1] |
auto[1] |
auto[1] |
396492 |
1 |
|
|
T23 |
3311 |
|
T25 |
12573 |
|
T1 |
2638 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365330 |
1 |
|
|
T22 |
1308 |
|
T23 |
63251 |
|
T24 |
1 |
| auto[1] |
6277562 |
1 |
|
|
T23 |
54845 |
|
T25 |
200829 |
|
T1 |
40513 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13846215 |
1 |
|
|
T22 |
1308 |
|
T23 |
111257 |
|
T24 |
1 |
| auto[1] |
796677 |
1 |
|
|
T23 |
6839 |
|
T25 |
26473 |
|
T1 |
5263 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8358114 |
1 |
|
|
T22 |
1308 |
|
T23 |
66313 |
|
T24 |
1 |
| auto[1] |
6284778 |
1 |
|
|
T23 |
51783 |
|
T25 |
200158 |
|
T1 |
40610 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2729913 |
1 |
|
|
T23 |
21710 |
|
T25 |
87161 |
|
T1 |
16065 |
| auto[1] |
auto[0] |
auto[1] |
395971 |
1 |
|
|
T23 |
3287 |
|
T25 |
13344 |
|
T1 |
2226 |
| auto[1] |
auto[1] |
auto[0] |
2758188 |
1 |
|
|
T23 |
23234 |
|
T25 |
86524 |
|
T1 |
19282 |
| auto[1] |
auto[1] |
auto[1] |
400706 |
1 |
|
|
T23 |
3552 |
|
T25 |
13129 |
|
T1 |
3037 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8333423 |
1 |
|
|
T22 |
1308 |
|
T23 |
66086 |
|
T24 |
1 |
| auto[1] |
6309469 |
1 |
|
|
T23 |
52010 |
|
T25 |
201478 |
|
T1 |
39502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13850577 |
1 |
|
|
T22 |
1308 |
|
T23 |
110856 |
|
T24 |
1 |
| auto[1] |
792315 |
1 |
|
|
T23 |
7240 |
|
T25 |
25444 |
|
T1 |
5346 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8382728 |
1 |
|
|
T22 |
1308 |
|
T23 |
63369 |
|
T24 |
1 |
| auto[1] |
6260164 |
1 |
|
|
T23 |
54727 |
|
T25 |
194379 |
|
T1 |
41093 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2715296 |
1 |
|
|
T23 |
24599 |
|
T25 |
83799 |
|
T1 |
18768 |
| auto[1] |
auto[0] |
auto[1] |
392601 |
1 |
|
|
T23 |
3736 |
|
T25 |
12600 |
|
T1 |
2794 |
| auto[1] |
auto[1] |
auto[0] |
2752553 |
1 |
|
|
T23 |
22888 |
|
T25 |
85136 |
|
T1 |
16979 |
| auto[1] |
auto[1] |
auto[1] |
399714 |
1 |
|
|
T23 |
3504 |
|
T25 |
12844 |
|
T1 |
2552 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8382235 |
1 |
|
|
T22 |
1308 |
|
T23 |
65888 |
|
T24 |
1 |
| auto[1] |
6260657 |
1 |
|
|
T23 |
52208 |
|
T25 |
197870 |
|
T1 |
36716 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13847046 |
1 |
|
|
T22 |
1308 |
|
T23 |
111079 |
|
T24 |
1 |
| auto[1] |
795846 |
1 |
|
|
T23 |
7017 |
|
T25 |
26988 |
|
T1 |
5185 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8359469 |
1 |
|
|
T22 |
1308 |
|
T23 |
64973 |
|
T24 |
1 |
| auto[1] |
6283423 |
1 |
|
|
T23 |
53123 |
|
T25 |
203746 |
|
T1 |
40664 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2733582 |
1 |
|
|
T23 |
23097 |
|
T25 |
90519 |
|
T1 |
18741 |
| auto[1] |
auto[0] |
auto[1] |
396368 |
1 |
|
|
T23 |
3537 |
|
T25 |
13886 |
|
T1 |
2756 |
| auto[1] |
auto[1] |
auto[0] |
2753995 |
1 |
|
|
T23 |
23009 |
|
T25 |
86239 |
|
T1 |
16738 |
| auto[1] |
auto[1] |
auto[1] |
399478 |
1 |
|
|
T23 |
3480 |
|
T25 |
13102 |
|
T1 |
2429 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8374398 |
1 |
|
|
T22 |
1308 |
|
T23 |
64794 |
|
T24 |
1 |
| auto[1] |
6268494 |
1 |
|
|
T23 |
53302 |
|
T25 |
199245 |
|
T1 |
40374 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13848634 |
1 |
|
|
T22 |
1308 |
|
T23 |
111475 |
|
T24 |
1 |
| auto[1] |
794258 |
1 |
|
|
T23 |
6621 |
|
T25 |
26426 |
|
T1 |
5163 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8373524 |
1 |
|
|
T22 |
1308 |
|
T23 |
67425 |
|
T24 |
1 |
| auto[1] |
6269368 |
1 |
|
|
T23 |
50671 |
|
T25 |
202681 |
|
T1 |
40349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2743807 |
1 |
|
|
T23 |
21972 |
|
T25 |
89622 |
|
T1 |
17403 |
| auto[1] |
auto[0] |
auto[1] |
397709 |
1 |
|
|
T23 |
3376 |
|
T25 |
13522 |
|
T1 |
2570 |
| auto[1] |
auto[1] |
auto[0] |
2731303 |
1 |
|
|
T23 |
22078 |
|
T25 |
86633 |
|
T1 |
17783 |
| auto[1] |
auto[1] |
auto[1] |
396549 |
1 |
|
|
T23 |
3245 |
|
T25 |
12904 |
|
T1 |
2593 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8366599 |
1 |
|
|
T22 |
1308 |
|
T23 |
67046 |
|
T24 |
1 |
| auto[1] |
6276293 |
1 |
|
|
T23 |
51050 |
|
T25 |
199443 |
|
T1 |
39866 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13848815 |
1 |
|
|
T22 |
1308 |
|
T23 |
111408 |
|
T24 |
1 |
| auto[1] |
794077 |
1 |
|
|
T23 |
6688 |
|
T25 |
26725 |
|
T1 |
5301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8375212 |
1 |
|
|
T22 |
1308 |
|
T23 |
66697 |
|
T24 |
1 |
| auto[1] |
6267680 |
1 |
|
|
T23 |
51399 |
|
T25 |
203611 |
|
T1 |
40578 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2732277 |
1 |
|
|
T23 |
22543 |
|
T25 |
90294 |
|
T1 |
18036 |
| auto[1] |
auto[0] |
auto[1] |
396241 |
1 |
|
|
T23 |
3349 |
|
T25 |
13581 |
|
T1 |
2698 |
| auto[1] |
auto[1] |
auto[0] |
2741326 |
1 |
|
|
T23 |
22168 |
|
T25 |
86592 |
|
T1 |
17241 |
| auto[1] |
auto[1] |
auto[1] |
397836 |
1 |
|
|
T23 |
3339 |
|
T25 |
13144 |
|
T1 |
2603 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435686 |
1 |
|
|
T22 |
1308 |
|
T23 |
62582 |
|
T24 |
1 |
| auto[1] |
6207206 |
1 |
|
|
T23 |
55514 |
|
T25 |
195427 |
|
T1 |
38449 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13843192 |
1 |
|
|
T22 |
1308 |
|
T23 |
111190 |
|
T24 |
1 |
| auto[1] |
799700 |
1 |
|
|
T23 |
6906 |
|
T25 |
26296 |
|
T1 |
5575 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8337994 |
1 |
|
|
T22 |
1308 |
|
T23 |
65937 |
|
T24 |
1 |
| auto[1] |
6304898 |
1 |
|
|
T23 |
52159 |
|
T25 |
199773 |
|
T1 |
42148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2781003 |
1 |
|
|
T23 |
21772 |
|
T25 |
89185 |
|
T1 |
18193 |
| auto[1] |
auto[0] |
auto[1] |
404585 |
1 |
|
|
T23 |
3249 |
|
T25 |
13589 |
|
T1 |
2751 |
| auto[1] |
auto[1] |
auto[0] |
2724195 |
1 |
|
|
T23 |
23481 |
|
T25 |
84292 |
|
T1 |
18380 |
| auto[1] |
auto[1] |
auto[1] |
395115 |
1 |
|
|
T23 |
3657 |
|
T25 |
12707 |
|
T1 |
2824 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8356056 |
1 |
|
|
T22 |
1308 |
|
T23 |
63892 |
|
T24 |
1 |
| auto[1] |
6286836 |
1 |
|
|
T23 |
54204 |
|
T25 |
199669 |
|
T1 |
39245 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13854706 |
1 |
|
|
T22 |
1308 |
|
T23 |
111555 |
|
T24 |
1 |
| auto[1] |
788186 |
1 |
|
|
T23 |
6541 |
|
T25 |
26333 |
|
T1 |
5058 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8409198 |
1 |
|
|
T22 |
1308 |
|
T23 |
67626 |
|
T24 |
1 |
| auto[1] |
6233694 |
1 |
|
|
T23 |
50470 |
|
T25 |
201324 |
|
T1 |
39127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2713004 |
1 |
|
|
T23 |
20961 |
|
T25 |
87671 |
|
T1 |
15946 |
| auto[1] |
auto[0] |
auto[1] |
391891 |
1 |
|
|
T23 |
3113 |
|
T25 |
13354 |
|
T1 |
2272 |
| auto[1] |
auto[1] |
auto[0] |
2732504 |
1 |
|
|
T23 |
22968 |
|
T25 |
87320 |
|
T1 |
18123 |
| auto[1] |
auto[1] |
auto[1] |
396295 |
1 |
|
|
T23 |
3428 |
|
T25 |
12979 |
|
T1 |
2786 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8369616 |
1 |
|
|
T22 |
1308 |
|
T23 |
65366 |
|
T24 |
1 |
| auto[1] |
6273276 |
1 |
|
|
T23 |
52730 |
|
T25 |
205689 |
|
T1 |
42626 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13846052 |
1 |
|
|
T22 |
1308 |
|
T23 |
111124 |
|
T24 |
1 |
| auto[1] |
796840 |
1 |
|
|
T23 |
6972 |
|
T25 |
26098 |
|
T1 |
5389 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8353041 |
1 |
|
|
T22 |
1308 |
|
T23 |
66003 |
|
T24 |
1 |
| auto[1] |
6289851 |
1 |
|
|
T23 |
52093 |
|
T25 |
199392 |
|
T1 |
41600 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756373 |
1 |
|
|
T23 |
22651 |
|
T25 |
85329 |
|
T1 |
16658 |
| auto[1] |
auto[0] |
auto[1] |
400159 |
1 |
|
|
T23 |
3426 |
|
T25 |
12606 |
|
T1 |
2422 |
| auto[1] |
auto[1] |
auto[0] |
2736638 |
1 |
|
|
T23 |
22470 |
|
T25 |
87965 |
|
T1 |
19553 |
| auto[1] |
auto[1] |
auto[1] |
396681 |
1 |
|
|
T23 |
3546 |
|
T25 |
13492 |
|
T1 |
2967 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355163 |
1 |
|
|
T22 |
1308 |
|
T23 |
64059 |
|
T24 |
1 |
| auto[1] |
6287729 |
1 |
|
|
T23 |
54037 |
|
T25 |
203318 |
|
T1 |
41201 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13846185 |
1 |
|
|
T22 |
1308 |
|
T23 |
111021 |
|
T24 |
1 |
| auto[1] |
796707 |
1 |
|
|
T23 |
7075 |
|
T25 |
26714 |
|
T1 |
4581 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8357694 |
1 |
|
|
T22 |
1308 |
|
T23 |
64729 |
|
T24 |
1 |
| auto[1] |
6285198 |
1 |
|
|
T23 |
53367 |
|
T25 |
204439 |
|
T1 |
36454 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2744053 |
1 |
|
|
T23 |
22023 |
|
T25 |
84113 |
|
T1 |
16030 |
| auto[1] |
auto[0] |
auto[1] |
399042 |
1 |
|
|
T23 |
3301 |
|
T25 |
12364 |
|
T1 |
2361 |
| auto[1] |
auto[1] |
auto[0] |
2744438 |
1 |
|
|
T23 |
24269 |
|
T25 |
93612 |
|
T1 |
15843 |
| auto[1] |
auto[1] |
auto[1] |
397665 |
1 |
|
|
T23 |
3774 |
|
T25 |
14350 |
|
T1 |
2220 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8357784 |
1 |
|
|
T22 |
1308 |
|
T23 |
64533 |
|
T24 |
1 |
| auto[1] |
6285108 |
1 |
|
|
T23 |
53563 |
|
T25 |
200659 |
|
T1 |
40730 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13855706 |
1 |
|
|
T22 |
1308 |
|
T23 |
111454 |
|
T24 |
1 |
| auto[1] |
787186 |
1 |
|
|
T23 |
6642 |
|
T25 |
25324 |
|
T1 |
5211 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8421888 |
1 |
|
|
T22 |
1308 |
|
T23 |
66489 |
|
T24 |
1 |
| auto[1] |
6221004 |
1 |
|
|
T23 |
51607 |
|
T25 |
194205 |
|
T1 |
39362 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2712270 |
1 |
|
|
T23 |
22179 |
|
T25 |
85266 |
|
T1 |
15911 |
| auto[1] |
auto[0] |
auto[1] |
392966 |
1 |
|
|
T23 |
3267 |
|
T25 |
12723 |
|
T1 |
2379 |
| auto[1] |
auto[1] |
auto[0] |
2721548 |
1 |
|
|
T23 |
22786 |
|
T25 |
83615 |
|
T1 |
18240 |
| auto[1] |
auto[1] |
auto[1] |
394220 |
1 |
|
|
T23 |
3375 |
|
T25 |
12601 |
|
T1 |
2832 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8362085 |
1 |
|
|
T22 |
1308 |
|
T23 |
67119 |
|
T24 |
1 |
| auto[1] |
6280807 |
1 |
|
|
T23 |
50977 |
|
T25 |
199879 |
|
T1 |
38560 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13845254 |
1 |
|
|
T22 |
1308 |
|
T23 |
111252 |
|
T24 |
1 |
| auto[1] |
797638 |
1 |
|
|
T23 |
6844 |
|
T25 |
26437 |
|
T1 |
5413 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8353635 |
1 |
|
|
T22 |
1308 |
|
T23 |
65824 |
|
T24 |
1 |
| auto[1] |
6289257 |
1 |
|
|
T23 |
52272 |
|
T25 |
202104 |
|
T1 |
41294 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2726979 |
1 |
|
|
T23 |
23536 |
|
T25 |
86799 |
|
T1 |
19098 |
| auto[1] |
auto[0] |
auto[1] |
395409 |
1 |
|
|
T23 |
3506 |
|
T25 |
13174 |
|
T1 |
3005 |
| auto[1] |
auto[1] |
auto[0] |
2764640 |
1 |
|
|
T23 |
21892 |
|
T25 |
88868 |
|
T1 |
16783 |
| auto[1] |
auto[1] |
auto[1] |
402229 |
1 |
|
|
T23 |
3338 |
|
T25 |
13263 |
|
T1 |
2408 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365152 |
1 |
|
|
T22 |
1308 |
|
T23 |
64168 |
|
T24 |
1 |
| auto[1] |
6277740 |
1 |
|
|
T23 |
53928 |
|
T25 |
200401 |
|
T1 |
39718 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13846769 |
1 |
|
|
T22 |
1308 |
|
T23 |
111057 |
|
T24 |
1 |
| auto[1] |
796123 |
1 |
|
|
T23 |
7039 |
|
T25 |
26452 |
|
T1 |
4797 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8362617 |
1 |
|
|
T22 |
1308 |
|
T23 |
64600 |
|
T24 |
1 |
| auto[1] |
6280275 |
1 |
|
|
T23 |
53496 |
|
T25 |
201168 |
|
T1 |
37828 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2739390 |
1 |
|
|
T23 |
22702 |
|
T25 |
88718 |
|
T1 |
17401 |
| auto[1] |
auto[0] |
auto[1] |
396101 |
1 |
|
|
T23 |
3403 |
|
T25 |
13569 |
|
T1 |
2638 |
| auto[1] |
auto[1] |
auto[0] |
2744762 |
1 |
|
|
T23 |
23755 |
|
T25 |
85998 |
|
T1 |
15630 |
| auto[1] |
auto[1] |
auto[1] |
400022 |
1 |
|
|
T23 |
3636 |
|
T25 |
12883 |
|
T1 |
2159 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8395255 |
1 |
|
|
T22 |
1308 |
|
T23 |
66407 |
|
T24 |
1 |
| auto[1] |
6247637 |
1 |
|
|
T23 |
51689 |
|
T25 |
201892 |
|
T1 |
38659 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13846266 |
1 |
|
|
T22 |
1308 |
|
T23 |
111055 |
|
T24 |
1 |
| auto[1] |
796626 |
1 |
|
|
T23 |
7041 |
|
T25 |
25484 |
|
T1 |
5144 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8358268 |
1 |
|
|
T22 |
1308 |
|
T23 |
65013 |
|
T24 |
1 |
| auto[1] |
6284624 |
1 |
|
|
T23 |
53083 |
|
T25 |
195175 |
|
T1 |
40457 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2743007 |
1 |
|
|
T23 |
22568 |
|
T25 |
84558 |
|
T1 |
18333 |
| auto[1] |
auto[0] |
auto[1] |
398125 |
1 |
|
|
T23 |
3441 |
|
T25 |
12862 |
|
T1 |
2725 |
| auto[1] |
auto[1] |
auto[0] |
2744991 |
1 |
|
|
T23 |
23474 |
|
T25 |
85133 |
|
T1 |
16980 |
| auto[1] |
auto[1] |
auto[1] |
398501 |
1 |
|
|
T23 |
3600 |
|
T25 |
12622 |
|
T1 |
2419 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8379671 |
1 |
|
|
T22 |
1308 |
|
T23 |
68544 |
|
T24 |
1 |
| auto[1] |
6263221 |
1 |
|
|
T23 |
49552 |
|
T25 |
201176 |
|
T1 |
40182 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13843783 |
1 |
|
|
T22 |
1308 |
|
T23 |
111173 |
|
T24 |
1 |
| auto[1] |
799109 |
1 |
|
|
T23 |
6923 |
|
T25 |
26981 |
|
T1 |
5032 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8341328 |
1 |
|
|
T22 |
1308 |
|
T23 |
65743 |
|
T24 |
1 |
| auto[1] |
6301564 |
1 |
|
|
T23 |
52353 |
|
T25 |
205111 |
|
T1 |
39462 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2753978 |
1 |
|
|
T23 |
24681 |
|
T25 |
85405 |
|
T1 |
18054 |
| auto[1] |
auto[0] |
auto[1] |
398476 |
1 |
|
|
T23 |
3896 |
|
T25 |
12545 |
|
T1 |
2698 |
| auto[1] |
auto[1] |
auto[0] |
2748477 |
1 |
|
|
T23 |
20749 |
|
T25 |
92725 |
|
T1 |
16376 |
| auto[1] |
auto[1] |
auto[1] |
400633 |
1 |
|
|
T23 |
3027 |
|
T25 |
14436 |
|
T1 |
2334 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380608 |
1 |
|
|
T22 |
1308 |
|
T23 |
64777 |
|
T24 |
1 |
| auto[1] |
6262284 |
1 |
|
|
T23 |
53319 |
|
T25 |
197600 |
|
T1 |
39375 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13847251 |
1 |
|
|
T22 |
1308 |
|
T23 |
110822 |
|
T24 |
1 |
| auto[1] |
795641 |
1 |
|
|
T23 |
7274 |
|
T25 |
26632 |
|
T1 |
5310 |