Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8359546 |
1 |
|
|
T22 |
1308 |
|
T23 |
65081 |
|
T24 |
1 |
auto[1] |
6283346 |
1 |
|
|
T23 |
53015 |
|
T25 |
204758 |
|
T1 |
39486 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13850819 |
1 |
|
|
T22 |
1308 |
|
T23 |
110887 |
|
T24 |
1 |
auto[1] |
792073 |
1 |
|
|
T23 |
7209 |
|
T25 |
25734 |
|
T1 |
5479 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8395454 |
1 |
|
|
T22 |
1308 |
|
T23 |
64430 |
|
T24 |
1 |
auto[1] |
6247438 |
1 |
|
|
T23 |
53666 |
|
T25 |
196608 |
|
T1 |
41538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2715249 |
1 |
|
|
T23 |
22575 |
|
T25 |
81887 |
|
T1 |
17488 |
auto[1] |
auto[0] |
auto[1] |
392979 |
1 |
|
|
T23 |
3473 |
|
T25 |
12077 |
|
T1 |
2606 |
auto[1] |
auto[1] |
auto[0] |
2740116 |
1 |
|
|
T23 |
23882 |
|
T25 |
88987 |
|
T1 |
18571 |
auto[1] |
auto[1] |
auto[1] |
399094 |
1 |
|
|
T23 |
3736 |
|
T25 |
13657 |
|
T1 |
2873 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |