Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403833 |
1 |
|
|
T22 |
1308 |
|
T23 |
65790 |
|
T24 |
1 |
| auto[1] |
6239059 |
1 |
|
|
T23 |
52306 |
|
T25 |
200307 |
|
T1 |
40119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13849942 |
1 |
|
|
T22 |
1308 |
|
T23 |
111294 |
|
T24 |
1 |
| auto[1] |
792950 |
1 |
|
|
T23 |
6802 |
|
T25 |
26618 |
|
T1 |
5290 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8384155 |
1 |
|
|
T22 |
1308 |
|
T23 |
66015 |
|
T24 |
1 |
| auto[1] |
6258737 |
1 |
|
|
T23 |
52081 |
|
T25 |
201527 |
|
T1 |
41301 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2759359 |
1 |
|
|
T23 |
22624 |
|
T25 |
87535 |
|
T1 |
18078 |
| auto[1] |
auto[0] |
auto[1] |
400220 |
1 |
|
|
T23 |
3372 |
|
T25 |
13418 |
|
T1 |
2694 |
| auto[1] |
auto[1] |
auto[0] |
2706428 |
1 |
|
|
T23 |
22655 |
|
T25 |
87374 |
|
T1 |
17933 |
| auto[1] |
auto[1] |
auto[1] |
392730 |
1 |
|
|
T23 |
3430 |
|
T25 |
13200 |
|
T1 |
2596 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |