Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349911 |
1 |
|
|
T22 |
1308 |
|
T23 |
64984 |
|
T24 |
1 |
| auto[1] |
6292981 |
1 |
|
|
T23 |
53112 |
|
T25 |
206102 |
|
T1 |
39963 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12131900 |
1 |
|
|
T22 |
1308 |
|
T23 |
97483 |
|
T24 |
1 |
| auto[1] |
2510992 |
1 |
|
|
T23 |
20613 |
|
T25 |
77725 |
|
T1 |
14335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8383701 |
1 |
|
|
T22 |
1308 |
|
T23 |
65668 |
|
T24 |
1 |
| auto[1] |
6259191 |
1 |
|
|
T23 |
52428 |
|
T25 |
203721 |
|
T1 |
37533 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1863582 |
1 |
|
|
T23 |
15390 |
|
T25 |
60990 |
|
T1 |
11318 |
| auto[1] |
auto[0] |
auto[1] |
1253263 |
1 |
|
|
T23 |
10112 |
|
T25 |
38783 |
|
T1 |
6935 |
| auto[1] |
auto[1] |
auto[0] |
1884617 |
1 |
|
|
T23 |
16425 |
|
T25 |
65006 |
|
T1 |
11880 |
| auto[1] |
auto[1] |
auto[1] |
1257729 |
1 |
|
|
T23 |
10501 |
|
T25 |
38942 |
|
T1 |
7400 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |