Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8398217 |
1 |
|
|
T22 |
1308 |
|
T23 |
65436 |
|
T24 |
1 |
| auto[1] |
6244675 |
1 |
|
|
T23 |
52660 |
|
T25 |
209919 |
|
T1 |
39525 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12129796 |
1 |
|
|
T22 |
1308 |
|
T23 |
98113 |
|
T24 |
1 |
| auto[1] |
2513096 |
1 |
|
|
T23 |
19983 |
|
T25 |
75021 |
|
T1 |
15520 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8378528 |
1 |
|
|
T22 |
1308 |
|
T23 |
65951 |
|
T24 |
1 |
| auto[1] |
6264364 |
1 |
|
|
T23 |
52145 |
|
T25 |
193417 |
|
T1 |
40054 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1886305 |
1 |
|
|
T23 |
16073 |
|
T25 |
55844 |
|
T1 |
12779 |
| auto[1] |
auto[0] |
auto[1] |
1262146 |
1 |
|
|
T23 |
10243 |
|
T25 |
36353 |
|
T1 |
7894 |
| auto[1] |
auto[1] |
auto[0] |
1864963 |
1 |
|
|
T23 |
16089 |
|
T25 |
62552 |
|
T1 |
11755 |
| auto[1] |
auto[1] |
auto[1] |
1250950 |
1 |
|
|
T23 |
9740 |
|
T25 |
38668 |
|
T1 |
7626 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |