Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8374049 |
1 |
|
|
T22 |
1308 |
|
T23 |
65288 |
|
T24 |
1 |
auto[1] |
6268843 |
1 |
|
|
T23 |
52808 |
|
T25 |
201374 |
|
T1 |
39778 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12126790 |
1 |
|
|
T22 |
1308 |
|
T23 |
97254 |
|
T24 |
1 |
auto[1] |
2516102 |
1 |
|
|
T23 |
20842 |
|
T25 |
78057 |
|
T1 |
14984 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8382910 |
1 |
|
|
T22 |
1308 |
|
T23 |
65663 |
|
T24 |
1 |
auto[1] |
6259982 |
1 |
|
|
T23 |
52433 |
|
T25 |
202684 |
|
T1 |
39721 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1870292 |
1 |
|
|
T23 |
16028 |
|
T25 |
62343 |
|
T1 |
12106 |
auto[1] |
auto[0] |
auto[1] |
1253145 |
1 |
|
|
T23 |
10617 |
|
T25 |
38172 |
|
T1 |
7288 |
auto[1] |
auto[1] |
auto[0] |
1873588 |
1 |
|
|
T23 |
15563 |
|
T25 |
62284 |
|
T1 |
12631 |
auto[1] |
auto[1] |
auto[1] |
1262957 |
1 |
|
|
T23 |
10225 |
|
T25 |
39885 |
|
T1 |
7696 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |