Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372854 |
1 |
|
|
T22 |
1308 |
|
T23 |
63220 |
|
T24 |
1 |
| auto[1] |
6270038 |
1 |
|
|
T23 |
54876 |
|
T25 |
203011 |
|
T1 |
40746 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2732201 |
1 |
|
|
T23 |
23409 |
|
T25 |
89728 |
|
T1 |
17721 |
| auto[1] |
auto[0] |
auto[1] |
397366 |
1 |
|
|
T23 |
3630 |
|
T25 |
13823 |
|
T1 |
2655 |
| auto[1] |
auto[1] |
auto[0] |
2742196 |
1 |
|
|
T23 |
24193 |
|
T25 |
86651 |
|
T1 |
17715 |
| auto[1] |
auto[1] |
auto[1] |
398275 |
1 |
|
|
T23 |
3644 |
|
T25 |
12809 |
|
T1 |
2655 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |