Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8333423 |
1 |
|
|
T22 |
1308 |
|
T23 |
66086 |
|
T24 |
1 |
| auto[1] |
6309469 |
1 |
|
|
T23 |
52010 |
|
T25 |
201478 |
|
T1 |
39502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12118837 |
1 |
|
|
T22 |
1308 |
|
T23 |
97706 |
|
T24 |
1 |
| auto[1] |
2524055 |
1 |
|
|
T23 |
20390 |
|
T25 |
76421 |
|
T1 |
14909 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8362648 |
1 |
|
|
T22 |
1308 |
|
T23 |
66624 |
|
T24 |
1 |
| auto[1] |
6280244 |
1 |
|
|
T23 |
51472 |
|
T25 |
198493 |
|
T1 |
39075 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1863893 |
1 |
|
|
T23 |
15913 |
|
T25 |
59874 |
|
T1 |
12840 |
| auto[1] |
auto[0] |
auto[1] |
1253675 |
1 |
|
|
T23 |
10286 |
|
T25 |
37611 |
|
T1 |
7769 |
| auto[1] |
auto[1] |
auto[0] |
1892296 |
1 |
|
|
T23 |
15169 |
|
T25 |
62198 |
|
T1 |
11326 |
| auto[1] |
auto[1] |
auto[1] |
1270380 |
1 |
|
|
T23 |
10104 |
|
T25 |
38810 |
|
T1 |
7140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |