Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8374398 |
1 |
|
|
T22 |
1308 |
|
T23 |
64794 |
|
T24 |
1 |
auto[1] |
6268494 |
1 |
|
|
T23 |
53302 |
|
T25 |
199245 |
|
T1 |
40374 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12115632 |
1 |
|
|
T22 |
1308 |
|
T23 |
97133 |
|
T24 |
1 |
auto[1] |
2527260 |
1 |
|
|
T23 |
20963 |
|
T25 |
77554 |
|
T1 |
14643 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8342970 |
1 |
|
|
T22 |
1308 |
|
T23 |
66137 |
|
T24 |
1 |
auto[1] |
6299922 |
1 |
|
|
T23 |
51959 |
|
T25 |
202949 |
|
T1 |
38905 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1897438 |
1 |
|
|
T23 |
15189 |
|
T25 |
61639 |
|
T1 |
12455 |
auto[1] |
auto[0] |
auto[1] |
1265603 |
1 |
|
|
T23 |
10537 |
|
T25 |
38233 |
|
T1 |
7358 |
auto[1] |
auto[1] |
auto[0] |
1875224 |
1 |
|
|
T23 |
15807 |
|
T25 |
63756 |
|
T1 |
11807 |
auto[1] |
auto[1] |
auto[1] |
1261657 |
1 |
|
|
T23 |
10426 |
|
T25 |
39321 |
|
T1 |
7285 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |