Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8357784 |
1 |
|
|
T22 |
1308 |
|
T23 |
64533 |
|
T24 |
1 |
auto[1] |
6285108 |
1 |
|
|
T23 |
53563 |
|
T25 |
200659 |
|
T1 |
40730 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12134730 |
1 |
|
|
T22 |
1308 |
|
T23 |
97546 |
|
T24 |
1 |
auto[1] |
2508162 |
1 |
|
|
T23 |
20550 |
|
T25 |
78710 |
|
T1 |
15080 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8370006 |
1 |
|
|
T22 |
1308 |
|
T23 |
65539 |
|
T24 |
1 |
auto[1] |
6272886 |
1 |
|
|
T23 |
52557 |
|
T25 |
206797 |
|
T1 |
41022 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1874515 |
1 |
|
|
T23 |
15982 |
|
T25 |
66715 |
|
T1 |
12861 |
auto[1] |
auto[0] |
auto[1] |
1248788 |
1 |
|
|
T23 |
10062 |
|
T25 |
40210 |
|
T1 |
7486 |
auto[1] |
auto[1] |
auto[0] |
1890209 |
1 |
|
|
T23 |
16025 |
|
T25 |
61372 |
|
T1 |
13081 |
auto[1] |
auto[1] |
auto[1] |
1259374 |
1 |
|
|
T23 |
10488 |
|
T25 |
38500 |
|
T1 |
7594 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |