Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8334008 |
1 |
|
|
T22 |
1308 |
|
T23 |
65988 |
|
T24 |
1 |
auto[1] |
6308884 |
1 |
|
|
T23 |
52108 |
|
T25 |
193892 |
|
T1 |
39750 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13846238 |
1 |
|
|
T22 |
1308 |
|
T23 |
111180 |
|
T24 |
1 |
auto[1] |
796654 |
1 |
|
|
T23 |
6916 |
|
T25 |
26330 |
|
T1 |
5233 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8375093 |
1 |
|
|
T22 |
1308 |
|
T23 |
65223 |
|
T24 |
1 |
auto[1] |
6267799 |
1 |
|
|
T23 |
52873 |
|
T25 |
199826 |
|
T1 |
40074 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2736428 |
1 |
|
|
T23 |
23262 |
|
T25 |
90490 |
|
T1 |
16436 |
auto[1] |
auto[0] |
auto[1] |
398147 |
1 |
|
|
T23 |
3482 |
|
T25 |
13884 |
|
T1 |
2437 |
auto[1] |
auto[1] |
auto[0] |
2734717 |
1 |
|
|
T23 |
22695 |
|
T25 |
83006 |
|
T1 |
18405 |
auto[1] |
auto[1] |
auto[1] |
398507 |
1 |
|
|
T23 |
3434 |
|
T25 |
12446 |
|
T1 |
2796 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |