Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8395255 |
1 |
|
|
T22 |
1308 |
|
T23 |
66407 |
|
T24 |
1 |
| auto[1] |
6247637 |
1 |
|
|
T23 |
51689 |
|
T25 |
201892 |
|
T1 |
38659 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12118871 |
1 |
|
|
T22 |
1308 |
|
T23 |
97749 |
|
T24 |
1 |
| auto[1] |
2524021 |
1 |
|
|
T23 |
20347 |
|
T25 |
78243 |
|
T1 |
14839 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8373726 |
1 |
|
|
T22 |
1308 |
|
T23 |
67547 |
|
T24 |
1 |
| auto[1] |
6269166 |
1 |
|
|
T23 |
50549 |
|
T25 |
203089 |
|
T1 |
38925 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1890904 |
1 |
|
|
T23 |
15742 |
|
T25 |
62038 |
|
T1 |
11763 |
| auto[1] |
auto[0] |
auto[1] |
1272763 |
1 |
|
|
T23 |
10747 |
|
T25 |
39164 |
|
T1 |
7551 |
| auto[1] |
auto[1] |
auto[0] |
1854241 |
1 |
|
|
T23 |
14460 |
|
T25 |
62808 |
|
T1 |
12323 |
| auto[1] |
auto[1] |
auto[1] |
1251258 |
1 |
|
|
T23 |
9600 |
|
T25 |
39079 |
|
T1 |
7288 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |