Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8373709 |
1 |
|
|
T22 |
1308 |
|
T23 |
64475 |
|
T24 |
1 |
auto[1] |
6269183 |
1 |
|
|
T23 |
53621 |
|
T25 |
198396 |
|
T1 |
41388 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13851597 |
1 |
|
|
T22 |
1308 |
|
T23 |
111363 |
|
T24 |
1 |
auto[1] |
791295 |
1 |
|
|
T23 |
6733 |
|
T25 |
26655 |
|
T1 |
5195 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8393303 |
1 |
|
|
T22 |
1308 |
|
T23 |
66263 |
|
T24 |
1 |
auto[1] |
6249589 |
1 |
|
|
T23 |
51833 |
|
T25 |
202260 |
|
T1 |
39239 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2735730 |
1 |
|
|
T23 |
22735 |
|
T25 |
88226 |
|
T1 |
16009 |
auto[1] |
auto[0] |
auto[1] |
396994 |
1 |
|
|
T23 |
3266 |
|
T25 |
13208 |
|
T1 |
2450 |
auto[1] |
auto[1] |
auto[0] |
2722564 |
1 |
|
|
T23 |
22365 |
|
T25 |
87379 |
|
T1 |
18035 |
auto[1] |
auto[1] |
auto[1] |
394301 |
1 |
|
|
T23 |
3467 |
|
T25 |
13447 |
|
T1 |
2745 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |