Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8358646 |
1 |
|
|
T22 |
1308 |
|
T23 |
65515 |
|
T24 |
1 |
auto[1] |
6284246 |
1 |
|
|
T23 |
52581 |
|
T25 |
203474 |
|
T1 |
43908 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13843756 |
1 |
|
|
T22 |
1308 |
|
T23 |
111034 |
|
T24 |
1 |
auto[1] |
799136 |
1 |
|
|
T23 |
7062 |
|
T25 |
26434 |
|
T1 |
5125 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8347461 |
1 |
|
|
T22 |
1308 |
|
T23 |
64269 |
|
T24 |
1 |
auto[1] |
6295431 |
1 |
|
|
T23 |
53827 |
|
T25 |
200292 |
|
T1 |
39787 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2750282 |
1 |
|
|
T23 |
23669 |
|
T25 |
86180 |
|
T1 |
15929 |
auto[1] |
auto[0] |
auto[1] |
400295 |
1 |
|
|
T23 |
3633 |
|
T25 |
12959 |
|
T1 |
2248 |
auto[1] |
auto[1] |
auto[0] |
2746013 |
1 |
|
|
T23 |
23096 |
|
T25 |
87678 |
|
T1 |
18733 |
auto[1] |
auto[1] |
auto[1] |
398841 |
1 |
|
|
T23 |
3429 |
|
T25 |
13475 |
|
T1 |
2877 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |