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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
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T766 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3280160046 May 05 01:55:23 PM PDT 24 May 05 01:55:24 PM PDT 24 17964993 ps
T767 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1845209744 May 05 01:55:35 PM PDT 24 May 05 01:55:37 PM PDT 24 27940649 ps
T768 /workspace/coverage/cover_reg_top/6.gpio_intr_test.941419336 May 05 01:55:35 PM PDT 24 May 05 01:55:37 PM PDT 24 14812302 ps
T44 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3149190059 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 40530736 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.258565202 May 05 01:55:24 PM PDT 24 May 05 01:55:25 PM PDT 24 18183454 ps
T769 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.426140960 May 05 01:55:18 PM PDT 24 May 05 01:55:19 PM PDT 24 45841165 ps
T770 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3321273554 May 05 01:55:42 PM PDT 24 May 05 01:55:43 PM PDT 24 16553264 ps
T771 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4210732321 May 05 01:55:28 PM PDT 24 May 05 01:55:31 PM PDT 24 38498056 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2853470217 May 05 01:55:18 PM PDT 24 May 05 01:55:19 PM PDT 24 86804348 ps
T773 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3733907129 May 05 01:55:22 PM PDT 24 May 05 01:55:26 PM PDT 24 930872236 ps
T42 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3693958365 May 05 01:55:32 PM PDT 24 May 05 01:55:34 PM PDT 24 696841910 ps
T102 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2560809465 May 05 01:55:30 PM PDT 24 May 05 01:55:31 PM PDT 24 30351627 ps
T774 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2100888214 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 55844049 ps
T775 /workspace/coverage/cover_reg_top/27.gpio_intr_test.560670692 May 05 01:55:29 PM PDT 24 May 05 01:55:30 PM PDT 24 12691622 ps
T87 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3046860341 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 19897539 ps
T776 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2166434953 May 05 01:55:21 PM PDT 24 May 05 01:55:23 PM PDT 24 16491131 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3532175372 May 05 01:55:29 PM PDT 24 May 05 01:55:31 PM PDT 24 33501504 ps
T778 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1135322184 May 05 01:55:46 PM PDT 24 May 05 01:55:47 PM PDT 24 45736149 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1854269562 May 05 01:55:20 PM PDT 24 May 05 01:55:21 PM PDT 24 135194780 ps
T780 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1194566238 May 05 01:55:40 PM PDT 24 May 05 01:55:41 PM PDT 24 198784676 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3036383886 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 81456655 ps
T782 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2369365156 May 05 01:55:27 PM PDT 24 May 05 01:55:29 PM PDT 24 41233181 ps
T88 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1184941211 May 05 01:55:27 PM PDT 24 May 05 01:55:29 PM PDT 24 138716467 ps
T41 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3399281948 May 05 01:55:44 PM PDT 24 May 05 01:55:46 PM PDT 24 150069274 ps
T783 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2212388648 May 05 01:55:46 PM PDT 24 May 05 01:55:48 PM PDT 24 30065398 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1448241524 May 05 01:55:22 PM PDT 24 May 05 01:55:24 PM PDT 24 38973385 ps
T785 /workspace/coverage/cover_reg_top/31.gpio_intr_test.766453982 May 05 01:55:51 PM PDT 24 May 05 01:55:52 PM PDT 24 14316665 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1517009362 May 05 01:55:43 PM PDT 24 May 05 01:55:44 PM PDT 24 39491449 ps
T787 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1823942620 May 05 01:55:28 PM PDT 24 May 05 01:55:30 PM PDT 24 52499457 ps
T788 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4182695543 May 05 01:55:21 PM PDT 24 May 05 01:55:24 PM PDT 24 56741517 ps
T789 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.623896919 May 05 01:55:36 PM PDT 24 May 05 01:55:37 PM PDT 24 36690330 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.982321766 May 05 01:55:33 PM PDT 24 May 05 01:55:34 PM PDT 24 98097223 ps
T791 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4123385879 May 05 01:55:35 PM PDT 24 May 05 01:55:36 PM PDT 24 39495734 ps
T792 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1556359496 May 05 01:55:20 PM PDT 24 May 05 01:55:22 PM PDT 24 71101020 ps
T793 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2781192225 May 05 01:55:32 PM PDT 24 May 05 01:55:35 PM PDT 24 227746054 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1408018425 May 05 01:55:17 PM PDT 24 May 05 01:55:19 PM PDT 24 16299013 ps
T795 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3777916399 May 05 01:55:41 PM PDT 24 May 05 01:55:42 PM PDT 24 17353805 ps
T796 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3512299185 May 05 01:55:44 PM PDT 24 May 05 01:55:46 PM PDT 24 19356274 ps
T797 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2571123222 May 05 01:55:40 PM PDT 24 May 05 01:55:42 PM PDT 24 11989436 ps
T798 /workspace/coverage/cover_reg_top/43.gpio_intr_test.53084559 May 05 01:55:33 PM PDT 24 May 05 01:55:34 PM PDT 24 45880692 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2502504158 May 05 01:55:33 PM PDT 24 May 05 01:55:34 PM PDT 24 19806788 ps
T800 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2547771577 May 05 01:55:37 PM PDT 24 May 05 01:55:38 PM PDT 24 46214561 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2894529617 May 05 01:55:15 PM PDT 24 May 05 01:55:16 PM PDT 24 38353796 ps
T802 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1339125192 May 05 01:55:31 PM PDT 24 May 05 01:55:32 PM PDT 24 15305762 ps
T89 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.823663131 May 05 01:55:18 PM PDT 24 May 05 01:55:23 PM PDT 24 146178284 ps
T90 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1714580871 May 05 01:55:51 PM PDT 24 May 05 01:55:53 PM PDT 24 12017806 ps
T803 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.937989263 May 05 01:55:32 PM PDT 24 May 05 01:55:33 PM PDT 24 186639693 ps
T804 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2807838607 May 05 01:55:45 PM PDT 24 May 05 01:55:47 PM PDT 24 36149878 ps
T805 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3191249059 May 05 01:55:40 PM PDT 24 May 05 01:55:42 PM PDT 24 232836169 ps
T806 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1768379426 May 05 01:55:51 PM PDT 24 May 05 01:55:52 PM PDT 24 16145436 ps
T807 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2324849006 May 05 01:55:43 PM PDT 24 May 05 01:55:44 PM PDT 24 21666290 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2527888425 May 05 01:55:17 PM PDT 24 May 05 01:55:23 PM PDT 24 25029307 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3960243926 May 05 01:55:14 PM PDT 24 May 05 01:55:15 PM PDT 24 54448639 ps
T810 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.176465993 May 05 01:55:28 PM PDT 24 May 05 01:55:29 PM PDT 24 23387596 ps
T91 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2474824055 May 05 01:55:21 PM PDT 24 May 05 01:55:24 PM PDT 24 13944412 ps
T92 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.641949775 May 05 01:55:18 PM PDT 24 May 05 01:55:20 PM PDT 24 95030612 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3817784897 May 05 01:55:18 PM PDT 24 May 05 01:55:19 PM PDT 24 18674799 ps
T812 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1280295344 May 05 01:55:22 PM PDT 24 May 05 01:55:24 PM PDT 24 29646902 ps
T45 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1509310658 May 05 01:55:37 PM PDT 24 May 05 01:55:39 PM PDT 24 389122341 ps
T93 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2559958889 May 05 01:55:23 PM PDT 24 May 05 01:55:24 PM PDT 24 18765197 ps
T813 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3489929276 May 05 01:55:24 PM PDT 24 May 05 01:55:26 PM PDT 24 27373590 ps
T814 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1402970337 May 05 01:55:18 PM PDT 24 May 05 01:55:23 PM PDT 24 43451306 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1588894199 May 05 01:55:20 PM PDT 24 May 05 01:55:22 PM PDT 24 40452630 ps
T815 /workspace/coverage/cover_reg_top/35.gpio_intr_test.11054876 May 05 01:55:48 PM PDT 24 May 05 01:55:49 PM PDT 24 15191804 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2195188817 May 05 01:55:25 PM PDT 24 May 05 01:55:27 PM PDT 24 529925426 ps
T817 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4006351377 May 05 01:55:43 PM PDT 24 May 05 01:55:44 PM PDT 24 117083279 ps
T818 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3896938860 May 05 01:55:23 PM PDT 24 May 05 01:55:26 PM PDT 24 393336578 ps
T819 /workspace/coverage/cover_reg_top/41.gpio_intr_test.349771964 May 05 01:55:33 PM PDT 24 May 05 01:55:34 PM PDT 24 15477602 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2644774779 May 05 01:55:23 PM PDT 24 May 05 01:55:24 PM PDT 24 26868708 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2314633227 May 05 01:55:17 PM PDT 24 May 05 01:55:19 PM PDT 24 11900885 ps
T822 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1081864041 May 05 01:55:20 PM PDT 24 May 05 01:55:22 PM PDT 24 27630875 ps
T823 /workspace/coverage/cover_reg_top/46.gpio_intr_test.435812016 May 05 01:55:47 PM PDT 24 May 05 01:55:48 PM PDT 24 36986675 ps
T824 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2708265294 May 05 01:55:39 PM PDT 24 May 05 01:55:41 PM PDT 24 117091292 ps
T825 /workspace/coverage/cover_reg_top/0.gpio_intr_test.598666226 May 05 01:55:15 PM PDT 24 May 05 01:55:16 PM PDT 24 32256439 ps
T826 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3572960325 May 05 01:55:29 PM PDT 24 May 05 01:55:31 PM PDT 24 219432776 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1991000342 May 05 01:55:45 PM PDT 24 May 05 01:55:47 PM PDT 24 40663581 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.587849395 May 05 01:55:16 PM PDT 24 May 05 01:55:18 PM PDT 24 118498058 ps
T829 /workspace/coverage/cover_reg_top/26.gpio_intr_test.334382377 May 05 01:55:32 PM PDT 24 May 05 01:55:33 PM PDT 24 30355489 ps
T830 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1860764075 May 05 01:55:48 PM PDT 24 May 05 01:55:50 PM PDT 24 94021784 ps
T831 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.307209878 May 05 01:55:40 PM PDT 24 May 05 01:55:42 PM PDT 24 16467062 ps
T832 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3012997794 May 05 01:55:42 PM PDT 24 May 05 01:55:43 PM PDT 24 49022395 ps
T833 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2070678279 May 05 01:55:37 PM PDT 24 May 05 01:55:38 PM PDT 24 13512813 ps
T834 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.152494413 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 177695659 ps
T835 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2011546162 May 05 01:55:34 PM PDT 24 May 05 01:55:35 PM PDT 24 56328844 ps
T836 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4197521685 May 05 01:55:40 PM PDT 24 May 05 01:55:44 PM PDT 24 165457140 ps
T837 /workspace/coverage/cover_reg_top/49.gpio_intr_test.361407684 May 05 01:55:53 PM PDT 24 May 05 01:55:54 PM PDT 24 18270099 ps
T838 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1500318185 May 05 01:55:35 PM PDT 24 May 05 01:55:36 PM PDT 24 85073031 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2780668169 May 05 01:55:19 PM PDT 24 May 05 01:55:21 PM PDT 24 17265996 ps
T839 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1531686555 May 05 01:55:32 PM PDT 24 May 05 01:55:34 PM PDT 24 541310962 ps
T840 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4183795285 May 05 01:55:30 PM PDT 24 May 05 01:55:32 PM PDT 24 13834122 ps
T841 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3735241199 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 86844287 ps
T842 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.707869801 May 05 01:55:52 PM PDT 24 May 05 01:55:54 PM PDT 24 32102389 ps
T843 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2440766271 May 05 12:19:17 PM PDT 24 May 05 12:19:18 PM PDT 24 59995221 ps
T844 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3878595706 May 05 12:19:13 PM PDT 24 May 05 12:19:15 PM PDT 24 204190459 ps
T845 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2164725818 May 05 12:20:22 PM PDT 24 May 05 12:20:25 PM PDT 24 96941723 ps
T846 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2843545633 May 05 12:19:03 PM PDT 24 May 05 12:19:05 PM PDT 24 62897124 ps
T847 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80701998 May 05 12:24:05 PM PDT 24 May 05 12:24:11 PM PDT 24 64867948 ps
T848 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716846928 May 05 12:19:14 PM PDT 24 May 05 12:19:15 PM PDT 24 32653921 ps
T849 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4055244533 May 05 12:19:11 PM PDT 24 May 05 12:19:13 PM PDT 24 78552261 ps
T850 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3432552338 May 05 12:19:18 PM PDT 24 May 05 12:19:22 PM PDT 24 189171722 ps
T851 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1155742323 May 05 12:19:17 PM PDT 24 May 05 12:19:20 PM PDT 24 429329503 ps
T852 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2966020002 May 05 12:23:53 PM PDT 24 May 05 12:23:56 PM PDT 24 58119382 ps
T853 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.42493386 May 05 12:19:03 PM PDT 24 May 05 12:19:06 PM PDT 24 54888223 ps
T854 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4076442018 May 05 12:21:28 PM PDT 24 May 05 12:21:30 PM PDT 24 95433420 ps
T855 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2178080656 May 05 12:19:17 PM PDT 24 May 05 12:19:20 PM PDT 24 111004603 ps
T856 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.824223884 May 05 12:20:22 PM PDT 24 May 05 12:20:24 PM PDT 24 72203098 ps
T857 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2894306323 May 05 12:25:05 PM PDT 24 May 05 12:25:08 PM PDT 24 34684909 ps
T858 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2523729528 May 05 12:19:12 PM PDT 24 May 05 12:19:14 PM PDT 24 68610893 ps
T859 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.428502688 May 05 12:24:04 PM PDT 24 May 05 12:24:09 PM PDT 24 284479017 ps
T860 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.325417743 May 05 12:19:17 PM PDT 24 May 05 12:19:19 PM PDT 24 51851488 ps
T861 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.386099728 May 05 12:19:55 PM PDT 24 May 05 12:19:57 PM PDT 24 80221125 ps
T862 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3170083425 May 05 12:24:06 PM PDT 24 May 05 12:24:12 PM PDT 24 58214005 ps
T863 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2635431790 May 05 12:19:14 PM PDT 24 May 05 12:19:15 PM PDT 24 130751090 ps
T864 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.345468075 May 05 12:22:48 PM PDT 24 May 05 12:22:50 PM PDT 24 167362291 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4106718147 May 05 12:22:07 PM PDT 24 May 05 12:22:09 PM PDT 24 139083716 ps
T866 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3172728365 May 05 12:19:17 PM PDT 24 May 05 12:19:20 PM PDT 24 255646555 ps
T867 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833124056 May 05 12:24:05 PM PDT 24 May 05 12:24:10 PM PDT 24 69899667 ps
T868 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.72238066 May 05 12:20:22 PM PDT 24 May 05 12:20:25 PM PDT 24 145998309 ps
T869 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1441595634 May 05 12:22:10 PM PDT 24 May 05 12:22:11 PM PDT 24 61561002 ps
T870 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1117577491 May 05 12:23:30 PM PDT 24 May 05 12:23:32 PM PDT 24 143633684 ps
T871 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3572132796 May 05 12:21:58 PM PDT 24 May 05 12:22:00 PM PDT 24 75452821 ps
T872 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.597227277 May 05 12:24:51 PM PDT 24 May 05 12:24:56 PM PDT 24 216217056 ps
T873 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2911290702 May 05 12:19:12 PM PDT 24 May 05 12:19:14 PM PDT 24 238699223 ps
T874 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3453012972 May 05 12:20:03 PM PDT 24 May 05 12:20:05 PM PDT 24 67743475 ps
T875 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1033470876 May 05 12:19:18 PM PDT 24 May 05 12:19:20 PM PDT 24 197309811 ps
T876 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.293354392 May 05 12:24:05 PM PDT 24 May 05 12:24:11 PM PDT 24 1000840477 ps
T877 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1904201789 May 05 12:19:18 PM PDT 24 May 05 12:19:21 PM PDT 24 289282268 ps
T878 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3511223015 May 05 12:19:14 PM PDT 24 May 05 12:19:16 PM PDT 24 42215001 ps
T879 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520860520 May 05 12:20:22 PM PDT 24 May 05 12:20:25 PM PDT 24 46710080 ps
T880 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3453993895 May 05 12:19:16 PM PDT 24 May 05 12:19:18 PM PDT 24 193472415 ps
T881 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045603125 May 05 12:19:56 PM PDT 24 May 05 12:19:58 PM PDT 24 352521180 ps
T882 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2676568740 May 05 12:20:02 PM PDT 24 May 05 12:20:04 PM PDT 24 282166098 ps
T883 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.871568603 May 05 12:19:17 PM PDT 24 May 05 12:19:20 PM PDT 24 337724867 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.33145517 May 05 12:20:41 PM PDT 24 May 05 12:20:42 PM PDT 24 142572929 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269711478 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 94153089 ps
T886 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926657546 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 152927227 ps
T887 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.435494532 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 49040830 ps
T888 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.932581152 May 05 12:24:04 PM PDT 24 May 05 12:24:07 PM PDT 24 57195187 ps
T889 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3823460281 May 05 12:24:04 PM PDT 24 May 05 12:24:08 PM PDT 24 77934675 ps
T890 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3008953703 May 05 12:20:22 PM PDT 24 May 05 12:20:25 PM PDT 24 64668475 ps
T891 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1044568716 May 05 12:20:46 PM PDT 24 May 05 12:20:48 PM PDT 24 93255189 ps
T892 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.727736870 May 05 12:19:17 PM PDT 24 May 05 12:19:19 PM PDT 24 37702802 ps
T893 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1384305368 May 05 12:24:48 PM PDT 24 May 05 12:24:50 PM PDT 24 47979061 ps
T894 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4282094221 May 05 12:19:12 PM PDT 24 May 05 12:19:14 PM PDT 24 231334094 ps
T895 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1650262538 May 05 12:19:18 PM PDT 24 May 05 12:19:20 PM PDT 24 117650147 ps
T896 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1627410952 May 05 12:24:05 PM PDT 24 May 05 12:24:11 PM PDT 24 84356396 ps
T897 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.102393029 May 05 12:19:17 PM PDT 24 May 05 12:19:19 PM PDT 24 48078054 ps
T898 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2930416221 May 05 12:19:13 PM PDT 24 May 05 12:19:14 PM PDT 24 47878886 ps
T899 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2610837323 May 05 12:19:17 PM PDT 24 May 05 12:19:20 PM PDT 24 287221174 ps
T900 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164901038 May 05 12:19:15 PM PDT 24 May 05 12:19:18 PM PDT 24 31421801 ps
T901 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.612731880 May 05 12:19:26 PM PDT 24 May 05 12:19:27 PM PDT 24 60758925 ps
T902 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1919899095 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 74151781 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3031670113 May 05 12:19:17 PM PDT 24 May 05 12:19:19 PM PDT 24 121681746 ps
T904 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577975707 May 05 12:24:48 PM PDT 24 May 05 12:24:50 PM PDT 24 124837650 ps
T905 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4220445414 May 05 12:19:12 PM PDT 24 May 05 12:19:14 PM PDT 24 211484163 ps
T906 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1788767740 May 05 12:22:46 PM PDT 24 May 05 12:22:47 PM PDT 24 42337517 ps
T907 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1125665381 May 05 12:20:23 PM PDT 24 May 05 12:20:25 PM PDT 24 67774732 ps
T908 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.202309061 May 05 12:25:08 PM PDT 24 May 05 12:25:12 PM PDT 24 226919525 ps
T909 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4226402761 May 05 12:19:26 PM PDT 24 May 05 12:19:27 PM PDT 24 57406650 ps
T910 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.387641576 May 05 12:24:03 PM PDT 24 May 05 12:24:06 PM PDT 24 221148433 ps
T911 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1936882231 May 05 12:24:48 PM PDT 24 May 05 12:24:51 PM PDT 24 76184654 ps
T912 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2119438289 May 05 12:21:10 PM PDT 24 May 05 12:21:12 PM PDT 24 53789780 ps
T913 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3868892282 May 05 12:24:04 PM PDT 24 May 05 12:24:09 PM PDT 24 119241040 ps
T914 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.957012601 May 05 12:21:57 PM PDT 24 May 05 12:21:58 PM PDT 24 187836901 ps
T915 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1753511706 May 05 12:20:23 PM PDT 24 May 05 12:20:25 PM PDT 24 267703476 ps
T916 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3078390794 May 05 12:20:24 PM PDT 24 May 05 12:20:25 PM PDT 24 84287449 ps
T917 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1138095465 May 05 12:19:12 PM PDT 24 May 05 12:19:13 PM PDT 24 83855839 ps
T918 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912367052 May 05 12:19:17 PM PDT 24 May 05 12:19:19 PM PDT 24 301839741 ps
T919 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3103834954 May 05 12:24:50 PM PDT 24 May 05 12:24:54 PM PDT 24 70322758 ps
T920 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3057861843 May 05 12:23:53 PM PDT 24 May 05 12:23:56 PM PDT 24 99772198 ps
T921 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2323803959 May 05 12:24:06 PM PDT 24 May 05 12:24:11 PM PDT 24 22731700 ps
T922 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3722848331 May 05 12:24:50 PM PDT 24 May 05 12:24:54 PM PDT 24 81445070 ps
T923 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.76691889 May 05 12:21:55 PM PDT 24 May 05 12:21:56 PM PDT 24 271888450 ps
T924 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.244596412 May 05 12:24:48 PM PDT 24 May 05 12:24:50 PM PDT 24 68371476 ps
T925 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4150403623 May 05 12:24:01 PM PDT 24 May 05 12:24:03 PM PDT 24 52972136 ps
T926 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.347962226 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 254960716 ps
T927 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2038511752 May 05 12:19:33 PM PDT 24 May 05 12:19:35 PM PDT 24 71246678 ps
T928 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2430329796 May 05 12:23:52 PM PDT 24 May 05 12:23:55 PM PDT 24 104445779 ps
T929 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1273477511 May 05 12:24:48 PM PDT 24 May 05 12:24:51 PM PDT 24 88093880 ps
T930 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2884664142 May 05 12:20:23 PM PDT 24 May 05 12:20:25 PM PDT 24 770694858 ps
T931 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2469374457 May 05 12:20:22 PM PDT 24 May 05 12:20:25 PM PDT 24 490485919 ps
T932 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064085886 May 05 12:22:24 PM PDT 24 May 05 12:22:26 PM PDT 24 257929830 ps
T933 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2027472885 May 05 12:21:58 PM PDT 24 May 05 12:22:00 PM PDT 24 393939675 ps
T934 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811159226 May 05 12:24:51 PM PDT 24 May 05 12:24:55 PM PDT 24 366284195 ps
T935 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4200483032 May 05 12:24:49 PM PDT 24 May 05 12:24:53 PM PDT 24 166941333 ps
T936 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3684649186 May 05 12:20:27 PM PDT 24 May 05 12:20:29 PM PDT 24 172297678 ps
T937 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.259778986 May 05 12:20:16 PM PDT 24 May 05 12:20:17 PM PDT 24 42175473 ps
T938 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4011631927 May 05 12:19:11 PM PDT 24 May 05 12:19:13 PM PDT 24 50269549 ps
T939 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284629223 May 05 12:19:16 PM PDT 24 May 05 12:19:18 PM PDT 24 60506130 ps
T940 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1023443140 May 05 12:20:23 PM PDT 24 May 05 12:20:25 PM PDT 24 73943506 ps
T941 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1765501282 May 05 12:20:00 PM PDT 24 May 05 12:20:02 PM PDT 24 86886943 ps
T942 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.890982353 May 05 12:21:29 PM PDT 24 May 05 12:21:30 PM PDT 24 589113799 ps

Test location /workspace/coverage/default/34.gpio_stress_all.2812454735
Short name T1
Test name
Test status
Simulation time 56511214683 ps
CPU time 151.92 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 198084 kb
Host smart-735a6764-f99c-4dca-aac9-292ebe6dd13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812454735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2812454735
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2610305095
Short name T16
Test name
Test status
Simulation time 357208593 ps
CPU time 3.4 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 198004 kb
Host smart-025faa26-dbbc-447c-8547-5cd290be7e2f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610305095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2610305095
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2564223595
Short name T28
Test name
Test status
Simulation time 50033269817 ps
CPU time 692.37 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:52:18 PM PDT 24
Peak memory 198100 kb
Host smart-6edf84fc-83bb-451f-99f4-599792b577aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2564223595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2564223595
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.377239084
Short name T32
Test name
Test status
Simulation time 154321472 ps
CPU time 1.17 seconds
Started May 05 01:55:34 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 197752 kb
Host smart-49a9b99a-eb06-4c9d-ba31-5b1704bc6d97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377239084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.377239084
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.877186719
Short name T76
Test name
Test status
Simulation time 45543195 ps
CPU time 0.65 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:33 PM PDT 24
Peak memory 194664 kb
Host smart-5c3faa24-486b-49be-9aa2-55bcd80c7e73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877186719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.877186719
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1557345867
Short name T143
Test name
Test status
Simulation time 11659622 ps
CPU time 0.63 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 194036 kb
Host smart-84feecfd-5764-4f92-8c43-5e1123b9d9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557345867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1557345867
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.432039785
Short name T34
Test name
Test status
Simulation time 1009498044 ps
CPU time 0.98 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 214920 kb
Host smart-b36f102a-e7b2-49cc-bfd3-115896671371
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432039785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.432039785
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3572960325
Short name T826
Test name
Test status
Simulation time 219432776 ps
CPU time 1.42 seconds
Started May 05 01:55:29 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 197772 kb
Host smart-69320e89-2d4b-45c3-b687-9f49d1fcd90d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572960325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3572960325
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.641949775
Short name T92
Test name
Test status
Simulation time 95030612 ps
CPU time 0.75 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:20 PM PDT 24
Peak memory 196080 kb
Host smart-17c2a93e-7752-4889-affe-cc7254c8889b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641949775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.641949775
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2243622720
Short name T100
Test name
Test status
Simulation time 51619479 ps
CPU time 0.74 seconds
Started May 05 01:55:13 PM PDT 24
Finished May 05 01:55:14 PM PDT 24
Peak memory 195920 kb
Host smart-101f9a55-bcf3-4b23-b95d-2ba333354a23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243622720 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2243622720
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2636924882
Short name T39
Test name
Test status
Simulation time 767943621 ps
CPU time 1.45 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 197788 kb
Host smart-3e735951-c524-4a06-a497-50bc67a8f747
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636924882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2636924882
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.4137248418
Short name T761
Test name
Test status
Simulation time 116345106 ps
CPU time 2.19 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:27 PM PDT 24
Peak memory 197756 kb
Host smart-635e540f-4d03-40da-9007-a2cda694cfc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137248418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.4137248418
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3280160046
Short name T766
Test name
Test status
Simulation time 17964993 ps
CPU time 0.66 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 194980 kb
Host smart-b257b253-e22e-465b-9c72-62a4b3ef737f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280160046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3280160046
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.587849395
Short name T828
Test name
Test status
Simulation time 118498058 ps
CPU time 0.87 seconds
Started May 05 01:55:16 PM PDT 24
Finished May 05 01:55:18 PM PDT 24
Peak memory 197660 kb
Host smart-10992369-c3f0-46e9-958f-928a3089551b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587849395 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.587849395
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.426140960
Short name T769
Test name
Test status
Simulation time 45841165 ps
CPU time 0.61 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 194496 kb
Host smart-4bd9a92e-bb32-4341-947d-a61d759c1343
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426140960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.426140960
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.598666226
Short name T825
Test name
Test status
Simulation time 32256439 ps
CPU time 0.56 seconds
Started May 05 01:55:15 PM PDT 24
Finished May 05 01:55:16 PM PDT 24
Peak memory 193424 kb
Host smart-eb89d925-112a-426e-b066-94ced1d03a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598666226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.598666226
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3960243926
Short name T809
Test name
Test status
Simulation time 54448639 ps
CPU time 0.65 seconds
Started May 05 01:55:14 PM PDT 24
Finished May 05 01:55:15 PM PDT 24
Peak memory 194040 kb
Host smart-05c1620e-0353-486e-b422-77351a85a8bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960243926 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3960243926
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2527888425
Short name T808
Test name
Test status
Simulation time 25029307 ps
CPU time 1.22 seconds
Started May 05 01:55:17 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 197732 kb
Host smart-75f77a5a-bb90-4fd9-a148-107cb7dbd946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527888425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2527888425
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3149190059
Short name T44
Test name
Test status
Simulation time 40530736 ps
CPU time 0.89 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 196908 kb
Host smart-691eac49-c6dc-4c1b-95b4-ab04f1550049
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149190059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3149190059
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1280295344
Short name T812
Test name
Test status
Simulation time 29646902 ps
CPU time 0.77 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 195680 kb
Host smart-e9f775e4-615c-4505-9672-c954009c5f67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280295344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1280295344
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2195188817
Short name T816
Test name
Test status
Simulation time 529925426 ps
CPU time 1.5 seconds
Started May 05 01:55:25 PM PDT 24
Finished May 05 01:55:27 PM PDT 24
Peak memory 196532 kb
Host smart-9f7a2437-a58c-4ec6-aa82-3b2ea0a85e2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195188817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2195188817
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1588894199
Short name T94
Test name
Test status
Simulation time 40452630 ps
CPU time 0.65 seconds
Started May 05 01:55:20 PM PDT 24
Finished May 05 01:55:22 PM PDT 24
Peak memory 194764 kb
Host smart-5daa9e07-e05d-4ae3-a8d6-c88f80f1a2ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588894199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1588894199
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1854269562
Short name T779
Test name
Test status
Simulation time 135194780 ps
CPU time 0.72 seconds
Started May 05 01:55:20 PM PDT 24
Finished May 05 01:55:21 PM PDT 24
Peak memory 197236 kb
Host smart-063e5be2-1510-4c91-ae41-fbf5a07317f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854269562 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1854269562
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2314633227
Short name T821
Test name
Test status
Simulation time 11900885 ps
CPU time 0.57 seconds
Started May 05 01:55:17 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 193020 kb
Host smart-e8ae880a-dc5e-4480-835a-26ddb8d1a69c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314633227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2314633227
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1408018425
Short name T794
Test name
Test status
Simulation time 16299013 ps
CPU time 0.64 seconds
Started May 05 01:55:17 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 193528 kb
Host smart-189b66b7-31be-4a0e-bafa-b55df2d6faaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408018425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1408018425
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3896938860
Short name T818
Test name
Test status
Simulation time 393336578 ps
CPU time 2.19 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 197668 kb
Host smart-7002f014-8cff-4f11-b0d3-65b117200e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896938860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3896938860
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3735241199
Short name T841
Test name
Test status
Simulation time 86844287 ps
CPU time 1.18 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197196 kb
Host smart-355771ab-831e-4e7d-a9cc-89dcfafd6093
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735241199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3735241199
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2320004599
Short name T744
Test name
Test status
Simulation time 86839185 ps
CPU time 1.24 seconds
Started May 05 01:55:38 PM PDT 24
Finished May 05 01:55:40 PM PDT 24
Peak memory 197848 kb
Host smart-6f8a8915-77fa-4b37-a827-7f324c67652b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320004599 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2320004599
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2313048487
Short name T83
Test name
Test status
Simulation time 43026451 ps
CPU time 0.61 seconds
Started May 05 01:55:30 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 194768 kb
Host smart-9e64c071-69f6-4e5c-a4d7-57058501c196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313048487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2313048487
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4092692332
Short name T724
Test name
Test status
Simulation time 19426774 ps
CPU time 0.57 seconds
Started May 05 01:55:25 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 194016 kb
Host smart-97a8c37b-8863-4081-9114-cd1aab9fea41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092692332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4092692332
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4206346247
Short name T75
Test name
Test status
Simulation time 126981857 ps
CPU time 0.83 seconds
Started May 05 01:55:29 PM PDT 24
Finished May 05 01:55:35 PM PDT 24
Peak memory 196160 kb
Host smart-4c73e3b3-7534-42b7-90b8-0e24786ebd00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206346247 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4206346247
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4210732321
Short name T771
Test name
Test status
Simulation time 38498056 ps
CPU time 2.14 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 197756 kb
Host smart-86e5d8b8-58af-4136-a611-d53f5d66dc7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210732321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4210732321
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1084508382
Short name T764
Test name
Test status
Simulation time 404015827 ps
CPU time 1.51 seconds
Started May 05 01:55:44 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 197744 kb
Host smart-4660bbc9-6afc-4d2c-80ea-0a25a430362b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084508382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1084508382
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3050375116
Short name T757
Test name
Test status
Simulation time 127690596 ps
CPU time 0.87 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:55:49 PM PDT 24
Peak memory 197616 kb
Host smart-764c7ee5-f591-4e15-9455-6049454c3318
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050375116 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3050375116
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.307209878
Short name T831
Test name
Test status
Simulation time 16467062 ps
CPU time 0.59 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:42 PM PDT 24
Peak memory 193048 kb
Host smart-bb96aa78-788c-4870-a3ad-0056291cd139
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307209878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.307209878
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2785133908
Short name T763
Test name
Test status
Simulation time 48609496 ps
CPU time 0.6 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 194056 kb
Host smart-6015e3de-df78-48b4-8428-e827644855ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785133908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2785133908
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1860764075
Short name T830
Test name
Test status
Simulation time 94021784 ps
CPU time 0.85 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:55:50 PM PDT 24
Peak memory 195936 kb
Host smart-380da786-b77c-4887-bcfe-f81955bc3c99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860764075 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1860764075
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4201003880
Short name T758
Test name
Test status
Simulation time 23193339 ps
CPU time 1.09 seconds
Started May 05 01:55:38 PM PDT 24
Finished May 05 01:55:40 PM PDT 24
Peak memory 197724 kb
Host smart-55892b51-1404-442a-b5ba-dc4d9b4b2948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201003880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4201003880
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3532175372
Short name T777
Test name
Test status
Simulation time 33501504 ps
CPU time 0.76 seconds
Started May 05 01:55:29 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 197684 kb
Host smart-dfec1b26-49a5-49ca-a8a2-a486d169b9ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532175372 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3532175372
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4076849515
Short name T85
Test name
Test status
Simulation time 15429821 ps
CPU time 0.56 seconds
Started May 05 01:55:29 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 193324 kb
Host smart-35bc9041-16a0-4764-a0cc-824932fc5d4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076849515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4076849515
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2655504682
Short name T736
Test name
Test status
Simulation time 38917668 ps
CPU time 0.6 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 193396 kb
Host smart-f2be234e-dec4-4b36-a04c-350f6fac39bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655504682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2655504682
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2324849006
Short name T807
Test name
Test status
Simulation time 21666290 ps
CPU time 0.63 seconds
Started May 05 01:55:43 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 194004 kb
Host smart-15d8f601-d3e9-4efd-9a6b-cf2d623f0fc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324849006 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2324849006
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3036383886
Short name T781
Test name
Test status
Simulation time 81456655 ps
CPU time 1.02 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197536 kb
Host smart-47a60290-9f06-4b8f-85c8-f0457c38b067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036383886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3036383886
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1509310658
Short name T45
Test name
Test status
Simulation time 389122341 ps
CPU time 1.19 seconds
Started May 05 01:55:37 PM PDT 24
Finished May 05 01:55:39 PM PDT 24
Peak memory 197760 kb
Host smart-07bc0a43-c03b-4e2f-9b34-85916cef366b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509310658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1509310658
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3644841256
Short name T752
Test name
Test status
Simulation time 501186104 ps
CPU time 0.95 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 197712 kb
Host smart-985eb434-0162-429c-8e4f-21907d1b14d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644841256 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3644841256
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3685135496
Short name T728
Test name
Test status
Simulation time 17620754 ps
CPU time 0.6 seconds
Started May 05 01:55:43 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 193208 kb
Host smart-0fe01915-8926-4143-8847-26d8971e9ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685135496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3685135496
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.861908622
Short name T78
Test name
Test status
Simulation time 42072403 ps
CPU time 0.65 seconds
Started May 05 01:55:25 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 194812 kb
Host smart-80f6eb45-76d0-4076-83a9-b3af20bb04af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861908622 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.861908622
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2858438291
Short name T748
Test name
Test status
Simulation time 76117249 ps
CPU time 1.18 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 197560 kb
Host smart-d2a7a741-ecbb-468e-8781-551302ba0bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858438291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2858438291
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2249712594
Short name T30
Test name
Test status
Simulation time 49857109 ps
CPU time 0.86 seconds
Started May 05 01:55:26 PM PDT 24
Finished May 05 01:55:28 PM PDT 24
Peak memory 196840 kb
Host smart-2c53bc6c-b502-4d38-b87a-f7e809029588
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249712594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2249712594
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.623896919
Short name T789
Test name
Test status
Simulation time 36690330 ps
CPU time 0.88 seconds
Started May 05 01:55:36 PM PDT 24
Finished May 05 01:55:37 PM PDT 24
Peak memory 197660 kb
Host smart-f4c96617-35c6-415d-8a0b-f31add4935dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623896919 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.623896919
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.261757398
Short name T746
Test name
Test status
Simulation time 45750545 ps
CPU time 0.57 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 193024 kb
Host smart-66d7e173-f811-4855-a910-e61f0f6e5c01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261757398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.261757398
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3321273554
Short name T770
Test name
Test status
Simulation time 16553264 ps
CPU time 0.58 seconds
Started May 05 01:55:42 PM PDT 24
Finished May 05 01:55:43 PM PDT 24
Peak memory 194040 kb
Host smart-a412ea85-c951-499e-9550-27fe6fa6cebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321273554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3321273554
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1517009362
Short name T786
Test name
Test status
Simulation time 39491449 ps
CPU time 0.72 seconds
Started May 05 01:55:43 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 194664 kb
Host smart-606c0fbc-b3ab-4735-a4da-6dceed6d285f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517009362 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1517009362
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2807838607
Short name T804
Test name
Test status
Simulation time 36149878 ps
CPU time 1.01 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 197640 kb
Host smart-6144883f-5452-4b7a-baae-2e9e5b3e4a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807838607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2807838607
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2708265294
Short name T824
Test name
Test status
Simulation time 117091292 ps
CPU time 1.37 seconds
Started May 05 01:55:39 PM PDT 24
Finished May 05 01:55:41 PM PDT 24
Peak memory 197844 kb
Host smart-ff1ff7c3-8c1d-44f3-8582-c2aa5967c55d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708265294 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2708265294
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.707869801
Short name T842
Test name
Test status
Simulation time 32102389 ps
CPU time 0.64 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 193708 kb
Host smart-13c1dea1-22ee-4155-a389-e45c95d30fa5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707869801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.707869801
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1339125192
Short name T802
Test name
Test status
Simulation time 15305762 ps
CPU time 0.6 seconds
Started May 05 01:55:31 PM PDT 24
Finished May 05 01:55:32 PM PDT 24
Peak memory 193412 kb
Host smart-898e8dc0-8386-4450-b33d-8dcd37f3d5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339125192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1339125192
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2411640127
Short name T96
Test name
Test status
Simulation time 42538623 ps
CPU time 0.86 seconds
Started May 05 01:55:42 PM PDT 24
Finished May 05 01:55:43 PM PDT 24
Peak memory 196000 kb
Host smart-9552c59d-590d-46ec-9ea6-63ff10673244
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411640127 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2411640127
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2781192225
Short name T793
Test name
Test status
Simulation time 227746054 ps
CPU time 3.11 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:35 PM PDT 24
Peak memory 197788 kb
Host smart-8ef9c8e3-a86b-42db-b85c-5d26a839b2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781192225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2781192225
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3399281948
Short name T41
Test name
Test status
Simulation time 150069274 ps
CPU time 0.89 seconds
Started May 05 01:55:44 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 197660 kb
Host smart-a717c1b4-a763-4c6d-8e3f-43c54455172e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399281948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3399281948
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.937989263
Short name T803
Test name
Test status
Simulation time 186639693 ps
CPU time 0.93 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:33 PM PDT 24
Peak memory 197688 kb
Host smart-a549a414-17bf-44b3-9de4-ff1167377bcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937989263 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.937989263
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.176465993
Short name T810
Test name
Test status
Simulation time 23387596 ps
CPU time 0.62 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 194568 kb
Host smart-9b4bc07c-92a4-46a9-a017-0926ffca69c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176465993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.176465993
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1991000342
Short name T827
Test name
Test status
Simulation time 40663581 ps
CPU time 0.58 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 193484 kb
Host smart-afbb714a-b069-4015-927b-30c2005f6816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991000342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1991000342
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2502504158
Short name T799
Test name
Test status
Simulation time 19806788 ps
CPU time 0.8 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 195836 kb
Host smart-a615198a-8877-4360-8493-7ada24b36a91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502504158 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2502504158
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2973176497
Short name T749
Test name
Test status
Simulation time 145270485 ps
CPU time 2.91 seconds
Started May 05 01:55:50 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 197704 kb
Host smart-7d1b77e5-09f7-4f15-b8b8-e12b6d3ebab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973176497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2973176497
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1194566238
Short name T780
Test name
Test status
Simulation time 198784676 ps
CPU time 0.83 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:41 PM PDT 24
Peak memory 196776 kb
Host smart-a92e67e6-4db2-41bf-b66c-cc0009daf599
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194566238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1194566238
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.982321766
Short name T790
Test name
Test status
Simulation time 98097223 ps
CPU time 0.8 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 197704 kb
Host smart-8dcc12db-1b98-4fa1-9032-0900df4e209d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982321766 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.982321766
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.496341055
Short name T84
Test name
Test status
Simulation time 30114908 ps
CPU time 0.63 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 195348 kb
Host smart-7d02a3db-385f-4c61-bd9c-5101800d0105
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496341055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.496341055
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3012997794
Short name T832
Test name
Test status
Simulation time 49022395 ps
CPU time 0.63 seconds
Started May 05 01:55:42 PM PDT 24
Finished May 05 01:55:43 PM PDT 24
Peak memory 193340 kb
Host smart-6d1a4770-9705-4461-b2eb-f39b42772062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012997794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3012997794
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3777916399
Short name T795
Test name
Test status
Simulation time 17353805 ps
CPU time 0.75 seconds
Started May 05 01:55:41 PM PDT 24
Finished May 05 01:55:42 PM PDT 24
Peak memory 196020 kb
Host smart-65270d0d-70cc-4a1e-92d1-f614dcff12f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777916399 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3777916399
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2298123088
Short name T765
Test name
Test status
Simulation time 122158199 ps
CPU time 2.33 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 197764 kb
Host smart-63f68c76-a42f-4c3e-8402-d264e68a21ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298123088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2298123088
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3938817250
Short name T43
Test name
Test status
Simulation time 51918624 ps
CPU time 0.88 seconds
Started May 05 01:55:31 PM PDT 24
Finished May 05 01:55:33 PM PDT 24
Peak memory 197316 kb
Host smart-79f8ee24-2c60-4e36-a59c-2fee54fea82b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938817250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3938817250
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.404136521
Short name T751
Test name
Test status
Simulation time 40419058 ps
CPU time 0.76 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:55:49 PM PDT 24
Peak memory 197868 kb
Host smart-23bebacf-87a1-4a79-aac2-6b80c3bcbb06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404136521 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.404136521
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3462791906
Short name T74
Test name
Test status
Simulation time 13679450 ps
CPU time 0.6 seconds
Started May 05 01:55:30 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 195080 kb
Host smart-e32e4d77-abcf-4d63-b6ca-de70cb42bd1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462791906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3462791906
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2212388648
Short name T783
Test name
Test status
Simulation time 30065398 ps
CPU time 0.62 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 193484 kb
Host smart-33c0ed4e-9202-4e19-a4a8-98063278c250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212388648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2212388648
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.23613196
Short name T97
Test name
Test status
Simulation time 58097484 ps
CPU time 0.65 seconds
Started May 05 01:55:31 PM PDT 24
Finished May 05 01:55:33 PM PDT 24
Peak memory 195052 kb
Host smart-b74c0b87-cdf6-4510-8258-cf03abe76bc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613196 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.gpio_same_csr_outstanding.23613196
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2652037844
Short name T754
Test name
Test status
Simulation time 151779541 ps
CPU time 3.09 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 197816 kb
Host smart-bd753a10-db48-4029-a66e-bb47cb98c2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652037844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2652037844
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3693958365
Short name T42
Test name
Test status
Simulation time 696841910 ps
CPU time 1.12 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 197764 kb
Host smart-126ad4bc-2d50-498e-b805-a4fc90552b7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693958365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3693958365
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.518875155
Short name T721
Test name
Test status
Simulation time 34165264 ps
CPU time 1.49 seconds
Started May 05 01:55:38 PM PDT 24
Finished May 05 01:55:40 PM PDT 24
Peak memory 197828 kb
Host smart-94cd567f-a3b7-4758-8df4-b98c0611cf03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518875155 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.518875155
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1714580871
Short name T90
Test name
Test status
Simulation time 12017806 ps
CPU time 0.64 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 193064 kb
Host smart-6a8c5f10-56e4-4995-af31-b6b0a363c21d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714580871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1714580871
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1845209744
Short name T767
Test name
Test status
Simulation time 27940649 ps
CPU time 0.59 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:37 PM PDT 24
Peak memory 193424 kb
Host smart-c7a79d77-2ab6-4d74-bf81-e6746e978d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845209744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1845209744
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3191249059
Short name T805
Test name
Test status
Simulation time 232836169 ps
CPU time 0.8 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:42 PM PDT 24
Peak memory 196260 kb
Host smart-61899bc4-ce29-4433-963a-ff9ae20ff25d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191249059 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3191249059
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4197521685
Short name T836
Test name
Test status
Simulation time 165457140 ps
CPU time 2.8 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 197996 kb
Host smart-6d256c60-e0a0-4a96-a3ed-0c7677a3c6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197521685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4197521685
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1531686555
Short name T839
Test name
Test status
Simulation time 541310962 ps
CPU time 0.85 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 197608 kb
Host smart-f5a76ddd-d2ec-4bcc-9c49-21ac1c4b41eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531686555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1531686555
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.823663131
Short name T89
Test name
Test status
Simulation time 146178284 ps
CPU time 0.87 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 196536 kb
Host smart-a767ab47-6629-42a4-aca8-f0fd56a201cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823663131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.823663131
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3733907129
Short name T773
Test name
Test status
Simulation time 930872236 ps
CPU time 2.58 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 197600 kb
Host smart-68719b40-012d-4dea-93f2-6ea150bd8262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733907129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3733907129
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3046860341
Short name T87
Test name
Test status
Simulation time 19897539 ps
CPU time 0.64 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 194060 kb
Host smart-6b0d8d6d-1d10-4227-bd64-2aaa843a017d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046860341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3046860341
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.42659605
Short name T731
Test name
Test status
Simulation time 27540975 ps
CPU time 0.73 seconds
Started May 05 01:55:20 PM PDT 24
Finished May 05 01:55:21 PM PDT 24
Peak memory 197604 kb
Host smart-dfddbc69-ad30-438e-9dc6-4fd16d220120
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659605 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.42659605
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.958924727
Short name T103
Test name
Test status
Simulation time 26663338 ps
CPU time 0.64 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 195216 kb
Host smart-764c7174-74c4-4562-b494-9f7a1b9638c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958924727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.958924727
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2894529617
Short name T801
Test name
Test status
Simulation time 38353796 ps
CPU time 0.6 seconds
Started May 05 01:55:15 PM PDT 24
Finished May 05 01:55:16 PM PDT 24
Peak memory 193484 kb
Host smart-4723bd4a-dded-46fe-8abe-52ca072146ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894529617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2894529617
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4155035197
Short name T101
Test name
Test status
Simulation time 49397272 ps
CPU time 0.74 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 195860 kb
Host smart-7faef1fb-aa1b-4ce8-8d6c-9a3f95c15716
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155035197 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4155035197
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2853470217
Short name T772
Test name
Test status
Simulation time 86804348 ps
CPU time 1.21 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 197776 kb
Host smart-41d1d446-ca47-43dc-b8ca-c1b42abeec82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853470217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2853470217
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.152494413
Short name T834
Test name
Test status
Simulation time 177695659 ps
CPU time 0.91 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197220 kb
Host smart-19c17758-5c35-4bfc-b1fe-6c28b9cb8e9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152494413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.152494413
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2571123222
Short name T797
Test name
Test status
Simulation time 11989436 ps
CPU time 0.61 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:42 PM PDT 24
Peak memory 193472 kb
Host smart-d78218c1-0796-41fc-ae24-4505e54ed190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571123222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2571123222
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3897660291
Short name T734
Test name
Test status
Simulation time 54768337 ps
CPU time 0.6 seconds
Started May 05 01:55:41 PM PDT 24
Finished May 05 01:55:42 PM PDT 24
Peak memory 193552 kb
Host smart-f05dc1c4-6bf8-4315-929e-e69e6dd1cb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897660291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3897660291
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2547771577
Short name T800
Test name
Test status
Simulation time 46214561 ps
CPU time 0.61 seconds
Started May 05 01:55:37 PM PDT 24
Finished May 05 01:55:38 PM PDT 24
Peak memory 193400 kb
Host smart-f8ad2db8-7bec-4ca2-8870-33813e042d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547771577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2547771577
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1135322184
Short name T778
Test name
Test status
Simulation time 45736149 ps
CPU time 0.72 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 194092 kb
Host smart-c99b42c6-53d0-43b2-b8a4-f38d513da74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135322184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1135322184
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1088896241
Short name T722
Test name
Test status
Simulation time 73826556 ps
CPU time 0.59 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:47 PM PDT 24
Peak memory 193500 kb
Host smart-2ff0d4b5-659e-45d0-8ff3-48e3c1e26812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088896241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1088896241
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3819432815
Short name T745
Test name
Test status
Simulation time 52003525 ps
CPU time 0.59 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 193624 kb
Host smart-f82d54b3-e900-4311-b061-7215d8494f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819432815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3819432815
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.334382377
Short name T829
Test name
Test status
Simulation time 30355489 ps
CPU time 0.57 seconds
Started May 05 01:55:32 PM PDT 24
Finished May 05 01:55:33 PM PDT 24
Peak memory 193412 kb
Host smart-6a7f6f19-4b00-40da-b249-0e7b12b1691f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334382377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.334382377
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.560670692
Short name T775
Test name
Test status
Simulation time 12691622 ps
CPU time 0.57 seconds
Started May 05 01:55:29 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 193424 kb
Host smart-147aafae-0399-4033-9989-9917476ac5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560670692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.560670692
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2070678279
Short name T833
Test name
Test status
Simulation time 13512813 ps
CPU time 0.6 seconds
Started May 05 01:55:37 PM PDT 24
Finished May 05 01:55:38 PM PDT 24
Peak memory 193372 kb
Host smart-1c2e9630-9707-4bcf-ac81-b0929b9ff809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070678279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2070678279
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2011546162
Short name T835
Test name
Test status
Simulation time 56328844 ps
CPU time 0.6 seconds
Started May 05 01:55:34 PM PDT 24
Finished May 05 01:55:35 PM PDT 24
Peak memory 193444 kb
Host smart-cd719cb9-3df3-465d-b797-fbceb1367dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011546162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2011546162
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2780668169
Short name T95
Test name
Test status
Simulation time 17265996 ps
CPU time 0.71 seconds
Started May 05 01:55:19 PM PDT 24
Finished May 05 01:55:21 PM PDT 24
Peak memory 195416 kb
Host smart-bbdb848a-f862-4593-a621-d59785b750c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780668169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2780668169
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.155993101
Short name T739
Test name
Test status
Simulation time 81579586 ps
CPU time 2.89 seconds
Started May 05 01:55:21 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 196380 kb
Host smart-089bcfd8-896e-4d03-8d07-74e33951f424
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155993101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.155993101
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3817784897
Short name T811
Test name
Test status
Simulation time 18674799 ps
CPU time 0.63 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 195148 kb
Host smart-5152166c-0d85-4fc3-bc3b-458adc9a8ea5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817784897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3817784897
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2100888214
Short name T774
Test name
Test status
Simulation time 55844049 ps
CPU time 0.83 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197712 kb
Host smart-4ae2ef50-e51d-4db0-bbef-c96eed81a643
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100888214 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2100888214
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2474824055
Short name T91
Test name
Test status
Simulation time 13944412 ps
CPU time 0.61 seconds
Started May 05 01:55:21 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 195388 kb
Host smart-94b8eca1-9d96-46f0-ad65-4582f4d67966
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474824055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2474824055
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1402970337
Short name T814
Test name
Test status
Simulation time 43451306 ps
CPU time 0.58 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 193500 kb
Host smart-3281af14-4e83-456e-92d3-705872bf7520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402970337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1402970337
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.42218278
Short name T99
Test name
Test status
Simulation time 17242213 ps
CPU time 0.7 seconds
Started May 05 01:55:16 PM PDT 24
Finished May 05 01:55:17 PM PDT 24
Peak memory 195708 kb
Host smart-e72ebc09-ecdd-476b-b5b0-809f11e3bb89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218278 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.gpio_same_csr_outstanding.42218278
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.682763459
Short name T735
Test name
Test status
Simulation time 140458312 ps
CPU time 2.61 seconds
Started May 05 01:55:19 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 197908 kb
Host smart-f83e2794-e2ae-4331-a712-7541168043aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682763459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.682763459
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3054890621
Short name T104
Test name
Test status
Simulation time 122379876 ps
CPU time 1.43 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:20 PM PDT 24
Peak memory 197788 kb
Host smart-06a31466-2e1c-4bc2-ba81-ca1f05ae1e98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054890621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3054890621
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4183795285
Short name T840
Test name
Test status
Simulation time 13834122 ps
CPU time 0.58 seconds
Started May 05 01:55:30 PM PDT 24
Finished May 05 01:55:32 PM PDT 24
Peak memory 194040 kb
Host smart-0728291e-0e2b-4595-9a6d-34d4eed3f92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183795285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4183795285
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.766453982
Short name T785
Test name
Test status
Simulation time 14316665 ps
CPU time 0.65 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:52 PM PDT 24
Peak memory 193464 kb
Host smart-0299d7dd-3fcd-4c63-bcc2-c0d825af59ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766453982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.766453982
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.282124933
Short name T756
Test name
Test status
Simulation time 42598620 ps
CPU time 0.58 seconds
Started May 05 01:55:31 PM PDT 24
Finished May 05 01:55:32 PM PDT 24
Peak memory 193416 kb
Host smart-a4d39616-7e2e-4c6d-90d6-278190b5f911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282124933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.282124933
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3512299185
Short name T796
Test name
Test status
Simulation time 19356274 ps
CPU time 0.56 seconds
Started May 05 01:55:44 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 193440 kb
Host smart-8bac700d-cdd5-4e9d-8734-bcdbb26261eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512299185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3512299185
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1446595056
Short name T747
Test name
Test status
Simulation time 61923703 ps
CPU time 0.57 seconds
Started May 05 01:55:34 PM PDT 24
Finished May 05 01:55:35 PM PDT 24
Peak memory 193432 kb
Host smart-a9f918aa-9ae3-447f-9aff-c13d2b4adbd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446595056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1446595056
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.11054876
Short name T815
Test name
Test status
Simulation time 15191804 ps
CPU time 0.58 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:55:49 PM PDT 24
Peak memory 194072 kb
Host smart-e44f2585-8f9f-48d6-968d-dd23e0e8b26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11054876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.11054876
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2623140521
Short name T733
Test name
Test status
Simulation time 21357072 ps
CPU time 0.62 seconds
Started May 05 01:55:44 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 193420 kb
Host smart-8fe6126f-3741-4c36-8bf3-72bec500f5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623140521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2623140521
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.460541579
Short name T732
Test name
Test status
Simulation time 30450874 ps
CPU time 0.6 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 193408 kb
Host smart-0bbfcfaf-0556-4790-85f2-6e0d89c6c530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460541579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.460541579
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1500318185
Short name T838
Test name
Test status
Simulation time 85073031 ps
CPU time 0.59 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 193368 kb
Host smart-be20baf5-c52a-4959-af16-6c5bbb0685a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500318185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1500318185
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.590676166
Short name T727
Test name
Test status
Simulation time 12247330 ps
CPU time 0.58 seconds
Started May 05 01:55:47 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 193396 kb
Host smart-adccaf20-4b1a-43f3-8a56-50b29341a86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590676166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.590676166
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.258565202
Short name T86
Test name
Test status
Simulation time 18183454 ps
CPU time 0.76 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 195660 kb
Host smart-a9046b1e-128d-4f30-b5ae-09fc7a1eb5ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258565202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.258565202
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.531209697
Short name T80
Test name
Test status
Simulation time 81853959 ps
CPU time 2.96 seconds
Started May 05 01:55:25 PM PDT 24
Finished May 05 01:55:28 PM PDT 24
Peak memory 196468 kb
Host smart-91810d52-7348-4583-8775-8f84c77e8d60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531209697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.531209697
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2474106863
Short name T77
Test name
Test status
Simulation time 52126532 ps
CPU time 0.62 seconds
Started May 05 01:55:31 PM PDT 24
Finished May 05 01:55:32 PM PDT 24
Peak memory 194388 kb
Host smart-85e3e53a-4952-43d6-9d50-b4598c6505d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474106863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2474106863
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1448241524
Short name T784
Test name
Test status
Simulation time 38973385 ps
CPU time 0.83 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 197668 kb
Host smart-23bf589e-a2f0-4b75-808f-d2c35ac0c634
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448241524 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1448241524
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2644774779
Short name T820
Test name
Test status
Simulation time 26868708 ps
CPU time 0.66 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 194284 kb
Host smart-79203737-2125-451b-98fd-714e87b1ba9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644774779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2644774779
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3123485813
Short name T743
Test name
Test status
Simulation time 43748748 ps
CPU time 0.58 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 194108 kb
Host smart-04f94664-2132-4342-ae9e-247d52b88cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123485813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3123485813
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4182695543
Short name T788
Test name
Test status
Simulation time 56741517 ps
CPU time 0.76 seconds
Started May 05 01:55:21 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 195884 kb
Host smart-2b31f519-b9ea-427f-b1cb-21cdf85f0b03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182695543 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4182695543
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3896652748
Short name T750
Test name
Test status
Simulation time 47979453 ps
CPU time 1.27 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197712 kb
Host smart-9ea53e99-7c08-4cc4-a7ea-42d5e26dee2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896652748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3896652748
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3288025804
Short name T31
Test name
Test status
Simulation time 610235411 ps
CPU time 1.44 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:35 PM PDT 24
Peak memory 197764 kb
Host smart-46069651-4454-4c98-b294-9aa4d9f627ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288025804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3288025804
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4101133585
Short name T726
Test name
Test status
Simulation time 67506833 ps
CPU time 0.57 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:41 PM PDT 24
Peak memory 193996 kb
Host smart-3f7382b7-b920-49ab-9ac7-770cbe214c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101133585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4101133585
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.349771964
Short name T819
Test name
Test status
Simulation time 15477602 ps
CPU time 0.61 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 193368 kb
Host smart-d9091cb3-3fe1-44e3-9deb-84c1133f6d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349771964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.349771964
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1768379426
Short name T806
Test name
Test status
Simulation time 16145436 ps
CPU time 0.59 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:52 PM PDT 24
Peak memory 193472 kb
Host smart-2905d48e-06eb-46ca-b4a9-78bf02bd0967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768379426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1768379426
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.53084559
Short name T798
Test name
Test status
Simulation time 45880692 ps
CPU time 0.56 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:34 PM PDT 24
Peak memory 193396 kb
Host smart-f8937b1b-7764-4bc5-8708-4a3e54a7dd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53084559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.53084559
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.404378902
Short name T755
Test name
Test status
Simulation time 17608993 ps
CPU time 0.57 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:55:50 PM PDT 24
Peak memory 194084 kb
Host smart-d8794aba-8742-4253-9676-8124050ba01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404378902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.404378902
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1652190893
Short name T759
Test name
Test status
Simulation time 12885770 ps
CPU time 0.57 seconds
Started May 05 01:55:39 PM PDT 24
Finished May 05 01:55:40 PM PDT 24
Peak memory 193344 kb
Host smart-9492039b-b1d3-4fac-bd4a-28dfb7e7068c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652190893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1652190893
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.435812016
Short name T823
Test name
Test status
Simulation time 36986675 ps
CPU time 0.6 seconds
Started May 05 01:55:47 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 193492 kb
Host smart-f3bab14e-8e4d-46c8-af1d-8b4b15b4af11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435812016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.435812016
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4006351377
Short name T817
Test name
Test status
Simulation time 117083279 ps
CPU time 0.64 seconds
Started May 05 01:55:43 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 193368 kb
Host smart-d6942c84-e31c-46f6-b45a-e68219ac7b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006351377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4006351377
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1371879381
Short name T725
Test name
Test status
Simulation time 12877396 ps
CPU time 0.61 seconds
Started May 05 01:55:43 PM PDT 24
Finished May 05 01:55:44 PM PDT 24
Peak memory 194104 kb
Host smart-a343ca6d-89d8-4521-bd79-fc0c5fe43565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371879381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1371879381
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.361407684
Short name T837
Test name
Test status
Simulation time 18270099 ps
CPU time 0.68 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 194140 kb
Host smart-0051c702-9a61-4aca-ab58-5456fc0bee2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361407684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.361407684
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3125766130
Short name T737
Test name
Test status
Simulation time 56575240 ps
CPU time 0.82 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 197664 kb
Host smart-1c83b6a3-0659-4b8d-a741-5d3cfd1bb9d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125766130 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3125766130
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2559958889
Short name T93
Test name
Test status
Simulation time 18765197 ps
CPU time 0.61 seconds
Started May 05 01:55:23 PM PDT 24
Finished May 05 01:55:24 PM PDT 24
Peak memory 194352 kb
Host smart-84adf1ef-0513-4677-91d1-67890e03da57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559958889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2559958889
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2369365156
Short name T782
Test name
Test status
Simulation time 41233181 ps
CPU time 0.58 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 193348 kb
Host smart-85ac99a9-a1f6-4680-82bc-6037fdc1e344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369365156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2369365156
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.735817462
Short name T98
Test name
Test status
Simulation time 115430308 ps
CPU time 0.67 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 195368 kb
Host smart-630b18d4-f1d1-49ab-9a1f-cea6cfb07577
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735817462 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.735817462
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.632895793
Short name T741
Test name
Test status
Simulation time 117962081 ps
CPU time 3.09 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 197760 kb
Host smart-27a9f6f3-5919-4c9f-b467-571d1835659d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632895793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.632895793
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3303450137
Short name T40
Test name
Test status
Simulation time 255863573 ps
CPU time 1.1 seconds
Started May 05 01:55:25 PM PDT 24
Finished May 05 01:55:27 PM PDT 24
Peak memory 197764 kb
Host smart-12d737c3-a25b-4588-9d21-f8dcef0673ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303450137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3303450137
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4123385879
Short name T791
Test name
Test status
Simulation time 39495734 ps
CPU time 1.09 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 197760 kb
Host smart-4686754f-a692-4d5a-b43d-973cd3983029
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123385879 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4123385879
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1184941211
Short name T88
Test name
Test status
Simulation time 138716467 ps
CPU time 0.62 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 194284 kb
Host smart-0c631191-ed86-46c4-8727-bd235ab550e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184941211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1184941211
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.941419336
Short name T768
Test name
Test status
Simulation time 14812302 ps
CPU time 0.61 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:37 PM PDT 24
Peak memory 193456 kb
Host smart-67464004-19df-4243-af45-108ff7e95b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941419336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.941419336
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1556359496
Short name T792
Test name
Test status
Simulation time 71101020 ps
CPU time 0.64 seconds
Started May 05 01:55:20 PM PDT 24
Finished May 05 01:55:22 PM PDT 24
Peak memory 194376 kb
Host smart-47b2880f-2862-4695-8c8f-2e95e5dea629
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556359496 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1556359496
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2007626167
Short name T723
Test name
Test status
Simulation time 415305817 ps
CPU time 1.95 seconds
Started May 05 01:55:33 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 197760 kb
Host smart-c51d9943-fef3-4c2b-b462-344434147c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007626167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2007626167
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1524303676
Short name T38
Test name
Test status
Simulation time 92207446 ps
CPU time 1.45 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197788 kb
Host smart-cb951265-21e2-4c56-93ca-a15680990fc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524303676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1524303676
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2957060766
Short name T738
Test name
Test status
Simulation time 23711883 ps
CPU time 0.76 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 197664 kb
Host smart-c4d023c0-0d63-4950-8031-1136f5971b7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957060766 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2957060766
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2889236415
Short name T79
Test name
Test status
Simulation time 13337264 ps
CPU time 0.62 seconds
Started May 05 01:55:40 PM PDT 24
Finished May 05 01:55:41 PM PDT 24
Peak memory 194648 kb
Host smart-4bcf3763-7d69-462b-8f0c-f77c72293547
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889236415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2889236415
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3036436290
Short name T740
Test name
Test status
Simulation time 14923241 ps
CPU time 0.57 seconds
Started May 05 01:55:18 PM PDT 24
Finished May 05 01:55:19 PM PDT 24
Peak memory 193440 kb
Host smart-a5e7bd76-86de-4bba-b2a4-47dd8354ac10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036436290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3036436290
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1081864041
Short name T822
Test name
Test status
Simulation time 27630875 ps
CPU time 0.73 seconds
Started May 05 01:55:20 PM PDT 24
Finished May 05 01:55:22 PM PDT 24
Peak memory 194912 kb
Host smart-8d6c7ab3-f582-4df6-8283-d80113f8ba11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081864041 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1081864041
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3558257320
Short name T760
Test name
Test status
Simulation time 229540681 ps
CPU time 3.11 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:27 PM PDT 24
Peak memory 197776 kb
Host smart-0aa930e1-4eba-45d9-9d5f-453945efffac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558257320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3558257320
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3489929276
Short name T813
Test name
Test status
Simulation time 27373590 ps
CPU time 1.02 seconds
Started May 05 01:55:24 PM PDT 24
Finished May 05 01:55:26 PM PDT 24
Peak memory 197624 kb
Host smart-3bc0cc95-1d9e-4eaf-9656-42f35c937e31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489929276 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3489929276
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3003098002
Short name T82
Test name
Test status
Simulation time 14544196 ps
CPU time 0.61 seconds
Started May 05 01:55:21 PM PDT 24
Finished May 05 01:55:22 PM PDT 24
Peak memory 194472 kb
Host smart-d66174b0-2988-4a0f-bb97-0bc2e88a0416
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003098002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3003098002
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3757680730
Short name T742
Test name
Test status
Simulation time 24278206 ps
CPU time 0.59 seconds
Started May 05 01:55:35 PM PDT 24
Finished May 05 01:55:37 PM PDT 24
Peak memory 194064 kb
Host smart-16750d64-10f6-424a-babf-5cd4d4c02a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757680730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3757680730
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2560809465
Short name T102
Test name
Test status
Simulation time 30351627 ps
CPU time 0.73 seconds
Started May 05 01:55:30 PM PDT 24
Finished May 05 01:55:31 PM PDT 24
Peak memory 195752 kb
Host smart-5099a3a7-08fa-408a-b767-c34b15515e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560809465 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2560809465
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1014900275
Short name T762
Test name
Test status
Simulation time 89736797 ps
CPU time 1.55 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 197820 kb
Host smart-3d3c540e-3e31-4cfe-b211-b36e24e532d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014900275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1014900275
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2964731018
Short name T33
Test name
Test status
Simulation time 202232007 ps
CPU time 0.84 seconds
Started May 05 01:55:30 PM PDT 24
Finished May 05 01:55:32 PM PDT 24
Peak memory 197540 kb
Host smart-fa02ed5b-8019-4439-93d4-2c99612eb3c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964731018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2964731018
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3219560906
Short name T729
Test name
Test status
Simulation time 30758932 ps
CPU time 0.87 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:28 PM PDT 24
Peak memory 197708 kb
Host smart-102e2c2d-b3fe-4792-bb47-077c4bb2713c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219560906 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3219560906
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2166434953
Short name T776
Test name
Test status
Simulation time 16491131 ps
CPU time 0.59 seconds
Started May 05 01:55:21 PM PDT 24
Finished May 05 01:55:23 PM PDT 24
Peak memory 193084 kb
Host smart-b40d2390-869b-4042-9b00-bb03a041ac7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166434953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2166434953
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2501197943
Short name T730
Test name
Test status
Simulation time 15495988 ps
CPU time 0.62 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 194108 kb
Host smart-158c9b34-d4f1-4425-b84b-393266325b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501197943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2501197943
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3711341963
Short name T81
Test name
Test status
Simulation time 31075166 ps
CPU time 0.65 seconds
Started May 05 01:55:27 PM PDT 24
Finished May 05 01:55:29 PM PDT 24
Peak memory 195080 kb
Host smart-f8abbff0-8d9e-4f57-a6a0-ce3e9d82a602
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711341963 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3711341963
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3504621946
Short name T753
Test name
Test status
Simulation time 433820904 ps
CPU time 2.14 seconds
Started May 05 01:55:22 PM PDT 24
Finished May 05 01:55:25 PM PDT 24
Peak memory 197764 kb
Host smart-c008b4dc-0283-4bc1-9679-8d279dba3ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504621946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3504621946
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1823942620
Short name T787
Test name
Test status
Simulation time 52499457 ps
CPU time 0.87 seconds
Started May 05 01:55:28 PM PDT 24
Finished May 05 01:55:30 PM PDT 24
Peak memory 196920 kb
Host smart-29f73baf-0fb5-40d4-b6c4-aaf15f2f67b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823942620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1823942620
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.567362928
Short name T240
Test name
Test status
Simulation time 18875460 ps
CPU time 0.62 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 193848 kb
Host smart-221454d6-f9b9-4d7b-96a4-5867a918fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567362928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.567362928
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3126855606
Short name T420
Test name
Test status
Simulation time 434366984 ps
CPU time 12.54 seconds
Started May 05 12:40:32 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 196720 kb
Host smart-59afdf2b-9094-4512-aa3b-f4b1976c77f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126855606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3126855606
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.945325605
Short name T72
Test name
Test status
Simulation time 99930698 ps
CPU time 0.89 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 197900 kb
Host smart-b1e5f7d2-e70a-420b-9cd9-9aa2d3575e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945325605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.945325605
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3937729425
Short name T231
Test name
Test status
Simulation time 330267912 ps
CPU time 1.23 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 195892 kb
Host smart-88923b5d-4072-47a6-be01-1b27263dd489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937729425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3937729425
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3699304081
Short name T503
Test name
Test status
Simulation time 33046501 ps
CPU time 1.29 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 196680 kb
Host smart-e486d93e-6a32-438b-b8be-2ee322d07da5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699304081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3699304081
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.6236590
Short name T499
Test name
Test status
Simulation time 47470149 ps
CPU time 1.54 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 195832 kb
Host smart-e14c2225-f6ed-453b-9f37-08511fe049f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6236590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.6236590
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2895078613
Short name T134
Test name
Test status
Simulation time 214108239 ps
CPU time 1.17 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 195688 kb
Host smart-a2de2170-5462-4efa-9a92-d1f3a76324cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895078613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2895078613
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2532737457
Short name T398
Test name
Test status
Simulation time 189281273 ps
CPU time 1.12 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 197956 kb
Host smart-4b13d550-ae39-4dc0-87ac-3df7b489f7da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532737457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2532737457
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.170340114
Short name T279
Test name
Test status
Simulation time 92816181 ps
CPU time 3.98 seconds
Started May 05 12:40:35 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 197876 kb
Host smart-c11f5179-29eb-47f4-b9f3-b41a34cc9ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170340114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.170340114
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1601771595
Short name T403
Test name
Test status
Simulation time 112047832 ps
CPU time 0.86 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:23 PM PDT 24
Peak memory 196188 kb
Host smart-248a27c9-7553-43c4-9680-7aa3093f67c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601771595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1601771595
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.780232412
Short name T177
Test name
Test status
Simulation time 1202245501 ps
CPU time 1.21 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 195640 kb
Host smart-e98c4fd4-c204-4146-87ec-06585efab7ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780232412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.780232412
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.4001209079
Short name T4
Test name
Test status
Simulation time 17285156444 ps
CPU time 25.71 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 198096 kb
Host smart-3dcac277-1c3b-4dfd-88c9-6f7f93f19500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001209079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.4001209079
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2178487497
Short name T232
Test name
Test status
Simulation time 14347598 ps
CPU time 0.57 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 194000 kb
Host smart-379820bc-0053-4a41-93e7-5aa4b4780ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178487497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2178487497
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.51090337
Short name T225
Test name
Test status
Simulation time 82076567 ps
CPU time 0.92 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:21 PM PDT 24
Peak memory 195828 kb
Host smart-e413bf7d-f898-4fd7-93d7-1c957b18304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51090337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.51090337
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3490420554
Short name T129
Test name
Test status
Simulation time 4197558542 ps
CPU time 22.57 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 197240 kb
Host smart-e61db140-08c0-46e8-a9ee-4ecf8b65a9b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490420554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3490420554
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3257532880
Short name T529
Test name
Test status
Simulation time 55403598 ps
CPU time 0.97 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 197120 kb
Host smart-16c77194-6078-4423-8541-08cf7193aa90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257532880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3257532880
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2079381054
Short name T48
Test name
Test status
Simulation time 261628657 ps
CPU time 1.24 seconds
Started May 05 12:40:39 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 195876 kb
Host smart-ed37e14a-392d-4ccf-9521-4c908d22d943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079381054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2079381054
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.451468569
Short name T146
Test name
Test status
Simulation time 143885480 ps
CPU time 1.67 seconds
Started May 05 12:40:39 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 197788 kb
Host smart-85ab1c82-2eb0-4007-9a38-bd05d145b177
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451468569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.451468569
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4103015993
Short name T350
Test name
Test status
Simulation time 608363469 ps
CPU time 3.21 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 197948 kb
Host smart-6e7c8e8c-72dd-4221-8a14-0c9ff9a6f20c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103015993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4103015993
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.153953357
Short name T628
Test name
Test status
Simulation time 47188358 ps
CPU time 0.73 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 195976 kb
Host smart-6ca8e709-c193-4e4f-a448-99472bdf9c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153953357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.153953357
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3290239375
Short name T182
Test name
Test status
Simulation time 82202344 ps
CPU time 1.23 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:23 PM PDT 24
Peak memory 196804 kb
Host smart-6634c521-6997-44e8-b7ec-5e05107dd999
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290239375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3290239375
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2696778041
Short name T710
Test name
Test status
Simulation time 142887366 ps
CPU time 1.57 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 197932 kb
Host smart-9df4076a-6c17-46a3-a9ad-58e0feda8ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696778041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2696778041
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2025095583
Short name T47
Test name
Test status
Simulation time 64535967 ps
CPU time 0.77 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 213576 kb
Host smart-ffc314e4-c761-4b0c-b3b1-b83b654b671c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025095583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2025095583
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.613619808
Short name T390
Test name
Test status
Simulation time 81575808 ps
CPU time 1.32 seconds
Started May 05 12:40:50 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 196708 kb
Host smart-9456f40a-5ffa-44d0-9dca-ba621e0075df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613619808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.613619808
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1618147542
Short name T263
Test name
Test status
Simulation time 317503543 ps
CPU time 1.29 seconds
Started May 05 12:40:29 PM PDT 24
Finished May 05 12:40:31 PM PDT 24
Peak memory 196696 kb
Host smart-4c6a155c-4747-47cb-a47b-e2ed78936a21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618147542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1618147542
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.472138143
Short name T556
Test name
Test status
Simulation time 8022117497 ps
CPU time 207.49 seconds
Started May 05 12:40:25 PM PDT 24
Finished May 05 12:43:53 PM PDT 24
Peak memory 198192 kb
Host smart-ea56de1c-b266-46e7-ae11-95a32d889bfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472138143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.472138143
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2696101529
Short name T367
Test name
Test status
Simulation time 13505876 ps
CPU time 0.57 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:50 PM PDT 24
Peak memory 193804 kb
Host smart-06508005-af50-4d00-9dd5-ac41fad30ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696101529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2696101529
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.78385557
Short name T300
Test name
Test status
Simulation time 88251576 ps
CPU time 0.82 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 195256 kb
Host smart-d377cbb0-8a76-4a64-b331-1973f98a868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78385557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.78385557
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4136907097
Short name T510
Test name
Test status
Simulation time 3061372040 ps
CPU time 25.76 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 196924 kb
Host smart-6d7dc0b8-dc52-4151-887a-e60dd830b7b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136907097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4136907097
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.79722549
Short name T210
Test name
Test status
Simulation time 113473132 ps
CPU time 0.69 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 194632 kb
Host smart-96dddf10-3078-4d81-9f11-1008a5818c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79722549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.79722549
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4240175278
Short name T224
Test name
Test status
Simulation time 93417372 ps
CPU time 1.37 seconds
Started May 05 12:40:50 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 197180 kb
Host smart-099a75fc-b324-40f4-9bcc-aa7396e36bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240175278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4240175278
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2623309044
Short name T118
Test name
Test status
Simulation time 239245930 ps
CPU time 1.81 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 198008 kb
Host smart-742f305a-44fd-4044-94fd-86ada8772762
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623309044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2623309044
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2323489160
Short name T169
Test name
Test status
Simulation time 208788974 ps
CPU time 1.41 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 195760 kb
Host smart-25615026-329d-4b52-bf47-8cba3a04bbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323489160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2323489160
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2954605691
Short name T266
Test name
Test status
Simulation time 57077915 ps
CPU time 0.79 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 196140 kb
Host smart-bc0bfff2-23ea-4ded-9189-486d6479ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954605691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2954605691
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2052839121
Short name T111
Test name
Test status
Simulation time 18910276 ps
CPU time 0.74 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 195376 kb
Host smart-32a1b4ed-2310-470b-a5c2-10e886745917
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052839121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2052839121
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2384981672
Short name T485
Test name
Test status
Simulation time 83516057 ps
CPU time 1.37 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 197836 kb
Host smart-28182157-02bb-4b5e-81af-96c71c4c5217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384981672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2384981672
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.81990111
Short name T555
Test name
Test status
Simulation time 51558309 ps
CPU time 1.37 seconds
Started May 05 12:40:53 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196656 kb
Host smart-a6028584-1b11-4c70-a459-e82ecb4a7e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81990111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.81990111
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3194992068
Short name T379
Test name
Test status
Simulation time 94066858 ps
CPU time 1.14 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 195536 kb
Host smart-5b9e8815-b7f1-45e9-acef-68108b4a967c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194992068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3194992068
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.929767204
Short name T321
Test name
Test status
Simulation time 20775119746 ps
CPU time 139.45 seconds
Started May 05 12:40:29 PM PDT 24
Finished May 05 12:42:48 PM PDT 24
Peak memory 198060 kb
Host smart-2e0bc4bb-70a1-42f5-82f9-9e83b8322434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929767204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.929767204
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1703335785
Short name T448
Test name
Test status
Simulation time 78004013353 ps
CPU time 1695.91 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 01:09:12 PM PDT 24
Peak memory 198088 kb
Host smart-b27d9129-c204-4aa9-8df7-12955f84138f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1703335785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1703335785
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1901447392
Short name T319
Test name
Test status
Simulation time 26845190 ps
CPU time 0.57 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 193968 kb
Host smart-8d91673b-fcee-4ebb-b226-b5020709cc82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901447392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1901447392
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2311912857
Short name T626
Test name
Test status
Simulation time 42266258 ps
CPU time 0.8 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 195352 kb
Host smart-b989ca4f-d829-46a2-95aa-d610c8d8cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311912857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2311912857
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.648021108
Short name T531
Test name
Test status
Simulation time 2566970972 ps
CPU time 21.7 seconds
Started May 05 12:40:50 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 196836 kb
Host smart-45916200-a9d4-468b-87bf-a66b22896aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648021108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.648021108
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3113288957
Short name T442
Test name
Test status
Simulation time 63119023 ps
CPU time 0.69 seconds
Started May 05 12:40:37 PM PDT 24
Finished May 05 12:40:39 PM PDT 24
Peak memory 194736 kb
Host smart-85457652-9616-45df-aa45-3014a08338e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113288957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3113288957
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4138489337
Short name T589
Test name
Test status
Simulation time 55038432 ps
CPU time 0.73 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 195396 kb
Host smart-5536f957-aeae-435d-8d41-b2236e2b7531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138489337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4138489337
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2475258683
Short name T632
Test name
Test status
Simulation time 135072464 ps
CPU time 1.63 seconds
Started May 05 12:40:48 PM PDT 24
Finished May 05 12:40:51 PM PDT 24
Peak memory 196648 kb
Host smart-56e51f54-866f-40e0-9ee2-222245e3e9cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475258683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2475258683
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1574539349
Short name T278
Test name
Test status
Simulation time 314332528 ps
CPU time 3.02 seconds
Started May 05 12:40:50 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 197100 kb
Host smart-89e260d3-d8c9-46ab-92f1-0c6c817a63c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574539349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1574539349
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1710816668
Short name T163
Test name
Test status
Simulation time 111056251 ps
CPU time 0.86 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 196208 kb
Host smart-f204a7d1-7491-4c24-ba9f-b49983eb22f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710816668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1710816668
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.409755055
Short name T625
Test name
Test status
Simulation time 62430177 ps
CPU time 0.84 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:50 PM PDT 24
Peak memory 196388 kb
Host smart-fa2d8ee9-3660-483b-9ef8-36190a06fa9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409755055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.409755055
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.791355680
Short name T343
Test name
Test status
Simulation time 383951375 ps
CPU time 3.69 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 197876 kb
Host smart-f6732a2e-13dc-4a6b-baa0-452f8b97401a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791355680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.791355680
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1016980339
Short name T304
Test name
Test status
Simulation time 241502386 ps
CPU time 1.3 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196236 kb
Host smart-b187d5c0-755a-463c-8fbd-2793350e1100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016980339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1016980339
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1947004491
Short name T329
Test name
Test status
Simulation time 122963055 ps
CPU time 1.33 seconds
Started May 05 12:40:53 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196652 kb
Host smart-9e866f7b-a6b0-4a8b-8229-62abc53c21ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947004491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1947004491
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3869442414
Short name T432
Test name
Test status
Simulation time 177661008581 ps
CPU time 187.53 seconds
Started May 05 12:40:56 PM PDT 24
Finished May 05 12:44:04 PM PDT 24
Peak memory 198052 kb
Host smart-56579b5a-fa04-471b-85b2-67af504fcc31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869442414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3869442414
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3032715470
Short name T491
Test name
Test status
Simulation time 25396620 ps
CPU time 0.57 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 193844 kb
Host smart-f56a7f98-2935-4439-9ec4-0a109ccbf7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032715470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3032715470
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3836870495
Short name T695
Test name
Test status
Simulation time 98252733 ps
CPU time 0.91 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 195844 kb
Host smart-5fdcb7e9-f599-4c38-ac8d-12c6f8511c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836870495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3836870495
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.351158684
Short name T679
Test name
Test status
Simulation time 4206661704 ps
CPU time 27.28 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:41:20 PM PDT 24
Peak memory 198068 kb
Host smart-13ec9810-1516-4e82-8263-85b305d64d33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351158684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.351158684
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.365263367
Short name T222
Test name
Test status
Simulation time 156158844 ps
CPU time 0.79 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 195912 kb
Host smart-27dc06a4-f0a2-4a60-ba37-2a3d826dea24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365263367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.365263367
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2395205964
Short name T110
Test name
Test status
Simulation time 159963375 ps
CPU time 1.21 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 196008 kb
Host smart-2e3b5e9d-7374-4fd4-8480-404805d32563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395205964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2395205964
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2431951671
Short name T114
Test name
Test status
Simulation time 37850242 ps
CPU time 1.65 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 197932 kb
Host smart-fc12fd3f-1b01-432f-aa39-25ba5ec3e548
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431951671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2431951671
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3581241671
Short name T341
Test name
Test status
Simulation time 36071883 ps
CPU time 0.95 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 196304 kb
Host smart-e85fdab4-a0e3-4aee-a0f5-63a5c97de33b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581241671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3581241671
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.589294
Short name T452
Test name
Test status
Simulation time 60171115 ps
CPU time 1.24 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 196528 kb
Host smart-dbf3729a-4ead-4b5c-b097-ea15654c89ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.589294
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3693025515
Short name T681
Test name
Test status
Simulation time 48965795 ps
CPU time 0.7 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 194944 kb
Host smart-095d8ddc-5df3-449d-bed6-ecc5ed320d92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693025515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3693025515
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3008896656
Short name T159
Test name
Test status
Simulation time 180723135 ps
CPU time 5.6 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 197872 kb
Host smart-d181ca6b-395f-4fdb-b854-f82a51f980b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008896656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3008896656
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2597529570
Short name T490
Test name
Test status
Simulation time 41400196 ps
CPU time 1.29 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 195736 kb
Host smart-2ecaf6e0-7658-415f-955f-acb38f65ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597529570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2597529570
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2355205990
Short name T313
Test name
Test status
Simulation time 45286048 ps
CPU time 1.21 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 196468 kb
Host smart-0d3d3aad-890f-4019-978f-cdcfee628361
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355205990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2355205990
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2237759107
Short name T439
Test name
Test status
Simulation time 24526172158 ps
CPU time 118.83 seconds
Started May 05 12:41:00 PM PDT 24
Finished May 05 12:43:00 PM PDT 24
Peak memory 198060 kb
Host smart-f49fc041-bf0d-4b2b-8daa-e7d9c50573bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237759107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2237759107
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3286301761
Short name T425
Test name
Test status
Simulation time 43029441445 ps
CPU time 914.37 seconds
Started May 05 12:41:00 PM PDT 24
Finished May 05 12:56:16 PM PDT 24
Peak memory 198100 kb
Host smart-78ce8313-ce59-455c-a17d-714c05d691cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3286301761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3286301761
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2195205895
Short name T184
Test name
Test status
Simulation time 95191451 ps
CPU time 0.59 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 192632 kb
Host smart-d4400c93-bc06-413a-bdcd-12e7edc38719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195205895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2195205895
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1000654162
Short name T645
Test name
Test status
Simulation time 43507501 ps
CPU time 0.94 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 196456 kb
Host smart-8ea28a8b-c41f-49c8-85e5-9fe90945dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000654162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1000654162
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3295902249
Short name T50
Test name
Test status
Simulation time 3038227530 ps
CPU time 21.24 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196792 kb
Host smart-85c739dd-174a-475b-8569-228a07c2b942
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295902249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3295902249
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3176158185
Short name T687
Test name
Test status
Simulation time 461258255 ps
CPU time 0.94 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 197096 kb
Host smart-f00ff96c-d7f6-4de4-b95c-5d32c3f81423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176158185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3176158185
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3146400973
Short name T155
Test name
Test status
Simulation time 651302175 ps
CPU time 0.95 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 195688 kb
Host smart-b610968c-d8a2-4eb0-86ca-4a4e3544d111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146400973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3146400973
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.816242610
Short name T315
Test name
Test status
Simulation time 113064877 ps
CPU time 1.18 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 196788 kb
Host smart-abe215d5-d999-4009-800b-2a534a7417db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816242610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.816242610
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1380247295
Short name T218
Test name
Test status
Simulation time 51601718 ps
CPU time 1.74 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 195952 kb
Host smart-d7cebbbf-f485-4ec6-8165-4f2267b4433a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380247295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1380247295
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2361166904
Short name T127
Test name
Test status
Simulation time 63155610 ps
CPU time 1.08 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 195980 kb
Host smart-b50c3260-c38d-41c2-b005-985c8a6d9add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361166904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2361166904
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1597658418
Short name T253
Test name
Test status
Simulation time 118563817 ps
CPU time 0.86 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 197140 kb
Host smart-c2c96223-2104-4e13-b239-8885e5e18aa5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597658418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1597658418
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3354777731
Short name T700
Test name
Test status
Simulation time 657418806 ps
CPU time 4.8 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 197744 kb
Host smart-404648c9-d926-4783-b171-1298864bc77d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354777731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3354777731
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1338667926
Short name T49
Test name
Test status
Simulation time 33683639 ps
CPU time 0.93 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 196036 kb
Host smart-b6d13dc8-afb4-4eb1-8eaf-6d48622edd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338667926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1338667926
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.469942874
Short name T497
Test name
Test status
Simulation time 35570413 ps
CPU time 0.81 seconds
Started May 05 12:40:47 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 195092 kb
Host smart-1a97d0a9-4638-47ee-b7e7-835721f79ed4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469942874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.469942874
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3987858669
Short name T667
Test name
Test status
Simulation time 46869244266 ps
CPU time 158.87 seconds
Started May 05 12:40:36 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 198092 kb
Host smart-12c03909-4a71-4bba-b014-82b66944dc91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987858669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3987858669
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.89060909
Short name T67
Test name
Test status
Simulation time 11218133 ps
CPU time 0.64 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:41:34 PM PDT 24
Peak memory 193868 kb
Host smart-92922fa4-a778-43b3-ac79-391986a6d89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89060909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.89060909
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3230453385
Short name T235
Test name
Test status
Simulation time 20324531 ps
CPU time 0.7 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 195252 kb
Host smart-38adca51-7e45-4c29-883f-73162b56f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230453385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3230453385
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3137307075
Short name T344
Test name
Test status
Simulation time 173386408 ps
CPU time 7.18 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196200 kb
Host smart-27998e96-594e-4b56-b9d6-ca3e25f31317
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137307075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3137307075
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3176596192
Short name T704
Test name
Test status
Simulation time 538463903 ps
CPU time 1.11 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:51 PM PDT 24
Peak memory 196364 kb
Host smart-7561f736-000e-4613-b136-4ba89b72cbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176596192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3176596192
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3586097719
Short name T288
Test name
Test status
Simulation time 254542457 ps
CPU time 0.92 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 195964 kb
Host smart-4b8ad5dd-8469-4f28-a2be-687fe65ed3ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586097719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3586097719
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3944289710
Short name T476
Test name
Test status
Simulation time 87617778 ps
CPU time 3.53 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 198008 kb
Host smart-df6123c3-0ae1-4358-809c-1f1a4ab5c720
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944289710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3944289710
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3336015905
Short name T296
Test name
Test status
Simulation time 91153379 ps
CPU time 1.58 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 195740 kb
Host smart-5bf88df7-8ea7-47ea-9165-5a21c7aa3f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336015905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3336015905
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4165020444
Short name T401
Test name
Test status
Simulation time 81690303 ps
CPU time 1.06 seconds
Started May 05 12:40:48 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 196464 kb
Host smart-ff151465-bd91-4d14-b3b7-0a5f5b5b1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165020444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4165020444
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3065215230
Short name T718
Test name
Test status
Simulation time 293509095 ps
CPU time 1.14 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 196508 kb
Host smart-f562fbf9-9026-4e8f-a61c-7e445bcb8c26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065215230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3065215230
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1873125200
Short name T495
Test name
Test status
Simulation time 49511708 ps
CPU time 2.34 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 197936 kb
Host smart-bed1bddf-1b10-4081-8100-8d2efeeb65d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873125200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1873125200
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1413919987
Short name T181
Test name
Test status
Simulation time 38940454 ps
CPU time 1.05 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:05 PM PDT 24
Peak memory 195740 kb
Host smart-1e307bc7-0842-4cb4-a105-aa78d16776fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413919987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1413919987
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2992012318
Short name T474
Test name
Test status
Simulation time 66536167 ps
CPU time 0.93 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 196256 kb
Host smart-275582bc-cee5-432a-b5dd-ae8cf61d6441
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992012318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2992012318
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2857263459
Short name T156
Test name
Test status
Simulation time 17296377674 ps
CPU time 64.94 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:42:15 PM PDT 24
Peak memory 198108 kb
Host smart-a9f4173b-ff53-4ed3-920a-012c2d29d1ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857263459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2857263459
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.15770558
Short name T608
Test name
Test status
Simulation time 12362367 ps
CPU time 0.57 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 193776 kb
Host smart-a4c93bd4-36c5-44d3-a556-a252ee2fb72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15770558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.15770558
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3905967042
Short name T428
Test name
Test status
Simulation time 24452234 ps
CPU time 0.75 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 195756 kb
Host smart-3d82a24b-6616-4a74-abbf-cc460e1973af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905967042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3905967042
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3840717920
Short name T342
Test name
Test status
Simulation time 1751429559 ps
CPU time 23.16 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195372 kb
Host smart-ff9d8b50-9de9-45ee-aef4-8171cdae068c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840717920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3840717920
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2258656541
Short name T481
Test name
Test status
Simulation time 57944834 ps
CPU time 0.83 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 195876 kb
Host smart-6af26a0e-8b12-4a2e-9578-f95cdd958e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258656541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2258656541
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.377355313
Short name T446
Test name
Test status
Simulation time 81603462 ps
CPU time 0.8 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 195564 kb
Host smart-75e00a31-41ab-42e3-a969-31848648088e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377355313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.377355313
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3274065789
Short name T629
Test name
Test status
Simulation time 247453472 ps
CPU time 2.24 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 198068 kb
Host smart-b3a0c765-ba5c-4347-8ec7-07e9858ca2ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274065789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3274065789
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2823218532
Short name T630
Test name
Test status
Simulation time 99141801 ps
CPU time 2.25 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:52 PM PDT 24
Peak memory 197108 kb
Host smart-3af78a81-9892-46d8-9aa2-7d01bb30e5be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823218532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2823218532
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1054371318
Short name T305
Test name
Test status
Simulation time 184754066 ps
CPU time 1.14 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 195984 kb
Host smart-4191037e-5514-4aaa-bdba-2c81fb9de1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054371318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1054371318
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.407391274
Short name T466
Test name
Test status
Simulation time 210770349 ps
CPU time 1.02 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 196472 kb
Host smart-34d4712d-4b71-4e40-989a-f43265321e5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407391274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.407391274
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1425643548
Short name T494
Test name
Test status
Simulation time 528004559 ps
CPU time 1.64 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 197716 kb
Host smart-e3ceab96-7912-4086-aa6c-76ca18a37e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425643548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1425643548
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.558281387
Short name T546
Test name
Test status
Simulation time 17064473 ps
CPU time 0.69 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 194192 kb
Host smart-458e23a3-72e7-4e0c-a87d-bc2ef35d2e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558281387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.558281387
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.995331785
Short name T654
Test name
Test status
Simulation time 229304326 ps
CPU time 1.06 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:05 PM PDT 24
Peak memory 196260 kb
Host smart-357b196f-30d8-4e0b-9833-09ec78d3081d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995331785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.995331785
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1342292278
Short name T606
Test name
Test status
Simulation time 50768128070 ps
CPU time 130.77 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 198120 kb
Host smart-82e838c9-3410-4d34-b1e2-c93823219f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342292278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1342292278
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3358182963
Short name T64
Test name
Test status
Simulation time 438820439651 ps
CPU time 2219.19 seconds
Started May 05 12:40:53 PM PDT 24
Finished May 05 01:17:54 PM PDT 24
Peak memory 198144 kb
Host smart-7500207f-0035-4855-af79-3f2eb43aeb19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3358182963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3358182963
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1388175385
Short name T395
Test name
Test status
Simulation time 14021348 ps
CPU time 0.58 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 193828 kb
Host smart-f70de5cc-6994-4d42-a41e-3cbec4795b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388175385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1388175385
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1715326044
Short name T188
Test name
Test status
Simulation time 98780773 ps
CPU time 0.83 seconds
Started May 05 12:40:56 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 196956 kb
Host smart-b9bff2dc-e5b4-4c7a-913f-6c83e39ea420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715326044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1715326044
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3329078717
Short name T459
Test name
Test status
Simulation time 527051780 ps
CPU time 9.78 seconds
Started May 05 12:41:00 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196916 kb
Host smart-cedd578e-38ce-4982-9fe6-95c56cd627d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329078717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3329078717
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2166797094
Short name T109
Test name
Test status
Simulation time 49275675 ps
CPU time 0.71 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 194532 kb
Host smart-97a6271e-3b80-48c4-af74-192bed45e5f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166797094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2166797094
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1086824424
Short name T641
Test name
Test status
Simulation time 51213875 ps
CPU time 0.74 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 195280 kb
Host smart-29550a0c-2d05-47fb-97f6-39fcc0dc52fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086824424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1086824424
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4123358900
Short name T720
Test name
Test status
Simulation time 75249892 ps
CPU time 2.81 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 197880 kb
Host smart-d1b2ce00-aada-495f-9c39-19d9a9ce227d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123358900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4123358900
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.42878474
Short name T123
Test name
Test status
Simulation time 187084435 ps
CPU time 1.69 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 195972 kb
Host smart-68a72173-ed78-4b91-ade5-d810b2b5ae5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.42878474
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.507958174
Short name T73
Test name
Test status
Simulation time 208838294 ps
CPU time 0.83 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196024 kb
Host smart-9cd2a6f1-9ffd-4ba0-a7aa-d58f0ae2dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507958174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.507958174
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2044580139
Short name T203
Test name
Test status
Simulation time 29084463 ps
CPU time 0.65 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 195032 kb
Host smart-c382dba8-6bc6-4e87-afc2-ba21a727a79a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044580139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2044580139
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1750040368
Short name T243
Test name
Test status
Simulation time 201173722 ps
CPU time 4.28 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197904 kb
Host smart-3118f676-5d8c-4b76-9804-73a41311dced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750040368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1750040368
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.595074699
Short name T670
Test name
Test status
Simulation time 206974023 ps
CPU time 0.97 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 195624 kb
Host smart-7d95768f-9f89-41e6-9b03-b899d7290473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595074699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.595074699
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3564816265
Short name T223
Test name
Test status
Simulation time 89535892 ps
CPU time 0.94 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 195212 kb
Host smart-56054a47-6c06-4e88-8872-96f4d4074307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564816265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3564816265
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.602767424
Short name T14
Test name
Test status
Simulation time 25431828178 ps
CPU time 207.75 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 198120 kb
Host smart-8fbffb8e-9329-4877-8c08-e3baf05cc6a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602767424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.602767424
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1682815253
Short name T544
Test name
Test status
Simulation time 44272411 ps
CPU time 0.55 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 193760 kb
Host smart-ae05b7c2-059b-45ef-b873-202ddb8a5362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682815253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1682815253
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2442374740
Short name T377
Test name
Test status
Simulation time 212335492 ps
CPU time 0.9 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 195868 kb
Host smart-314cca4c-de08-46f4-a3e0-3bb0d62d3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442374740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2442374740
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2762959519
Short name T267
Test name
Test status
Simulation time 7214673383 ps
CPU time 24.79 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:41:36 PM PDT 24
Peak memory 196784 kb
Host smart-816d517d-4bdf-4007-8a33-6ddad8a8582a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762959519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2762959519
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.228929247
Short name T693
Test name
Test status
Simulation time 1242007912 ps
CPU time 1.05 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196448 kb
Host smart-acfe5080-1f70-4eca-a422-1521e8e949f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228929247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.228929247
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2552150046
Short name T121
Test name
Test status
Simulation time 599670748 ps
CPU time 1.18 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 196592 kb
Host smart-b669bee8-aefb-43a8-aafc-ac62afad8784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552150046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2552150046
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.91378601
Short name T400
Test name
Test status
Simulation time 26329944 ps
CPU time 1.14 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 197508 kb
Host smart-66c9bd35-749f-4ba9-b770-0c8168bef6a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91378601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.gpio_intr_with_filter_rand_intr_event.91378601
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4061983040
Short name T242
Test name
Test status
Simulation time 113940666 ps
CPU time 1.7 seconds
Started May 05 12:41:00 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 195688 kb
Host smart-0eac58f5-6bdb-4665-91de-08c66cc49597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061983040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4061983040
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3354059477
Short name T659
Test name
Test status
Simulation time 60501006 ps
CPU time 1.04 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 195708 kb
Host smart-55717179-ca7e-438c-9bb6-ccbdac736df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354059477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3354059477
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2243811650
Short name T13
Test name
Test status
Simulation time 90799489 ps
CPU time 1.3 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 197912 kb
Host smart-5a260d41-bd87-46dc-bb9d-0f1e96e0be3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243811650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2243811650
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3256373602
Short name T200
Test name
Test status
Simulation time 184444130 ps
CPU time 4.29 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197856 kb
Host smart-e9347ebf-f692-4939-945f-25344913019c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256373602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3256373602
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2762115037
Short name T612
Test name
Test status
Simulation time 74661070 ps
CPU time 1.15 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 196628 kb
Host smart-4a01dd95-fae6-4533-9adb-76923310e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762115037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2762115037
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3904415284
Short name T166
Test name
Test status
Simulation time 151267301 ps
CPU time 0.99 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 195356 kb
Host smart-beb03982-5584-4427-883b-bf877078e485
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904415284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3904415284
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1148741589
Short name T276
Test name
Test status
Simulation time 4350106482 ps
CPU time 30.95 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 198024 kb
Host smart-9f394e54-13f5-4e8b-9c95-31d500091d30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148741589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1148741589
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1217175039
Short name T642
Test name
Test status
Simulation time 12942446 ps
CPU time 0.56 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 194496 kb
Host smart-2ccdf27f-3694-4ef1-bd5e-837fc0bac1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217175039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1217175039
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.146262627
Short name T613
Test name
Test status
Simulation time 35651427 ps
CPU time 0.78 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 195840 kb
Host smart-3058be96-8375-4e14-b28c-7a2739c89939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146262627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.146262627
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4191680869
Short name T17
Test name
Test status
Simulation time 2404359661 ps
CPU time 5.38 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 196756 kb
Host smart-9e052afa-4e18-4d99-b73a-e4ff75b42d73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191680869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4191680869
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.507845252
Short name T160
Test name
Test status
Simulation time 73710320 ps
CPU time 0.99 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196508 kb
Host smart-81b767b8-f56a-4298-a057-d215a13bf0ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507845252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.507845252
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1335240026
Short name T133
Test name
Test status
Simulation time 183507891 ps
CPU time 1.3 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:58 PM PDT 24
Peak memory 196396 kb
Host smart-a5291000-054f-438e-ab0b-342837c0f315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335240026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1335240026
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1229858645
Short name T205
Test name
Test status
Simulation time 34444177 ps
CPU time 1.24 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196564 kb
Host smart-c8fc4dc2-f7c9-4e70-b087-966dfdbd9967
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229858645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1229858645
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.844411791
Short name T131
Test name
Test status
Simulation time 194455297 ps
CPU time 1.02 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 195592 kb
Host smart-83e1f50f-be0d-4ef3-82e6-f0c43e238e52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844411791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
844411791
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3306129930
Short name T579
Test name
Test status
Simulation time 652071599 ps
CPU time 1.05 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 195708 kb
Host smart-4537e2c1-5cf4-4732-87ed-70a41b77709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306129930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3306129930
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1534083380
Short name T712
Test name
Test status
Simulation time 62844705 ps
CPU time 1.18 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 197268 kb
Host smart-5e8b2023-cd70-45cf-89c0-37951834c744
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534083380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1534083380
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1356403024
Short name T591
Test name
Test status
Simulation time 1493589331 ps
CPU time 6.42 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 198000 kb
Host smart-70c5456f-85bb-4849-a064-d611704d766a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356403024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1356403024
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1200809261
Short name T676
Test name
Test status
Simulation time 29680776 ps
CPU time 0.92 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 195608 kb
Host smart-d5a91e0c-6e84-4d1e-8ab1-66cab02872c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200809261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1200809261
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3804909328
Short name T297
Test name
Test status
Simulation time 69109638 ps
CPU time 1.12 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196268 kb
Host smart-4c0798ce-e190-4cb5-a0c6-c84bb81cc3fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804909328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3804909328
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2803439243
Short name T5
Test name
Test status
Simulation time 42318040377 ps
CPU time 224.49 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:44:55 PM PDT 24
Peak memory 198044 kb
Host smart-0960c1e3-e967-42cf-ab0d-3eab53e78160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803439243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2803439243
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4200485373
Short name T599
Test name
Test status
Simulation time 674838684852 ps
CPU time 1826.93 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 01:11:37 PM PDT 24
Peak memory 198220 kb
Host smart-3fbe3c88-3aec-4209-bb7e-9701f584cd15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4200485373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4200485373
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2492304481
Short name T530
Test name
Test status
Simulation time 39315849 ps
CPU time 0.55 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 193828 kb
Host smart-add37184-2133-4ea2-8266-d2ccbb0a6122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492304481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2492304481
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2126794611
Short name T419
Test name
Test status
Simulation time 35870706 ps
CPU time 0.8 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 196220 kb
Host smart-a6d557a3-6e86-4a9c-ac20-09a6b4d9dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126794611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2126794611
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.459065623
Short name T178
Test name
Test status
Simulation time 663010845 ps
CPU time 18.1 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:24 PM PDT 24
Peak memory 196320 kb
Host smart-1805dc45-38bf-4cfd-9090-c7d367b66a33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459065623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.459065623
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3640298517
Short name T457
Test name
Test status
Simulation time 20823290 ps
CPU time 0.71 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 194652 kb
Host smart-f4f9f748-db6e-4487-a2b0-3d1127d9d607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640298517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3640298517
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2817994322
Short name T547
Test name
Test status
Simulation time 94406669 ps
CPU time 1.45 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197060 kb
Host smart-0c49b290-4fff-4091-9f05-e6395ab4dd22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817994322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2817994322
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1597078554
Short name T709
Test name
Test status
Simulation time 235966397 ps
CPU time 1.81 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 197856 kb
Host smart-72cec93d-2668-4760-badf-d5c4447de9e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597078554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1597078554
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.486674837
Short name T467
Test name
Test status
Simulation time 196082521 ps
CPU time 1.51 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:58 PM PDT 24
Peak memory 196792 kb
Host smart-9689c2c0-83f6-4a42-a831-b1e4435bb6e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486674837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
486674837
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.334140521
Short name T220
Test name
Test status
Simulation time 211627429 ps
CPU time 1.13 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 196372 kb
Host smart-1e8e8713-7027-4a83-9330-d4d93ac20f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334140521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.334140521
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2383851691
Short name T683
Test name
Test status
Simulation time 39442705 ps
CPU time 0.69 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 194836 kb
Host smart-f2b64aa7-bfb7-485d-8ff4-32e15f31c778
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383851691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2383851691
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2443917952
Short name T450
Test name
Test status
Simulation time 314960161 ps
CPU time 3.23 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197908 kb
Host smart-da9e3da0-1484-45f8-936e-bc3e3c458e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443917952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2443917952
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3774405439
Short name T115
Test name
Test status
Simulation time 204658541 ps
CPU time 1.08 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195384 kb
Host smart-4e01fa7b-5c9d-422a-afd6-e59d803004f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774405439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3774405439
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4190538835
Short name T656
Test name
Test status
Simulation time 67278306 ps
CPU time 0.76 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 195156 kb
Host smart-1d985f67-0774-4c48-8aa0-a624aa958afe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190538835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4190538835
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2440191369
Short name T404
Test name
Test status
Simulation time 4619486071 ps
CPU time 119.79 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:43:06 PM PDT 24
Peak memory 198060 kb
Host smart-f2c7fa39-72af-4807-b0f2-0cbd1300210c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440191369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2440191369
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2349959879
Short name T62
Test name
Test status
Simulation time 29502645637 ps
CPU time 817.4 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:54:35 PM PDT 24
Peak memory 198156 kb
Host smart-69caaa7b-ce8c-44ce-b747-9280b5190113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2349959879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2349959879
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.322610668
Short name T37
Test name
Test status
Simulation time 23456504 ps
CPU time 0.57 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 195500 kb
Host smart-c50650fd-1a90-415f-b68d-8c9340e168df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322610668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.322610668
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.220153649
Short name T533
Test name
Test status
Simulation time 34737318 ps
CPU time 0.66 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 193884 kb
Host smart-a5b4b877-c93b-46ff-b283-b1f83a11bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220153649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.220153649
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.4134522726
Short name T407
Test name
Test status
Simulation time 127313362 ps
CPU time 3.87 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:50 PM PDT 24
Peak memory 196080 kb
Host smart-abb70e13-bb44-42a9-8f16-dbf4433c83e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134522726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.4134522726
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2293514034
Short name T21
Test name
Test status
Simulation time 40894441 ps
CPU time 0.69 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 194496 kb
Host smart-4961c63b-f163-4c44-8d41-1cc1e7e5de48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293514034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2293514034
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4209927802
Short name T691
Test name
Test status
Simulation time 143504833 ps
CPU time 0.74 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 195452 kb
Host smart-55106046-9406-4b4a-a800-d5d1c7c242e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209927802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4209927802
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4740420
Short name T172
Test name
Test status
Simulation time 189705829 ps
CPU time 3.22 seconds
Started May 05 12:40:36 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 197960 kb
Host smart-719bc380-3590-42c7-9881-714087a20281
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4740420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_intr_with_filter_rand_intr_event.4740420
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1275311312
Short name T374
Test name
Test status
Simulation time 115278909 ps
CPU time 1.08 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 195624 kb
Host smart-96b15b1a-5aa8-4f3e-b7f5-d58dff4244fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275311312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1275311312
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.400014292
Short name T325
Test name
Test status
Simulation time 21803190 ps
CPU time 0.68 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 194272 kb
Host smart-00485cc5-cfb3-4609-9331-63ea102e8fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400014292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.400014292
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4165141058
Short name T337
Test name
Test status
Simulation time 38545584 ps
CPU time 0.89 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 195936 kb
Host smart-c2547113-075e-454a-9a41-70b959203b88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165141058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4165141058
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1396486907
Short name T360
Test name
Test status
Simulation time 517012230 ps
CPU time 3.11 seconds
Started May 05 12:40:28 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 197172 kb
Host smart-fc9b79c9-c768-46a5-96e0-3b441e19b4eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396486907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1396486907
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.877952053
Short name T46
Test name
Test status
Simulation time 214104775 ps
CPU time 0.74 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 213540 kb
Host smart-6967093d-f218-4b5b-a91a-f2e9dd54430a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877952053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.877952053
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1093828265
Short name T373
Test name
Test status
Simulation time 39032524 ps
CPU time 1.08 seconds
Started May 05 12:40:30 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 195416 kb
Host smart-5bd519dd-aec2-4191-9058-fead83d38241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093828265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1093828265
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.666634808
Short name T692
Test name
Test status
Simulation time 113110357 ps
CPU time 1.17 seconds
Started May 05 12:40:32 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 196268 kb
Host smart-07a6cefb-6725-4e3f-86ea-6f1f9fff9371
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666634808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.666634808
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3739685385
Short name T559
Test name
Test status
Simulation time 26721766792 ps
CPU time 109.59 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:41:59 PM PDT 24
Peak memory 197960 kb
Host smart-c5cd570e-8a2d-444b-828c-fabf6ffe1f19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739685385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3739685385
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1231234856
Short name T24
Test name
Test status
Simulation time 26364765 ps
CPU time 0.56 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 193788 kb
Host smart-7ee87725-9c63-4d64-85a6-80f23708d5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231234856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1231234856
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.645946826
Short name T154
Test name
Test status
Simulation time 45165066 ps
CPU time 0.88 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 196368 kb
Host smart-ab9ee727-0be4-4ab6-9b4f-fbb74df7af31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645946826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.645946826
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2560235572
Short name T652
Test name
Test status
Simulation time 173774289 ps
CPU time 2.94 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 196392 kb
Host smart-1e3990a7-03f3-43b3-86bc-f215b0f8cfb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560235572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2560235572
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2225376912
Short name T594
Test name
Test status
Simulation time 84211413 ps
CPU time 0.6 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 195212 kb
Host smart-17ae90d9-bc24-4fdf-a08e-6381c05c88d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225376912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2225376912
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1589256895
Short name T582
Test name
Test status
Simulation time 33982875 ps
CPU time 0.99 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 195960 kb
Host smart-b79c6036-66f9-420d-a0d4-5cfbd685c47d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589256895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1589256895
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4050480901
Short name T553
Test name
Test status
Simulation time 100279330 ps
CPU time 1.19 seconds
Started May 05 12:41:17 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 196156 kb
Host smart-40dce04a-59cc-4c19-a7f4-97f10d1073be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050480901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4050480901
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1684227280
Short name T107
Test name
Test status
Simulation time 123706189 ps
CPU time 2.87 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 196968 kb
Host smart-c4d57b2d-2c71-4777-bc70-93c341751f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684227280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1684227280
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.481764951
Short name T640
Test name
Test status
Simulation time 30582890 ps
CPU time 1.11 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 198024 kb
Host smart-7860fa2f-2da1-4372-9682-77d94e300f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481764951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.481764951
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1245302971
Short name T314
Test name
Test status
Simulation time 417017609 ps
CPU time 1.11 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196060 kb
Host smart-0f45208c-f00c-41b0-8a97-b491d4bffcb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245302971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1245302971
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1086662624
Short name T658
Test name
Test status
Simulation time 394946619 ps
CPU time 4.38 seconds
Started May 05 12:41:12 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 197936 kb
Host smart-2e1eb4fe-6ac4-4d7d-81af-f79deb259d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086662624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1086662624
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2009898595
Short name T141
Test name
Test status
Simulation time 82915364 ps
CPU time 1.15 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 196164 kb
Host smart-f8f7154e-ccd8-4f1a-9adf-8f056a61ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009898595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2009898595
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.333956083
Short name T194
Test name
Test status
Simulation time 86263136 ps
CPU time 0.94 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 196452 kb
Host smart-0e3c6778-dadb-4074-8678-f0c366346e04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333956083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.333956083
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2222710666
Short name T195
Test name
Test status
Simulation time 12967182783 ps
CPU time 171.31 seconds
Started May 05 12:41:26 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 198140 kb
Host smart-55255096-a1c4-453c-90d2-bd958f8e1cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222710666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2222710666
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.953969895
Short name T58
Test name
Test status
Simulation time 86051873612 ps
CPU time 786.68 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:54:43 PM PDT 24
Peak memory 198168 kb
Host smart-9c422a04-f3cd-4194-a23e-f73fa65c742a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=953969895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.953969895
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2791269316
Short name T447
Test name
Test status
Simulation time 57082795 ps
CPU time 0.53 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 193852 kb
Host smart-232505cf-ae0c-4d00-a3fc-4c039f73e1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791269316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2791269316
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3073516324
Short name T376
Test name
Test status
Simulation time 88200358 ps
CPU time 0.91 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:02 PM PDT 24
Peak memory 196932 kb
Host smart-0d120789-bf4b-4c6a-b7b7-de13803785c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073516324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3073516324
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4271948253
Short name T202
Test name
Test status
Simulation time 738705079 ps
CPU time 15.14 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 195428 kb
Host smart-babcb1dc-98bf-460e-8a50-abbb89f6d8ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271948253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4271948253
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1671988190
Short name T621
Test name
Test status
Simulation time 299744865 ps
CPU time 1.03 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 197748 kb
Host smart-8fd2b421-c66a-4c07-9a76-2a084a4a0872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671988190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1671988190
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2592746293
Short name T171
Test name
Test status
Simulation time 82984506 ps
CPU time 1.22 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 195680 kb
Host smart-cb912327-f381-44e7-80c6-d6bcdd081560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592746293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2592746293
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3036919893
Short name T456
Test name
Test status
Simulation time 165096141 ps
CPU time 3.07 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 198028 kb
Host smart-9515db63-e04c-4411-a8fe-b3034b610525
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036919893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3036919893
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1571674330
Short name T247
Test name
Test status
Simulation time 204580694 ps
CPU time 1.28 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:41:25 PM PDT 24
Peak memory 196772 kb
Host smart-72b73669-31bf-4c12-bc88-a4b0044740d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571674330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1571674330
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1100717476
Short name T239
Test name
Test status
Simulation time 268953925 ps
CPU time 0.8 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 197192 kb
Host smart-86f7b0d7-7dd2-40c2-8f08-de4d253caf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100717476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1100717476
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2226397945
Short name T590
Test name
Test status
Simulation time 104064886 ps
CPU time 1.19 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196964 kb
Host smart-431e6291-0442-47cd-aae8-81a82f636643
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226397945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2226397945
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2813040868
Short name T655
Test name
Test status
Simulation time 147321123 ps
CPU time 3.45 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197940 kb
Host smart-b690cfce-8630-4bbd-be5d-a6db228b12bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813040868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2813040868
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.455685952
Short name T631
Test name
Test status
Simulation time 244011015 ps
CPU time 1.13 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 195792 kb
Host smart-af393cc8-c878-4e40-a780-39982932e853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455685952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.455685952
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.704854972
Short name T150
Test name
Test status
Simulation time 26489188 ps
CPU time 0.83 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 196352 kb
Host smart-ac4df01c-0729-46ee-aaf7-712d28a13bc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704854972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.704854972
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1788418740
Short name T673
Test name
Test status
Simulation time 7565485587 ps
CPU time 102.78 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 198036 kb
Host smart-b6c8f11c-ab5a-4397-95a1-0c76a08e9428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788418740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1788418740
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2345939515
Short name T604
Test name
Test status
Simulation time 242939372046 ps
CPU time 1129.07 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:59:59 PM PDT 24
Peak memory 198156 kb
Host smart-c7f41837-aab7-4208-b8e2-71dd365eaadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2345939515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2345939515
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1446011614
Short name T173
Test name
Test status
Simulation time 11768067 ps
CPU time 0.56 seconds
Started May 05 12:40:59 PM PDT 24
Finished May 05 12:41:01 PM PDT 24
Peak memory 193816 kb
Host smart-2088db5e-dde9-4981-8de5-13b14ce55358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446011614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1446011614
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2105475004
Short name T125
Test name
Test status
Simulation time 48635848 ps
CPU time 0.89 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:41:17 PM PDT 24
Peak memory 195864 kb
Host smart-c9ce8d48-1019-44a3-9920-437b4943f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105475004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2105475004
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2328910747
Short name T598
Test name
Test status
Simulation time 971206885 ps
CPU time 8.73 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 197804 kb
Host smart-0df6c54f-3640-45af-927f-9753b6a055eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328910747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2328910747
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1260084305
Short name T472
Test name
Test status
Simulation time 336134863 ps
CPU time 1.03 seconds
Started May 05 12:41:25 PM PDT 24
Finished May 05 12:41:27 PM PDT 24
Peak memory 197792 kb
Host smart-a51bb3f4-59b6-4df7-95ae-8f914a237b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260084305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1260084305
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2795559693
Short name T563
Test name
Test status
Simulation time 121325664 ps
CPU time 1.18 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196728 kb
Host smart-e46f090b-d239-4e91-9e89-46a5eaf30af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795559693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2795559693
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.4165478301
Short name T258
Test name
Test status
Simulation time 116022910 ps
CPU time 1.46 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 198048 kb
Host smart-f9029dab-0b03-42f4-bdbb-e580f77c4ba2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165478301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.4165478301
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.469135676
Short name T137
Test name
Test status
Simulation time 91736918 ps
CPU time 1.03 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 196312 kb
Host smart-3a40ce25-8cb8-4f4d-a5d4-18f81f182cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469135676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
469135676
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3691299814
Short name T214
Test name
Test status
Simulation time 21575993 ps
CPU time 0.64 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 194152 kb
Host smart-e096d677-6a8c-40ed-a5eb-bff773582b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691299814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3691299814
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3667865456
Short name T627
Test name
Test status
Simulation time 80646112 ps
CPU time 0.87 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196376 kb
Host smart-d714eb1b-ac38-4e83-b256-46b3a6c90a78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667865456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3667865456
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3201881227
Short name T643
Test name
Test status
Simulation time 632231281 ps
CPU time 5.15 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 197892 kb
Host smart-8f2c83dc-b192-44b2-8d69-7a4dec03a5a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201881227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3201881227
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3364203780
Short name T479
Test name
Test status
Simulation time 392142503 ps
CPU time 1.27 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:41:24 PM PDT 24
Peak memory 196664 kb
Host smart-151b30da-657d-44f3-8ffa-2cb071253543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364203780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3364203780
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1970788224
Short name T405
Test name
Test status
Simulation time 247890966 ps
CPU time 1.08 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195364 kb
Host smart-78b890e0-c2aa-4d0c-b8a7-d3a582f68e40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970788224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1970788224
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.727564594
Short name T609
Test name
Test status
Simulation time 11750927057 ps
CPU time 63.09 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:42:12 PM PDT 24
Peak memory 198136 kb
Host smart-554b86e2-b0d6-4bb0-8e8b-4214c066e125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727564594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.727564594
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3286172524
Short name T162
Test name
Test status
Simulation time 65978030 ps
CPU time 0.57 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 194728 kb
Host smart-fb032629-8910-4684-8914-b10d681b9cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286172524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3286172524
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1374507982
Short name T661
Test name
Test status
Simulation time 20286218 ps
CPU time 0.62 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 194012 kb
Host smart-f834fab1-46fe-4ec5-99a6-6ebc0f552d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374507982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1374507982
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1215108301
Short name T664
Test name
Test status
Simulation time 641031604 ps
CPU time 8.82 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 196880 kb
Host smart-880e03d1-c3de-42f4-9073-6a8efb6c7464
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215108301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1215108301
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.4216846338
Short name T513
Test name
Test status
Simulation time 99179255 ps
CPU time 0.77 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196460 kb
Host smart-e5cb104a-e5d0-4697-82b8-79152c508da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216846338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.4216846338
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3601700807
Short name T482
Test name
Test status
Simulation time 70010445 ps
CPU time 1.13 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196688 kb
Host smart-7054c443-063e-448f-8dc9-079eb5d8eafe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601700807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3601700807
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1711629315
Short name T130
Test name
Test status
Simulation time 161617977 ps
CPU time 1.72 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:05 PM PDT 24
Peak memory 197008 kb
Host smart-b41b6a12-c354-46d9-bfbb-a2dff5b7c59d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711629315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1711629315
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3916384065
Short name T140
Test name
Test status
Simulation time 56080727 ps
CPU time 1.45 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:41:17 PM PDT 24
Peak memory 195812 kb
Host smart-202df16f-8f03-4ab6-a8c0-4c6a4c0a9b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916384065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3916384065
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1239213249
Short name T183
Test name
Test status
Simulation time 71562176 ps
CPU time 0.93 seconds
Started May 05 12:41:29 PM PDT 24
Finished May 05 12:41:30 PM PDT 24
Peak memory 195960 kb
Host smart-b7c40856-fdb0-4e34-8a69-46115071b641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239213249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1239213249
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3007856007
Short name T249
Test name
Test status
Simulation time 105042523 ps
CPU time 1.26 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196476 kb
Host smart-35b84741-ae48-4081-a3bf-460f153c56ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007856007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3007856007
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3796788079
Short name T593
Test name
Test status
Simulation time 294209124 ps
CPU time 4.86 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 197904 kb
Host smart-981845ba-ee2e-49bc-a49e-de47cf64167e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796788079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3796788079
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3813490138
Short name T349
Test name
Test status
Simulation time 139477426 ps
CPU time 0.82 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196352 kb
Host smart-7494c44a-43ca-46ff-8f05-299160fe2ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813490138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3813490138
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3242096714
Short name T717
Test name
Test status
Simulation time 308135019 ps
CPU time 0.93 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196332 kb
Host smart-5d7d7fc9-f8ca-4f40-bf26-b3395b15421a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242096714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3242096714
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3174930327
Short name T8
Test name
Test status
Simulation time 58361053718 ps
CPU time 180.81 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 198128 kb
Host smart-01003ac7-eda5-469a-b322-93a50f0bb888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174930327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3174930327
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2352925119
Short name T639
Test name
Test status
Simulation time 21050765 ps
CPU time 0.56 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 192728 kb
Host smart-73e96306-ec13-406f-84b6-736b7137acd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352925119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2352925119
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.166563495
Short name T66
Test name
Test status
Simulation time 75933636 ps
CPU time 0.68 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 194180 kb
Host smart-0a127437-982c-4fb9-8364-28c67ad2ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166563495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.166563495
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3381617609
Short name T713
Test name
Test status
Simulation time 3530498740 ps
CPU time 27.01 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:30 PM PDT 24
Peak memory 198092 kb
Host smart-294a9ab7-f5b0-40d6-a48a-a69e1712b3bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381617609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3381617609
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1919078222
Short name T678
Test name
Test status
Simulation time 30626773 ps
CPU time 0.71 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 194520 kb
Host smart-15a3b4e3-a2c7-4915-9126-9ebb896d2da2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919078222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1919078222
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1358873785
Short name T441
Test name
Test status
Simulation time 29316261 ps
CPU time 0.79 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 194324 kb
Host smart-7632ba18-6502-40da-b55c-ca0167a8b597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358873785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1358873785
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4094416220
Short name T462
Test name
Test status
Simulation time 192417431 ps
CPU time 1.65 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:05 PM PDT 24
Peak memory 195916 kb
Host smart-8e4dc47a-1906-4f81-b1b5-c89f9facc5f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094416220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4094416220
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2184106653
Short name T318
Test name
Test status
Simulation time 125850918 ps
CPU time 1.16 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196536 kb
Host smart-713e5352-aa22-4b69-9883-bc0c750f1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184106653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2184106653
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3033338713
Short name T561
Test name
Test status
Simulation time 35313961 ps
CPU time 0.89 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 195772 kb
Host smart-b80b6436-cb1e-4613-b4f6-58ace2cdf71b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033338713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3033338713
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3331914449
Short name T245
Test name
Test status
Simulation time 429676852 ps
CPU time 1.56 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 197948 kb
Host smart-187968b5-b1b5-4026-bbb9-16b285cb7010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331914449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3331914449
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.462230958
Short name T396
Test name
Test status
Simulation time 419903800 ps
CPU time 0.88 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 196352 kb
Host smart-415d5d31-ab16-4981-a473-7fd142eb484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462230958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.462230958
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.668118125
Short name T527
Test name
Test status
Simulation time 92906744 ps
CPU time 1.18 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 196400 kb
Host smart-60c94a9e-f550-4463-9828-84c6b55b9cf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668118125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.668118125
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3839148323
Short name T682
Test name
Test status
Simulation time 85476582242 ps
CPU time 210.2 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 198032 kb
Host smart-b44dbe75-ed43-43e4-bdff-4bb6010e44f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839148323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3839148323
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1951404583
Short name T271
Test name
Test status
Simulation time 26568324 ps
CPU time 0.57 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:41:20 PM PDT 24
Peak memory 194024 kb
Host smart-e8007525-0fc9-49c0-961f-dfb51b05f611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951404583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1951404583
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2921962854
Short name T54
Test name
Test status
Simulation time 37578183 ps
CPU time 0.86 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196524 kb
Host smart-6f84f5bc-2efb-4e06-999e-710a165b2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921962854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2921962854
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.688836467
Short name T387
Test name
Test status
Simulation time 227484495 ps
CPU time 10.44 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:59 PM PDT 24
Peak memory 196756 kb
Host smart-92f0d900-820e-4950-8194-adc85b749e87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688836467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.688836467
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3175342701
Short name T562
Test name
Test status
Simulation time 29822614 ps
CPU time 0.79 seconds
Started May 05 12:41:16 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 194752 kb
Host smart-366bd8ee-e6c1-4719-9124-fba16585db10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175342701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3175342701
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3024536480
Short name T206
Test name
Test status
Simulation time 78478380 ps
CPU time 0.65 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 195052 kb
Host smart-0d43218f-cd2a-49b5-9a99-3a8727bfb81f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024536480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3024536480
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2561974975
Short name T520
Test name
Test status
Simulation time 107759985 ps
CPU time 1.8 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197696 kb
Host smart-f55ab2a1-21fc-4c27-baeb-c7c1e2119f0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561974975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2561974975
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3060579356
Short name T152
Test name
Test status
Simulation time 73358966 ps
CPU time 1.92 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 196908 kb
Host smart-49748cd0-8cfe-4ff9-b271-b17f40d0294b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060579356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3060579356
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1636074586
Short name T359
Test name
Test status
Simulation time 327463618 ps
CPU time 0.75 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196180 kb
Host smart-77728918-03aa-46a0-b4ef-89f72dcf1bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636074586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1636074586
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1789060816
Short name T636
Test name
Test status
Simulation time 20468922 ps
CPU time 0.67 seconds
Started May 05 12:41:33 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 194320 kb
Host smart-8513e047-5208-494b-8c8e-e32b94d2afee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789060816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1789060816
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1645180967
Short name T211
Test name
Test status
Simulation time 179824808 ps
CPU time 1.62 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197876 kb
Host smart-c8c954a3-d42c-4394-a43f-9f1f5fe1f5f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645180967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1645180967
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.174986986
Short name T554
Test name
Test status
Simulation time 54958553 ps
CPU time 1.01 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195712 kb
Host smart-3776796c-d530-43f0-99b0-11db03d401dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174986986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.174986986
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2309344589
Short name T611
Test name
Test status
Simulation time 452169550 ps
CPU time 1.11 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 195736 kb
Host smart-30fe6a14-326c-4626-b991-62362851e112
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309344589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2309344589
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1721470012
Short name T708
Test name
Test status
Simulation time 8649785080 ps
CPU time 46.32 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 197776 kb
Host smart-ca9c167c-34ce-4569-9896-ea033e488a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721470012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1721470012
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1787127550
Short name T324
Test name
Test status
Simulation time 50007787 ps
CPU time 0.56 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 194624 kb
Host smart-50bd3951-d8d6-497c-851a-04577c124879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787127550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1787127550
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.207117672
Short name T575
Test name
Test status
Simulation time 378125053 ps
CPU time 0.8 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 195256 kb
Host smart-36fd79c2-edd1-4160-a9f2-326493c47ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207117672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.207117672
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1384049314
Short name T539
Test name
Test status
Simulation time 1139602282 ps
CPU time 16.48 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196660 kb
Host smart-7f2bcc8a-88b1-4652-bafb-a7fa7987efaa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384049314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1384049314
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1298539155
Short name T585
Test name
Test status
Simulation time 85245249 ps
CPU time 0.99 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 196380 kb
Host smart-9ecec598-b7e8-4ecd-baff-20359637077a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298539155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1298539155
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2083812311
Short name T290
Test name
Test status
Simulation time 52199891 ps
CPU time 1.36 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 197116 kb
Host smart-099eb06d-508f-4117-a78a-8fff6f8dfef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083812311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2083812311
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.319084958
Short name T170
Test name
Test status
Simulation time 73861235 ps
CPU time 1.36 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 196600 kb
Host smart-082a3ffd-0dbc-4e9c-a8fd-223218f1d27d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319084958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.319084958
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3283916804
Short name T649
Test name
Test status
Simulation time 67031222 ps
CPU time 1.95 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196936 kb
Host smart-a5f47b8e-1de1-49a1-8421-526c2fdcd21b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283916804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3283916804
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1448807025
Short name T453
Test name
Test status
Simulation time 30314007 ps
CPU time 0.78 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:03 PM PDT 24
Peak memory 196192 kb
Host smart-a190c0af-82d8-4258-b190-a429c59a24de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448807025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1448807025
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1232990404
Short name T312
Test name
Test status
Simulation time 77854636 ps
CPU time 0.93 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 195648 kb
Host smart-9eea3b00-df0b-4d93-821e-0a1c2dea2e82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232990404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1232990404
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2461178534
Short name T339
Test name
Test status
Simulation time 61987688 ps
CPU time 2.92 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 197912 kb
Host smart-83179477-24cf-411c-9d05-cc693aeaa319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461178534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2461178534
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.545782430
Short name T703
Test name
Test status
Simulation time 79712665 ps
CPU time 1.37 seconds
Started May 05 12:41:08 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 195492 kb
Host smart-e6fffc85-24f1-40dc-9693-f61ffc49ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545782430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.545782430
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1199609073
Short name T136
Test name
Test status
Simulation time 149816276 ps
CPU time 1.21 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 196584 kb
Host smart-1e3bf756-3ea4-446b-ac46-bd934837084c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199609073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1199609073
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.556240699
Short name T187
Test name
Test status
Simulation time 3242598156 ps
CPU time 50.57 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:42:04 PM PDT 24
Peak memory 198068 kb
Host smart-819dc0b5-eedf-4534-ab26-6c4ab5cd7cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556240699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.556240699
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.271580443
Short name T251
Test name
Test status
Simulation time 14163973 ps
CPU time 0.58 seconds
Started May 05 12:41:08 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 193872 kb
Host smart-4a5f3716-1e79-4029-a902-f922aa0c7415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271580443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.271580443
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2102835667
Short name T234
Test name
Test status
Simulation time 39587365 ps
CPU time 0.65 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 194032 kb
Host smart-ba830903-87d3-44c0-bab9-8e083f41e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102835667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2102835667
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1511913154
Short name T502
Test name
Test status
Simulation time 1662063439 ps
CPU time 7.97 seconds
Started May 05 12:41:12 PM PDT 24
Finished May 05 12:41:22 PM PDT 24
Peak memory 196928 kb
Host smart-5b5c08d7-33fa-462e-afa5-318908dc618a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511913154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1511913154
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.4120262090
Short name T286
Test name
Test status
Simulation time 723226646 ps
CPU time 0.92 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197164 kb
Host smart-b7567ef8-8d88-4bfb-ab0b-8cda5ce873c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120262090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.4120262090
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.878942376
Short name T506
Test name
Test status
Simulation time 57679949 ps
CPU time 1.07 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 196020 kb
Host smart-ba05ec81-6aa6-4c37-877c-5c044e305c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878942376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.878942376
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2259780123
Short name T706
Test name
Test status
Simulation time 85740064 ps
CPU time 1.88 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 196428 kb
Host smart-41392102-415c-409f-adff-a643edb17802
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259780123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2259780123
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4089579150
Short name T138
Test name
Test status
Simulation time 88753081 ps
CPU time 1.48 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 196100 kb
Host smart-607e89ac-a406-4c53-b75c-8e4bbb3b8287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089579150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4089579150
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3917586164
Short name T402
Test name
Test status
Simulation time 155046231 ps
CPU time 1.28 seconds
Started May 05 12:41:26 PM PDT 24
Finished May 05 12:41:27 PM PDT 24
Peak memory 197940 kb
Host smart-0ed5a201-63b0-48ed-bace-54ba72489ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917586164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3917586164
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.744820890
Short name T363
Test name
Test status
Simulation time 56919954 ps
CPU time 0.64 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 194952 kb
Host smart-cade9fd5-04dc-41bc-b323-14726ede2887
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744820890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.744820890
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1601843413
Short name T638
Test name
Test status
Simulation time 1634184242 ps
CPU time 4.71 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 197932 kb
Host smart-ef20b436-3045-445f-9ab1-e0e2c5776716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601843413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1601843413
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.246892269
Short name T445
Test name
Test status
Simulation time 219730868 ps
CPU time 1.09 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196084 kb
Host smart-b78b67d6-4b86-4643-913a-2e2e4d276858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246892269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.246892269
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.665111001
Short name T153
Test name
Test status
Simulation time 125407604 ps
CPU time 0.75 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 195184 kb
Host smart-235aac31-4a5c-4e24-bee4-74e20e54ebff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665111001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.665111001
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4169811308
Short name T680
Test name
Test status
Simulation time 3263422341 ps
CPU time 43.8 seconds
Started May 05 12:41:16 PM PDT 24
Finished May 05 12:42:01 PM PDT 24
Peak memory 198136 kb
Host smart-f6a482b4-170a-4c09-855e-d05da9c16728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169811308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4169811308
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3943689503
Short name T61
Test name
Test status
Simulation time 109693482409 ps
CPU time 1039.84 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:59:07 PM PDT 24
Peak memory 198084 kb
Host smart-2f2c62be-8638-4700-bece-6b7d4b9c62b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3943689503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3943689503
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.922830953
Short name T646
Test name
Test status
Simulation time 48081418 ps
CPU time 0.56 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 193824 kb
Host smart-6b41c5ee-e3f8-42f9-a1ce-7c749fc65b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922830953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.922830953
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1205753349
Short name T283
Test name
Test status
Simulation time 85974590 ps
CPU time 0.69 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 194976 kb
Host smart-43de2f61-a05f-488e-b104-22eca91624e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205753349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1205753349
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2026267922
Short name T366
Test name
Test status
Simulation time 227682503 ps
CPU time 11.16 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 196676 kb
Host smart-0c74c192-b729-44b0-9c71-527dfed4e8a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026267922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2026267922
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3840757857
Short name T381
Test name
Test status
Simulation time 61402918 ps
CPU time 0.87 seconds
Started May 05 12:41:35 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196552 kb
Host smart-b744866e-fe63-432b-af72-bbe22b3458fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840757857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3840757857
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1314510151
Short name T578
Test name
Test status
Simulation time 196286540 ps
CPU time 0.92 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 195680 kb
Host smart-0db95dd6-d1de-4cf0-b206-8dee9c3ed595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314510151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1314510151
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1057106470
Short name T144
Test name
Test status
Simulation time 41365898 ps
CPU time 1.6 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 197064 kb
Host smart-392d9c25-d96d-4777-a924-0d93cefbc70d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057106470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1057106470
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1161994316
Short name T486
Test name
Test status
Simulation time 70436824 ps
CPU time 0.94 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 195508 kb
Host smart-95adeecc-593b-4420-a3e6-cd780f22f96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161994316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1161994316
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3011176871
Short name T302
Test name
Test status
Simulation time 101014667 ps
CPU time 1.15 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196596 kb
Host smart-3767db4a-9abe-46de-a8d1-02f947827806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011176871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3011176871
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1176990632
Short name T690
Test name
Test status
Simulation time 261338593 ps
CPU time 1.43 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 196728 kb
Host smart-7bf14dca-60fc-4929-9305-a57092a243fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176990632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1176990632
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1300571345
Short name T515
Test name
Test status
Simulation time 383860734 ps
CPU time 1.94 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:42 PM PDT 24
Peak memory 197888 kb
Host smart-bc36bd27-cc52-4a06-b2b5-baa9cdf331d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300571345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1300571345
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1523976831
Short name T416
Test name
Test status
Simulation time 182217054 ps
CPU time 0.95 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 196112 kb
Host smart-005a6bc4-cd01-4c58-a847-d9de93207384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523976831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1523976831
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2539302947
Short name T512
Test name
Test status
Simulation time 74921837 ps
CPU time 1.27 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 196796 kb
Host smart-17d6de7a-ea9d-4f26-baa9-c92bed0904b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539302947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2539302947
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.313569188
Short name T20
Test name
Test status
Simulation time 22154942493 ps
CPU time 63.75 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:42:15 PM PDT 24
Peak memory 198112 kb
Host smart-c9b667d7-4e3b-4f73-a709-8619eba7ecee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313569188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.313569188
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3963250632
Short name T57
Test name
Test status
Simulation time 81273251685 ps
CPU time 896.52 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:56:05 PM PDT 24
Peak memory 198148 kb
Host smart-16189508-7626-49e6-8536-38fe3216c779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3963250632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3963250632
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1971798057
Short name T108
Test name
Test status
Simulation time 14624944 ps
CPU time 0.59 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:41 PM PDT 24
Peak memory 194020 kb
Host smart-ce7b6b8a-a040-4360-bb07-0013885635da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971798057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1971798057
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1020785985
Short name T320
Test name
Test status
Simulation time 101841576 ps
CPU time 0.86 seconds
Started May 05 12:41:17 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 197284 kb
Host smart-c91a20d1-cd01-4aea-aa14-7b8232c3a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020785985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1020785985
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3523898780
Short name T291
Test name
Test status
Simulation time 976115321 ps
CPU time 26.1 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:41 PM PDT 24
Peak memory 196656 kb
Host smart-6a5f3d75-4f62-44ee-8fa7-80b6aa64e2e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523898780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3523898780
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.694104539
Short name T328
Test name
Test status
Simulation time 30021242 ps
CPU time 0.64 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 195280 kb
Host smart-a4744f26-f5f3-487f-862c-735ec9a7f7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694104539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.694104539
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.122620093
Short name T204
Test name
Test status
Simulation time 45558113 ps
CPU time 0.9 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:42 PM PDT 24
Peak memory 197440 kb
Host smart-063b9723-bddc-4eb6-ad70-b17846d99279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122620093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.122620093
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.879060849
Short name T244
Test name
Test status
Simulation time 226766571 ps
CPU time 2.18 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:41:23 PM PDT 24
Peak memory 197948 kb
Host smart-8d561806-40dd-4761-82cd-31a287104292
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879060849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.879060849
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2959436549
Short name T179
Test name
Test status
Simulation time 73901662 ps
CPU time 0.96 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 196220 kb
Host smart-d016923a-4ce8-4fd4-b3c2-d3945c5a7a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959436549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2959436549
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.346046489
Short name T145
Test name
Test status
Simulation time 42862853 ps
CPU time 0.99 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 195712 kb
Host smart-fa7f9acd-89ca-42d0-a869-fd37245e7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346046489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.346046489
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4131569511
Short name T438
Test name
Test status
Simulation time 24136895 ps
CPU time 0.73 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:44 PM PDT 24
Peak memory 195940 kb
Host smart-a5387fb8-994d-445a-9e79-0b95a372d74b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131569511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4131569511
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.73531931
Short name T236
Test name
Test status
Simulation time 431844374 ps
CPU time 3.75 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197860 kb
Host smart-10878cf8-00d8-4a5d-8729-d81da8ae72b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73531931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand
om_long_reg_writes_reg_reads.73531931
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1367282087
Short name T19
Test name
Test status
Simulation time 100947039 ps
CPU time 0.99 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 195420 kb
Host smart-6fca9522-eb66-44ff-9234-11e3c1791341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367282087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1367282087
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.714681235
Short name T543
Test name
Test status
Simulation time 34718820 ps
CPU time 0.76 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 195180 kb
Host smart-361bc8b4-258a-4ea1-8477-fefd83972300
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714681235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.714681235
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3524998927
Short name T69
Test name
Test status
Simulation time 3135319937 ps
CPU time 45.26 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 198148 kb
Host smart-e3907c4c-e478-4d80-9858-de626dd86d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524998927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3524998927
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3265035214
Short name T540
Test name
Test status
Simulation time 425742142862 ps
CPU time 1478.98 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 01:05:54 PM PDT 24
Peak memory 206424 kb
Host smart-ef7f68b0-498e-4dbe-b06c-718a20114642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3265035214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3265035214
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.282736886
Short name T551
Test name
Test status
Simulation time 25353303 ps
CPU time 0.58 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 194484 kb
Host smart-81fa6574-d3a4-4b8d-b109-07f891f6b4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282736886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.282736886
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1837170302
Short name T287
Test name
Test status
Simulation time 17807651 ps
CPU time 0.6 seconds
Started May 05 12:40:23 PM PDT 24
Finished May 05 12:40:29 PM PDT 24
Peak memory 194536 kb
Host smart-ce5ec816-9e07-4884-8d1f-9777b8540c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837170302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1837170302
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1312611846
Short name T468
Test name
Test status
Simulation time 248234026 ps
CPU time 3.29 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:25 PM PDT 24
Peak memory 195888 kb
Host smart-b4bd4b48-d338-4806-b903-9fd0ae97e7c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312611846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1312611846
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.41167726
Short name T7
Test name
Test status
Simulation time 70437041 ps
CPU time 0.86 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196788 kb
Host smart-ae2fd2db-6327-4680-95b8-8e6d19e1a351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41167726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.41167726
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.128004282
Short name T429
Test name
Test status
Simulation time 44882062 ps
CPU time 0.93 seconds
Started May 05 12:40:23 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 195952 kb
Host smart-5c456ca8-b6f4-4ce1-ba4c-caddd504a638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128004282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.128004282
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1692612692
Short name T623
Test name
Test status
Simulation time 78005597 ps
CPU time 2.15 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 196344 kb
Host smart-5c05cfcd-3e65-4e41-b684-2edff24fd2b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692612692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1692612692
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3492890043
Short name T230
Test name
Test status
Simulation time 107139344 ps
CPU time 1.32 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 196744 kb
Host smart-4b4955e2-c53c-4c7c-96f0-d2c3f643f5e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492890043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3492890043
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.691333050
Short name T27
Test name
Test status
Simulation time 32384940 ps
CPU time 1.14 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 196504 kb
Host smart-86340447-1965-4184-a015-4dd81eb3a41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691333050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.691333050
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.795530540
Short name T440
Test name
Test status
Simulation time 110279776 ps
CPU time 1.08 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 196484 kb
Host smart-c3a7af90-f477-40bc-b510-a5dd9bedbddf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795530540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.795530540
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.977647297
Short name T569
Test name
Test status
Simulation time 666275976 ps
CPU time 3.25 seconds
Started May 05 12:40:28 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 197844 kb
Host smart-b3652a83-05e9-4abf-a5e4-fb24ef1a7e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977647297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.977647297
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2905219264
Short name T36
Test name
Test status
Simulation time 195669626 ps
CPU time 0.84 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:22 PM PDT 24
Peak memory 213756 kb
Host smart-22327ab4-79eb-4078-9874-7117eb1a56a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905219264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2905219264
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2275105962
Short name T260
Test name
Test status
Simulation time 548611742 ps
CPU time 1.06 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 196496 kb
Host smart-640c06d6-e467-4131-8b94-517b261accf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275105962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2275105962
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1361916402
Short name T671
Test name
Test status
Simulation time 63239052 ps
CPU time 1.15 seconds
Started May 05 12:40:37 PM PDT 24
Finished May 05 12:40:39 PM PDT 24
Peak memory 195696 kb
Host smart-073661d7-691d-43b5-8f34-71ff6d623a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361916402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1361916402
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.91126881
Short name T699
Test name
Test status
Simulation time 21823181391 ps
CPU time 58.6 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 198020 kb
Host smart-a53a1b6a-fea9-43ec-97c3-f2a406695aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91126881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpi
o_stress_all.91126881
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.560416061
Short name T660
Test name
Test status
Simulation time 51939202723 ps
CPU time 836.04 seconds
Started May 05 12:40:31 PM PDT 24
Finished May 05 12:54:28 PM PDT 24
Peak memory 198164 kb
Host smart-d3e6362d-ad77-45b5-bdea-399601855d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=560416061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.560416061
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2977665061
Short name T522
Test name
Test status
Simulation time 14907432 ps
CPU time 0.57 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 193984 kb
Host smart-e335fa92-7595-49f7-b955-68cfdf22f111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977665061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2977665061
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3957467285
Short name T615
Test name
Test status
Simulation time 156030165 ps
CPU time 0.67 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 194160 kb
Host smart-4201387d-e741-4ef6-a05b-e9670cf4316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957467285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3957467285
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.773377899
Short name T209
Test name
Test status
Simulation time 2029260322 ps
CPU time 18.03 seconds
Started May 05 12:41:17 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 195428 kb
Host smart-60e29c46-48a5-4112-88cc-e49a3b031c54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773377899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.773377899
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1165992843
Short name T336
Test name
Test status
Simulation time 231325964 ps
CPU time 1.01 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:05 PM PDT 24
Peak memory 196912 kb
Host smart-b911549b-26e6-4ff4-8635-26ff5a260952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165992843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1165992843
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3223497105
Short name T550
Test name
Test status
Simulation time 323548606 ps
CPU time 1.4 seconds
Started May 05 12:41:34 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196424 kb
Host smart-f153e5ed-0ae0-4e41-a3ac-ad33955f7180
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223497105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3223497105
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1767657971
Short name T273
Test name
Test status
Simulation time 141781267 ps
CPU time 1.77 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 196404 kb
Host smart-9eb91fd6-f9c6-4912-84c7-c5bc5b5b2387
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767657971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1767657971
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2392321890
Short name T250
Test name
Test status
Simulation time 60937896 ps
CPU time 1.81 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 197324 kb
Host smart-9ff56a2a-6311-4d0d-a3b3-34635c048aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392321890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2392321890
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1640512988
Short name T516
Test name
Test status
Simulation time 117438074 ps
CPU time 1.16 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 196556 kb
Host smart-194b9d33-946b-4666-ac90-d10465e267fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640512988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1640512988
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3774020382
Short name T412
Test name
Test status
Simulation time 37974050 ps
CPU time 0.84 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 197140 kb
Host smart-f26ed3cc-dfd0-46f1-80cb-aa0d00db4ad6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774020382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3774020382
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4082985318
Short name T449
Test name
Test status
Simulation time 744879553 ps
CPU time 5.09 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:20 PM PDT 24
Peak memory 197736 kb
Host smart-c97ebf58-a1ac-4f83-979f-bab9060e0a26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082985318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4082985318
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3500950265
Short name T142
Test name
Test status
Simulation time 92719086 ps
CPU time 1.38 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 195428 kb
Host smart-cff36c81-3798-4fd9-acae-8f2fb55e2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500950265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3500950265
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4239654304
Short name T256
Test name
Test status
Simulation time 74976313 ps
CPU time 1.02 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 195604 kb
Host smart-735f4253-8cb9-43ae-8520-0db174b879fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239654304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4239654304
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1787867070
Short name T289
Test name
Test status
Simulation time 71924204105 ps
CPU time 143.24 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 198028 kb
Host smart-a7316d64-1b83-4c22-8126-cef630533cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787867070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1787867070
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2016308368
Short name T161
Test name
Test status
Simulation time 17575035 ps
CPU time 0.57 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 193992 kb
Host smart-815f6f08-a968-4ac6-b56e-249a974a7ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016308368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2016308368
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2814474301
Short name T192
Test name
Test status
Simulation time 46084024 ps
CPU time 0.79 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195472 kb
Host smart-44112832-e99e-40de-8cb9-9378bea23dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814474301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2814474301
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.436666896
Short name T354
Test name
Test status
Simulation time 330574424 ps
CPU time 8.67 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 196976 kb
Host smart-cc8d7fc1-356e-4a3c-bfea-84e43658ac1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436666896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.436666896
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2749099150
Short name T669
Test name
Test status
Simulation time 104328297 ps
CPU time 0.7 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 194724 kb
Host smart-94ba249f-f0fc-4360-aec5-e89a762b41a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749099150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2749099150
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1364976352
Short name T617
Test name
Test status
Simulation time 134107341 ps
CPU time 0.69 seconds
Started May 05 12:41:08 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 195048 kb
Host smart-8cf3ba5b-0df2-4f8d-a37d-6bef3257e98d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364976352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1364976352
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2572943673
Short name T493
Test name
Test status
Simulation time 68630571 ps
CPU time 2.68 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 198000 kb
Host smart-9b05bc25-f1ad-4cea-95e1-eb0138a50f3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572943673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2572943673
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3149976476
Short name T500
Test name
Test status
Simulation time 208001337 ps
CPU time 1.31 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:04 PM PDT 24
Peak memory 196048 kb
Host smart-71dadbdf-185e-45b2-bae1-74c71dea49df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149976476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3149976476
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2791344144
Short name T361
Test name
Test status
Simulation time 132906768 ps
CPU time 0.83 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 197108 kb
Host smart-acd6f312-4cf9-44ea-97f4-9c9a125a904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791344144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2791344144
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.613983532
Short name T165
Test name
Test status
Simulation time 31799673 ps
CPU time 0.9 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 195756 kb
Host smart-a98af5ea-a4fe-47ae-9f17-2ee052ac91f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613983532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.613983532
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.517279119
Short name T701
Test name
Test status
Simulation time 78837695 ps
CPU time 3.52 seconds
Started May 05 12:41:11 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 197840 kb
Host smart-3d25df26-2c79-42ca-a374-1ee1fea36190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517279119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.517279119
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3580134178
Short name T167
Test name
Test status
Simulation time 349814018 ps
CPU time 0.75 seconds
Started May 05 12:41:21 PM PDT 24
Finished May 05 12:41:22 PM PDT 24
Peak memory 195968 kb
Host smart-1454aab5-89a9-4ce4-ab8e-04da6f21b843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580134178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3580134178
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.858277240
Short name T454
Test name
Test status
Simulation time 71708297 ps
CPU time 1.05 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 195736 kb
Host smart-bb55d14e-e107-4574-928a-a2fd63c927cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858277240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.858277240
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3290615251
Short name T571
Test name
Test status
Simulation time 2198843972 ps
CPU time 56.57 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 197996 kb
Host smart-dcd49551-6558-47a4-a792-4aafb3134735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290615251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3290615251
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3148325664
Short name T25
Test name
Test status
Simulation time 34982364780 ps
CPU time 970.34 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:57:26 PM PDT 24
Peak memory 198176 kb
Host smart-18e0e5e4-d039-434d-a887-f79f34f77c8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3148325664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3148325664
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2692575921
Short name T375
Test name
Test status
Simulation time 23061037 ps
CPU time 0.56 seconds
Started May 05 12:41:31 PM PDT 24
Finished May 05 12:41:32 PM PDT 24
Peak memory 193852 kb
Host smart-d937713a-7c97-4287-8b69-19a59d648391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692575921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2692575921
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1181072019
Short name T364
Test name
Test status
Simulation time 168752828 ps
CPU time 0.81 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 195348 kb
Host smart-0a4be896-0dfa-43e8-a127-2988fefa8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181072019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1181072019
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3454277536
Short name T174
Test name
Test status
Simulation time 2786302882 ps
CPU time 23.83 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 196816 kb
Host smart-45f63d3f-f2f4-4ff7-b76b-931d08a83404
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454277536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3454277536
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1544240406
Short name T330
Test name
Test status
Simulation time 244773692 ps
CPU time 1.03 seconds
Started May 05 12:41:32 PM PDT 24
Finished May 05 12:41:33 PM PDT 24
Peak memory 197580 kb
Host smart-e1fa7108-8e59-4759-abd4-cde47d646d72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544240406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1544240406
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3677194783
Short name T600
Test name
Test status
Simulation time 36080498 ps
CPU time 0.75 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:41:20 PM PDT 24
Peak memory 195388 kb
Host smart-eb4924d8-a336-4b1f-835c-f30bc4074715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677194783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3677194783
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1001735775
Short name T601
Test name
Test status
Simulation time 96667182 ps
CPU time 3.69 seconds
Started May 05 12:41:35 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 196332 kb
Host smart-7bf18024-d5c0-4ff5-a891-94330b80c045
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001735775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1001735775
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2141932933
Short name T389
Test name
Test status
Simulation time 110972044 ps
CPU time 2.94 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:41:06 PM PDT 24
Peak memory 195760 kb
Host smart-f90d3eda-1035-41ae-a5b2-17ef0ca8d90e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141932933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2141932933
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2293593436
Short name T469
Test name
Test status
Simulation time 113603570 ps
CPU time 0.85 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196360 kb
Host smart-055b063e-bd6e-4e3e-a096-b945028871c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293593436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2293593436
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3214481180
Short name T662
Test name
Test status
Simulation time 57515843 ps
CPU time 1.27 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:41:17 PM PDT 24
Peak memory 196852 kb
Host smart-7eb02afc-4c4b-4717-bdd5-09cb5547e42c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214481180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3214481180
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1655659772
Short name T149
Test name
Test status
Simulation time 256158183 ps
CPU time 5.57 seconds
Started May 05 12:41:01 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 197828 kb
Host smart-e03b229a-ec8f-4386-8a32-74ae68d227a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655659772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1655659772
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2486698176
Short name T261
Test name
Test status
Simulation time 117142106 ps
CPU time 1.24 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 196648 kb
Host smart-b3874054-a5ce-462b-9c9d-b8f4369aebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486698176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2486698176
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.267439850
Short name T356
Test name
Test status
Simulation time 41831297 ps
CPU time 0.89 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 196216 kb
Host smart-82c17783-f880-4144-ac18-70d9999474f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267439850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.267439850
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1690766366
Short name T526
Test name
Test status
Simulation time 35564347554 ps
CPU time 171.31 seconds
Started May 05 12:41:02 PM PDT 24
Finished May 05 12:43:54 PM PDT 24
Peak memory 197960 kb
Host smart-a8f8684e-8086-4c71-98ab-20650bd1fdcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690766366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1690766366
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2347915039
Short name T68
Test name
Test status
Simulation time 30999417 ps
CPU time 0.59 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 194804 kb
Host smart-b18a8fac-d509-47b4-b77f-7bc8fab4a58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347915039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2347915039
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.99603844
Short name T311
Test name
Test status
Simulation time 60767277 ps
CPU time 0.79 seconds
Started May 05 12:41:22 PM PDT 24
Finished May 05 12:41:23 PM PDT 24
Peak memory 195236 kb
Host smart-4d17210f-720a-475b-8149-94bbe40a9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99603844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.99603844
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2431287342
Short name T542
Test name
Test status
Simulation time 15472768432 ps
CPU time 26.98 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196876 kb
Host smart-b6f269d6-4d19-473c-8b37-db7d8432b7a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431287342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2431287342
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.466266429
Short name T634
Test name
Test status
Simulation time 177030650 ps
CPU time 0.82 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 196336 kb
Host smart-2d98849e-ed4d-46f5-ba8e-facb447a1b22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466266429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.466266429
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.767436271
Short name T535
Test name
Test status
Simulation time 247886020 ps
CPU time 1.01 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 196068 kb
Host smart-9fbe2f5a-bd57-4c1e-8849-bf4bddbf4038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767436271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.767436271
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2522201165
Short name T573
Test name
Test status
Simulation time 265517135 ps
CPU time 0.93 seconds
Started May 05 12:41:22 PM PDT 24
Finished May 05 12:41:24 PM PDT 24
Peak memory 196164 kb
Host smart-74d35526-185a-43f2-bf50-67daddecf0a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522201165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2522201165
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1708474967
Short name T338
Test name
Test status
Simulation time 257208513 ps
CPU time 1.68 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 196016 kb
Host smart-8eaa1b66-ac93-4a6f-ba77-93008b196545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708474967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1708474967
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4224254467
Short name T622
Test name
Test status
Simulation time 67814185 ps
CPU time 1.02 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196368 kb
Host smart-1fa35287-b735-432c-b66d-9f6ac230bf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224254467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4224254467
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2592994677
Short name T545
Test name
Test status
Simulation time 94729693 ps
CPU time 0.77 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 196164 kb
Host smart-4884ebb3-6f43-477d-8e66-05aea47062e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592994677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2592994677
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1977827635
Short name T333
Test name
Test status
Simulation time 2092659448 ps
CPU time 6.26 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 197836 kb
Host smart-c078f395-5636-403f-880a-faea546e9474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977827635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1977827635
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4256625565
Short name T399
Test name
Test status
Simulation time 58197127 ps
CPU time 0.73 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195232 kb
Host smart-880392fd-b81a-445f-ad67-b18e9a1daf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256625565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4256625565
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2066504948
Short name T406
Test name
Test status
Simulation time 163668985 ps
CPU time 1.36 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:13 PM PDT 24
Peak memory 197844 kb
Host smart-a7847720-cc57-4e27-a259-e4454e426c60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066504948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2066504948
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.700276979
Short name T23
Test name
Test status
Simulation time 54898804461 ps
CPU time 188.46 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 198108 kb
Host smart-06ecc2eb-e660-4350-b8e6-438a9d2f4f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700276979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.700276979
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1584145762
Short name T501
Test name
Test status
Simulation time 218946767095 ps
CPU time 1679.33 seconds
Started May 05 12:41:04 PM PDT 24
Finished May 05 01:09:07 PM PDT 24
Peak memory 198148 kb
Host smart-86e24d58-2b52-4d62-ad2a-f7eee8ae88d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1584145762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1584145762
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2154431167
Short name T633
Test name
Test status
Simulation time 34232779 ps
CPU time 0.56 seconds
Started May 05 12:41:30 PM PDT 24
Finished May 05 12:41:31 PM PDT 24
Peak memory 194464 kb
Host smart-a0fe3ed3-13b9-4881-a642-0c646cc3e461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154431167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2154431167
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3270710268
Short name T421
Test name
Test status
Simulation time 68306371 ps
CPU time 0.72 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:08 PM PDT 24
Peak memory 195348 kb
Host smart-ca496614-8524-48eb-8735-6226ca3922d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270710268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3270710268
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1993172922
Short name T238
Test name
Test status
Simulation time 221391187 ps
CPU time 11.01 seconds
Started May 05 12:41:19 PM PDT 24
Finished May 05 12:41:30 PM PDT 24
Peak memory 197936 kb
Host smart-4029afd4-94c7-46ae-9cc0-63b0b426f3b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993172922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1993172922
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.488069735
Short name T340
Test name
Test status
Simulation time 272236340 ps
CPU time 0.9 seconds
Started May 05 12:41:29 PM PDT 24
Finished May 05 12:41:30 PM PDT 24
Peak memory 196172 kb
Host smart-483979cc-30e5-4dc7-8e16-ae6b86fd0997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488069735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.488069735
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.651641549
Short name T392
Test name
Test status
Simulation time 186287494 ps
CPU time 1.24 seconds
Started May 05 12:41:12 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 196492 kb
Host smart-520f71c4-35b3-403c-9793-be800cd68b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651641549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.651641549
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.445837281
Short name T198
Test name
Test status
Simulation time 43994097 ps
CPU time 1.83 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 198320 kb
Host smart-9030aae3-b17f-4679-b792-f582e1eff8cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445837281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.445837281
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.178722190
Short name T295
Test name
Test status
Simulation time 33305926 ps
CPU time 0.95 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 195368 kb
Host smart-0580cc34-f290-4152-bfb1-e36ee48366bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178722190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
178722190
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4089054553
Short name T383
Test name
Test status
Simulation time 63590545 ps
CPU time 1.21 seconds
Started May 05 12:41:03 PM PDT 24
Finished May 05 12:41:07 PM PDT 24
Peak memory 197948 kb
Host smart-b440602d-b636-4ea0-ab49-a70e6e68bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089054553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4089054553
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3291384950
Short name T458
Test name
Test status
Simulation time 130700831 ps
CPU time 1 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 195960 kb
Host smart-04f3de22-0dd7-4c9a-b785-e34c31640ce3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291384950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3291384950
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.98619794
Short name T484
Test name
Test status
Simulation time 104157290 ps
CPU time 1.25 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:41 PM PDT 24
Peak memory 197712 kb
Host smart-f7b92e34-9834-442c-8605-0bf1be3c60ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98619794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand
om_long_reg_writes_reg_reads.98619794
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3725899950
Short name T18
Test name
Test status
Simulation time 162422842 ps
CPU time 1.19 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:09 PM PDT 24
Peak memory 196160 kb
Host smart-777e0246-7acb-4a2b-9899-9a8de2c88f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725899950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3725899950
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.323470804
Short name T470
Test name
Test status
Simulation time 43373986 ps
CPU time 0.73 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 194096 kb
Host smart-d0fa5188-b495-481c-914d-604be127306c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323470804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.323470804
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3327254077
Short name T697
Test name
Test status
Simulation time 60995040448 ps
CPU time 702.15 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:53:10 PM PDT 24
Peak memory 198156 kb
Host smart-2278ffca-9edc-4f5b-9666-0a8f6b6c76ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3327254077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3327254077
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2481398563
Short name T423
Test name
Test status
Simulation time 20854220 ps
CPU time 0.57 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:40 PM PDT 24
Peak memory 193792 kb
Host smart-96179d90-8f8a-4bf8-ae4f-1531ae473ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481398563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2481398563
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2194306200
Short name T707
Test name
Test status
Simulation time 153994390 ps
CPU time 0.86 seconds
Started May 05 12:41:17 PM PDT 24
Finished May 05 12:41:19 PM PDT 24
Peak memory 196996 kb
Host smart-99c3ea69-f031-44d9-9c90-dedf07d57d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194306200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2194306200
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1130495124
Short name T538
Test name
Test status
Simulation time 839272820 ps
CPU time 13.2 seconds
Started May 05 12:41:31 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 196128 kb
Host smart-95ba5361-34bc-4d0b-a314-ba39497372cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130495124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1130495124
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2538706705
Short name T650
Test name
Test status
Simulation time 455096641 ps
CPU time 0.91 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 197788 kb
Host smart-b70ec8cb-639a-4ff7-a792-77317a176373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538706705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2538706705
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3702347471
Short name T397
Test name
Test status
Simulation time 31875151 ps
CPU time 0.68 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 194336 kb
Host smart-ec3545ca-0815-416d-9684-a6517485e1cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702347471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3702347471
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2714074616
Short name T212
Test name
Test status
Simulation time 529741595 ps
CPU time 2.8 seconds
Started May 05 12:41:16 PM PDT 24
Finished May 05 12:41:20 PM PDT 24
Peak memory 197900 kb
Host smart-d608c647-3979-406f-9222-6c84d718e489
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714074616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2714074616
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3613735371
Short name T382
Test name
Test status
Simulation time 129281159 ps
CPU time 2.88 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:44 PM PDT 24
Peak memory 197036 kb
Host smart-f4a30a13-7071-4182-ac69-4ce2659dcf81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613735371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3613735371
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.389216460
Short name T216
Test name
Test status
Simulation time 197438614 ps
CPU time 1.17 seconds
Started May 05 12:41:07 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197100 kb
Host smart-d3d39cd2-6d3a-475f-957e-5b7ecac2a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389216460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.389216460
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3233572860
Short name T711
Test name
Test status
Simulation time 109006493 ps
CPU time 1.17 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 196864 kb
Host smart-13910235-4d3a-41cf-8663-1a3731ad67b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233572860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3233572860
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.87187927
Short name T228
Test name
Test status
Simulation time 366599067 ps
CPU time 3.96 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 197940 kb
Host smart-565bbe2c-ed93-4510-9202-044ac44b2fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87187927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand
om_long_reg_writes_reg_reads.87187927
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1173030916
Short name T558
Test name
Test status
Simulation time 103280841 ps
CPU time 1.04 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:10 PM PDT 24
Peak memory 196140 kb
Host smart-96352406-65e9-4439-bbba-6835d4c0eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173030916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1173030916
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2625148695
Short name T281
Test name
Test status
Simulation time 370520253 ps
CPU time 1.39 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 197028 kb
Host smart-4ed2e141-56b6-4636-9b99-82c3462ebc32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625148695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2625148695
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3886314137
Short name T10
Test name
Test status
Simulation time 4461094244 ps
CPU time 49.79 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 198160 kb
Host smart-24122ade-1c8d-42b0-9b60-8a6aa9a8ea1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886314137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3886314137
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3752683553
Short name T534
Test name
Test status
Simulation time 147925651770 ps
CPU time 2009.7 seconds
Started May 05 12:41:08 PM PDT 24
Finished May 05 01:14:42 PM PDT 24
Peak memory 198220 kb
Host smart-f13401e7-7981-4003-8c57-c91895795a1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3752683553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3752683553
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4224703613
Short name T694
Test name
Test status
Simulation time 14098702 ps
CPU time 0.57 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 194016 kb
Host smart-9b815fc3-84c1-4f67-8595-8e49c54e68d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224703613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4224703613
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2161063541
Short name T677
Test name
Test status
Simulation time 97045825 ps
CPU time 0.69 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 194016 kb
Host smart-33ff89d6-eb78-452a-8b4a-f6377798ac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161063541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2161063541
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3996375161
Short name T168
Test name
Test status
Simulation time 216870249 ps
CPU time 5.75 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 197960 kb
Host smart-a90c8b26-1089-4563-aabf-f02d27158803
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996375161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3996375161
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1156531816
Short name T326
Test name
Test status
Simulation time 237798129 ps
CPU time 0.89 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 196132 kb
Host smart-44e31537-d93c-4220-84ec-40ac2771633e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156531816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1156531816
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3692882863
Short name T322
Test name
Test status
Simulation time 48825026 ps
CPU time 1.01 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 195840 kb
Host smart-de40df3f-7141-431c-b88a-6fa71b4e9df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692882863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3692882863
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1536636513
Short name T536
Test name
Test status
Simulation time 90166413 ps
CPU time 2.62 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 197996 kb
Host smart-dc9a5f23-b9e6-49d2-821f-5d043da31977
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536636513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1536636513
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1443541528
Short name T580
Test name
Test status
Simulation time 110740319 ps
CPU time 2.15 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 196172 kb
Host smart-4545920e-e088-4599-b29f-bff9706c0ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443541528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1443541528
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.435649198
Short name T106
Test name
Test status
Simulation time 19547417 ps
CPU time 0.72 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 195928 kb
Host smart-12413403-c7fc-4b28-854d-9a6f7df8b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435649198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.435649198
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4042064961
Short name T435
Test name
Test status
Simulation time 83624492 ps
CPU time 1.06 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 196560 kb
Host smart-b08a97da-53ba-45e3-a90c-e32b92fcd6ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042064961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4042064961
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1889169553
Short name T193
Test name
Test status
Simulation time 77057850 ps
CPU time 3.44 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 198000 kb
Host smart-cb111b33-d32b-49e1-85c6-b16340671b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889169553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1889169553
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3695968130
Short name T719
Test name
Test status
Simulation time 150778165 ps
CPU time 0.94 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 195512 kb
Host smart-9a26f431-635f-4721-87b5-848f7231d4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695968130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3695968130
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.687411222
Short name T525
Test name
Test status
Simulation time 142767737 ps
CPU time 0.79 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:41:28 PM PDT 24
Peak memory 195120 kb
Host smart-2f0a32e2-78f1-4688-a634-411d19950b5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687411222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.687411222
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3869241625
Short name T112
Test name
Test status
Simulation time 3764417992 ps
CPU time 50.62 seconds
Started May 05 12:41:19 PM PDT 24
Finished May 05 12:42:10 PM PDT 24
Peak memory 198104 kb
Host smart-19968242-2c3e-424c-9dce-497868a40278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869241625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3869241625
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2170421159
Short name T507
Test name
Test status
Simulation time 394772912414 ps
CPU time 987.85 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:57:49 PM PDT 24
Peak memory 198120 kb
Host smart-fe937174-de3c-4a0d-9e8d-0f3b9fcfd62f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2170421159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2170421159
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.4009644545
Short name T128
Test name
Test status
Simulation time 11660637 ps
CPU time 0.56 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 193804 kb
Host smart-6a015e94-5c7b-4cc4-875c-2d9a630fd609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009644545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.4009644545
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3865826133
Short name T215
Test name
Test status
Simulation time 29236807 ps
CPU time 0.71 seconds
Started May 05 12:41:05 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 195780 kb
Host smart-74d454e2-8ca9-493e-b096-7cd977105ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865826133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3865826133
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2025888752
Short name T151
Test name
Test status
Simulation time 585771513 ps
CPU time 14.86 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:25 PM PDT 24
Peak memory 197964 kb
Host smart-f5122bcb-8c42-480c-85af-d1d232022d25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025888752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2025888752
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3740341619
Short name T471
Test name
Test status
Simulation time 45207203 ps
CPU time 0.82 seconds
Started May 05 12:41:24 PM PDT 24
Finished May 05 12:41:25 PM PDT 24
Peak memory 195804 kb
Host smart-0e1d8f37-9c90-464e-97db-4865be92f94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740341619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3740341619
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3539769844
Short name T157
Test name
Test status
Simulation time 35062456 ps
CPU time 0.75 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:40 PM PDT 24
Peak memory 195276 kb
Host smart-bc744874-fc3c-4c5d-9786-16ba7ad5fcc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539769844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3539769844
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2125369622
Short name T586
Test name
Test status
Simulation time 68824243 ps
CPU time 2.43 seconds
Started May 05 12:41:40 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 196196 kb
Host smart-05894fb4-7b84-4587-a61a-689e05145de1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125369622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2125369622
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1704400559
Short name T53
Test name
Test status
Simulation time 284714156 ps
CPU time 2.21 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 195712 kb
Host smart-c1a0e279-eef4-4599-8f3e-ca3d448feb18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704400559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1704400559
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1380148160
Short name T618
Test name
Test status
Simulation time 154798517 ps
CPU time 1.04 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 196612 kb
Host smart-d9cbdab5-c462-4600-99ce-abac4b97ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380148160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1380148160
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2695328552
Short name T189
Test name
Test status
Simulation time 533485094 ps
CPU time 0.95 seconds
Started May 05 12:41:33 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 195752 kb
Host smart-33f5b7d7-7125-4b6f-a09e-e42139a52567
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695328552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2695328552
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1314528289
Short name T248
Test name
Test status
Simulation time 71107690 ps
CPU time 1.48 seconds
Started May 05 12:41:29 PM PDT 24
Finished May 05 12:41:31 PM PDT 24
Peak memory 197832 kb
Host smart-3bdc065f-5490-41f1-908e-73a0d51d9f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314528289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1314528289
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2647957937
Short name T576
Test name
Test status
Simulation time 209064776 ps
CPU time 1.28 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 196192 kb
Host smart-f76eeeeb-4716-4a52-826d-d4b755565618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647957937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2647957937
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.825381085
Short name T698
Test name
Test status
Simulation time 179910778 ps
CPU time 1.26 seconds
Started May 05 12:41:19 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 196252 kb
Host smart-cca6da5c-30e1-4843-a452-ccabd3d15638
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825381085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.825381085
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3302638147
Short name T597
Test name
Test status
Simulation time 54774073119 ps
CPU time 133.91 seconds
Started May 05 12:41:09 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 198120 kb
Host smart-97333a3f-6a08-4018-a8ba-36487b1bc6f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302638147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3302638147
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.34749699
Short name T26
Test name
Test status
Simulation time 15847560 ps
CPU time 0.6 seconds
Started May 05 12:41:17 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 193964 kb
Host smart-cef0ac0b-daa4-45b5-a9ae-24afc275c919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.34749699
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1396564448
Short name T511
Test name
Test status
Simulation time 115922109 ps
CPU time 0.9 seconds
Started May 05 12:41:21 PM PDT 24
Finished May 05 12:41:22 PM PDT 24
Peak memory 196344 kb
Host smart-47bd067e-b647-4ea4-8093-89343e7a9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396564448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1396564448
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2179994101
Short name T688
Test name
Test status
Simulation time 541529850 ps
CPU time 18.56 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:42:08 PM PDT 24
Peak memory 197836 kb
Host smart-54029da4-39dd-4992-9701-ae8400e44254
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179994101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2179994101
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1929644710
Short name T317
Test name
Test status
Simulation time 224588916 ps
CPU time 0.84 seconds
Started May 05 12:41:40 PM PDT 24
Finished May 05 12:41:42 PM PDT 24
Peak memory 195884 kb
Host smart-7fb52a31-b870-470a-a882-4f220627cb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929644710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1929644710
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.870132316
Short name T614
Test name
Test status
Simulation time 23493642 ps
CPU time 0.73 seconds
Started May 05 12:41:14 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 194376 kb
Host smart-71364709-0f53-4126-9f6b-d9ded182daff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870132316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.870132316
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1324561887
Short name T504
Test name
Test status
Simulation time 87895300 ps
CPU time 3.17 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:41:27 PM PDT 24
Peak memory 197960 kb
Host smart-1dd559ab-2324-45ea-9a70-7991e4177344
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324561887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1324561887
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1681954800
Short name T307
Test name
Test status
Simulation time 177277648 ps
CPU time 1.91 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:51 PM PDT 24
Peak memory 196056 kb
Host smart-294aa060-58b7-4a2e-9711-7cbde2860c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681954800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1681954800
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4212572245
Short name T293
Test name
Test status
Simulation time 42028798 ps
CPU time 1.16 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 196956 kb
Host smart-e71c41bf-89b0-47cb-9aa6-63a48fea9f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212572245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4212572245
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2447549710
Short name T666
Test name
Test status
Simulation time 105013632 ps
CPU time 1.19 seconds
Started May 05 12:41:34 PM PDT 24
Finished May 05 12:41:36 PM PDT 24
Peak memory 196832 kb
Host smart-d8718779-3b7f-4898-bc40-a264065eac5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447549710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2447549710
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1216238783
Short name T310
Test name
Test status
Simulation time 246873951 ps
CPU time 4.12 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:41:28 PM PDT 24
Peak memory 197868 kb
Host smart-dc6fe5a1-3b8c-4fb1-a3c1-10dc7018b2f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216238783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1216238783
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1077187366
Short name T394
Test name
Test status
Simulation time 100313792 ps
CPU time 1.06 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 195576 kb
Host smart-2bbe3335-048a-4184-9d72-f3e52b08567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077187366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1077187366
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.519088678
Short name T475
Test name
Test status
Simulation time 80030167 ps
CPU time 0.95 seconds
Started May 05 12:41:20 PM PDT 24
Finished May 05 12:41:21 PM PDT 24
Peak memory 196388 kb
Host smart-18907c65-b744-47e5-8be2-59ed9f3a84e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519088678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.519088678
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4117487099
Short name T213
Test name
Test status
Simulation time 24978876199 ps
CPU time 41.21 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:42:00 PM PDT 24
Peak memory 198028 kb
Host smart-bd34db32-3b47-49a0-ae61-b74aaf6b6b08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117487099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4117487099
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.871967587
Short name T63
Test name
Test status
Simulation time 115533636920 ps
CPU time 1136.16 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 01:00:35 PM PDT 24
Peak memory 198100 kb
Host smart-501d6278-0c1c-45f5-b544-ec9ffb9c006c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=871967587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.871967587
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3010025782
Short name T705
Test name
Test status
Simulation time 42935077 ps
CPU time 0.55 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:41:57 PM PDT 24
Peak memory 194508 kb
Host smart-4fa435f5-eb6d-4434-85ea-81c9a7d75987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010025782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3010025782
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1541514703
Short name T577
Test name
Test status
Simulation time 68154222 ps
CPU time 0.69 seconds
Started May 05 12:41:35 PM PDT 24
Finished May 05 12:41:36 PM PDT 24
Peak memory 194720 kb
Host smart-f1e88859-c0bf-4ac5-8a02-5e8cc74236b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541514703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1541514703
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3819856484
Short name T388
Test name
Test status
Simulation time 1829530340 ps
CPU time 20.02 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 12:41:36 PM PDT 24
Peak memory 196804 kb
Host smart-4cfeaa47-0f81-4272-92b0-e242be8766f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819856484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3819856484
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3075279581
Short name T262
Test name
Test status
Simulation time 271729638 ps
CPU time 0.84 seconds
Started May 05 12:41:29 PM PDT 24
Finished May 05 12:41:31 PM PDT 24
Peak memory 196696 kb
Host smart-6bd98ecd-7af4-40d1-b148-ae97732a4e37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075279581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3075279581
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1362571704
Short name T285
Test name
Test status
Simulation time 15925212 ps
CPU time 0.64 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:41:24 PM PDT 24
Peak memory 194264 kb
Host smart-c6afbe61-d677-4d74-a3eb-f7188395dbac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362571704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1362571704
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.54968617
Short name T415
Test name
Test status
Simulation time 259328706 ps
CPU time 2.62 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 197968 kb
Host smart-260739b7-8f37-40f8-9d59-f8d5ef193594
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54968617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.gpio_intr_with_filter_rand_intr_event.54968617
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3446940319
Short name T185
Test name
Test status
Simulation time 76757507 ps
CPU time 2.3 seconds
Started May 05 12:41:32 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 196724 kb
Host smart-47135a44-de12-4430-a1ed-158ff9e5797c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446940319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3446940319
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2321549606
Short name T259
Test name
Test status
Simulation time 32055721 ps
CPU time 1.24 seconds
Started May 05 12:41:35 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196928 kb
Host smart-a406e0d6-b52f-4558-8842-a1cd56a03bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321549606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2321549606
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2262107434
Short name T496
Test name
Test status
Simulation time 115691184 ps
CPU time 0.92 seconds
Started May 05 12:41:26 PM PDT 24
Finished May 05 12:41:28 PM PDT 24
Peak memory 196024 kb
Host smart-106704bd-66c8-407b-a9c9-a40548e462a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262107434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2262107434
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.113067288
Short name T417
Test name
Test status
Simulation time 513690363 ps
CPU time 5.92 seconds
Started May 05 12:41:40 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 197920 kb
Host smart-2deb908c-fdad-47e8-8eee-4f15de3615f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113067288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.113067288
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1654682645
Short name T51
Test name
Test status
Simulation time 37679569 ps
CPU time 0.81 seconds
Started May 05 12:41:13 PM PDT 24
Finished May 05 12:41:15 PM PDT 24
Peak memory 195268 kb
Host smart-c166b409-28cf-431c-8518-106c72d9a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654682645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1654682645
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.367950877
Short name T393
Test name
Test status
Simulation time 40146098 ps
CPU time 0.9 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 196316 kb
Host smart-f7955997-f06f-4897-a310-a2e4118d2b1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367950877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.367950877
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3376777331
Short name T207
Test name
Test status
Simulation time 19851921498 ps
CPU time 72.96 seconds
Started May 05 12:41:27 PM PDT 24
Finished May 05 12:42:40 PM PDT 24
Peak memory 198152 kb
Host smart-e3e4e91a-69d0-473c-9479-793223a07f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376777331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3376777331
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1528016990
Short name T246
Test name
Test status
Simulation time 44648949 ps
CPU time 0.59 seconds
Started May 05 12:40:32 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 193780 kb
Host smart-2e27accc-73f6-4c60-af2e-5ea18a556b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528016990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1528016990
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2267958237
Short name T117
Test name
Test status
Simulation time 44127744 ps
CPU time 0.9 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 195908 kb
Host smart-e2cf0a6c-1c99-465b-a2b7-a69f6c48bf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267958237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2267958237
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1983858833
Short name T201
Test name
Test status
Simulation time 284478606 ps
CPU time 7.31 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:48 PM PDT 24
Peak memory 197896 kb
Host smart-430718c9-859e-4901-96ec-0d06f8e45064
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983858833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1983858833
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.377312669
Short name T352
Test name
Test status
Simulation time 60903127 ps
CPU time 0.92 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 196576 kb
Host smart-6c68a1bb-dede-411a-8a77-6284add73610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377312669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.377312669
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.669046101
Short name T696
Test name
Test status
Simulation time 31037743 ps
CPU time 0.91 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 196704 kb
Host smart-c3873dc7-2283-4084-b3fa-2e211a34e625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669046101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.669046101
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3115432144
Short name T488
Test name
Test status
Simulation time 80323176 ps
CPU time 3.19 seconds
Started May 05 12:40:20 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 197948 kb
Host smart-b829469c-7882-4866-b887-f3cdb7c3ef7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115432144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3115432144
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.804130031
Short name T327
Test name
Test status
Simulation time 246274351 ps
CPU time 1.68 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 196076 kb
Host smart-fdfe3613-f61a-455b-b5b9-9bcea6692c3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804130031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.804130031
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2629210758
Short name T492
Test name
Test status
Simulation time 189294024 ps
CPU time 0.9 seconds
Started May 05 12:40:27 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 195952 kb
Host smart-07f6f80c-3ff0-40a3-a8fc-ea0d6e64a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629210758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2629210758
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2195511851
Short name T365
Test name
Test status
Simulation time 85640178 ps
CPU time 0.76 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 195424 kb
Host smart-b2e26c6e-39aa-45ef-bfa1-42d5d34d4487
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195511851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2195511851
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.886551882
Short name T635
Test name
Test status
Simulation time 72791048 ps
CPU time 1.56 seconds
Started May 05 12:40:47 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 197912 kb
Host smart-9cbfae30-8470-4702-8565-b263ed049b58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886551882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.886551882
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2229978826
Short name T35
Test name
Test status
Simulation time 185340589 ps
CPU time 0.91 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 213692 kb
Host smart-60f7058a-ce77-47b3-b29a-abc65ed35c5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229978826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2229978826
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2639237719
Short name T15
Test name
Test status
Simulation time 145375140 ps
CPU time 1.37 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 196636 kb
Host smart-b269d077-ab08-4f82-8cd8-f739fb567a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639237719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2639237719
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.4012328389
Short name T120
Test name
Test status
Simulation time 76088684 ps
CPU time 1.23 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 196452 kb
Host smart-7a561257-595f-423a-ab62-5a6b2b964ede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012328389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.4012328389
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.199588991
Short name T519
Test name
Test status
Simulation time 14520601976 ps
CPU time 196.19 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 198112 kb
Host smart-c5d235dd-de5d-40ca-a0fc-9f0835508dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199588991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.199588991
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1188194934
Short name T408
Test name
Test status
Simulation time 15927229 ps
CPU time 0.55 seconds
Started May 05 12:41:24 PM PDT 24
Finished May 05 12:41:25 PM PDT 24
Peak memory 193820 kb
Host smart-7e7fae5a-3a52-402d-99cd-0778c07884a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188194934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1188194934
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1940262898
Short name T427
Test name
Test status
Simulation time 375969750 ps
CPU time 0.73 seconds
Started May 05 12:41:38 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 194144 kb
Host smart-c5e41872-eaea-4d3d-a76e-83e54a80fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940262898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1940262898
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1071557438
Short name T444
Test name
Test status
Simulation time 725893884 ps
CPU time 6.89 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 197932 kb
Host smart-1cd35b3d-4972-4ad0-9911-7f24d7d915a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071557438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1071557438
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.935873489
Short name T323
Test name
Test status
Simulation time 251708154 ps
CPU time 1.03 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 196356 kb
Host smart-5b6225ab-e7d1-42be-8172-d6d5db443ae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935873489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.935873489
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3229282977
Short name T518
Test name
Test status
Simulation time 53305199 ps
CPU time 1.05 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 196620 kb
Host smart-9f838742-8f6d-40ad-b136-0628be4d8db8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229282977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3229282977
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.858580755
Short name T411
Test name
Test status
Simulation time 114840654 ps
CPU time 2.24 seconds
Started May 05 12:41:26 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 197976 kb
Host smart-c4978d18-37b7-40bf-927f-5b38f159eab2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858580755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.858580755
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1343007100
Short name T175
Test name
Test status
Simulation time 232516614 ps
CPU time 3.44 seconds
Started May 05 12:41:34 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 197220 kb
Host smart-f43d39ed-c9e2-4cac-a8ce-da95190e912b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343007100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1343007100
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1758268773
Short name T217
Test name
Test status
Simulation time 94415053 ps
CPU time 0.66 seconds
Started May 05 12:41:48 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 194224 kb
Host smart-4b9e9906-82b4-4f07-b78a-031e6126391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758268773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1758268773
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.481731018
Short name T431
Test name
Test status
Simulation time 32906631 ps
CPU time 0.82 seconds
Started May 05 12:41:28 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 196504 kb
Host smart-357d3a5a-8c64-45d8-907d-1f60740df61c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481731018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.481731018
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3496804221
Short name T9
Test name
Test status
Simulation time 99073361 ps
CPU time 1.21 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 197840 kb
Host smart-c632a5cd-37c4-4f94-9c80-995b432f9edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496804221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3496804221
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1864963785
Short name T275
Test name
Test status
Simulation time 122659262 ps
CPU time 0.72 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 195184 kb
Host smart-b3e22914-bf84-413f-ae74-ad5ca4697fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864963785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1864963785
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2667055040
Short name T668
Test name
Test status
Simulation time 43260368 ps
CPU time 1.24 seconds
Started May 05 12:41:33 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 196460 kb
Host smart-99c395b2-d5e3-4038-a4bc-5a245f932cbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667055040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2667055040
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3642768966
Short name T570
Test name
Test status
Simulation time 324592833307 ps
CPU time 229.33 seconds
Started May 05 12:41:26 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 198028 kb
Host smart-1e3e8d2c-e35b-453f-b487-99c5f64873dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642768966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3642768966
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3144714866
Short name T269
Test name
Test status
Simulation time 12546785 ps
CPU time 0.61 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 193860 kb
Host smart-be37ff40-cf93-4f57-8e18-d9ed96517c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144714866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3144714866
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1580355905
Short name T565
Test name
Test status
Simulation time 404437159 ps
CPU time 0.91 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 196456 kb
Host smart-377ca896-9570-44a0-954e-1c0c228159cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580355905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1580355905
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2373350704
Short name T647
Test name
Test status
Simulation time 364163224 ps
CPU time 9.93 seconds
Started May 05 12:41:18 PM PDT 24
Finished May 05 12:41:29 PM PDT 24
Peak memory 195360 kb
Host smart-2de950e9-05e3-4caa-add1-60f7063e96fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373350704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2373350704
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.479276791
Short name T124
Test name
Test status
Simulation time 595922135 ps
CPU time 1.14 seconds
Started May 05 12:41:29 PM PDT 24
Finished May 05 12:41:31 PM PDT 24
Peak memory 197808 kb
Host smart-94fb37b2-73ab-4bc4-9989-dccb7d9469a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479276791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.479276791
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2873902707
Short name T714
Test name
Test status
Simulation time 26501273 ps
CPU time 0.84 seconds
Started May 05 12:41:42 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 196404 kb
Host smart-7f40cdb5-c677-4ea8-b952-8416e112a1f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873902707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2873902707
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2616905272
Short name T303
Test name
Test status
Simulation time 275379830 ps
CPU time 3.07 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 198108 kb
Host smart-ee499ded-4adb-458c-93cc-7782820f20d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616905272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2616905272
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3306950772
Short name T583
Test name
Test status
Simulation time 30781781 ps
CPU time 1.06 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 196260 kb
Host smart-751199a8-2853-40e9-9abc-f1f07556c38a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306950772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3306950772
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4238039178
Short name T148
Test name
Test status
Simulation time 31522092 ps
CPU time 1.13 seconds
Started May 05 12:41:35 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 196980 kb
Host smart-ae1e720b-f6eb-4615-a829-19402a80661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238039178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4238039178
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2717501154
Short name T524
Test name
Test status
Simulation time 62049056 ps
CPU time 1.14 seconds
Started May 05 12:41:25 PM PDT 24
Finished May 05 12:41:27 PM PDT 24
Peak memory 196988 kb
Host smart-7925ac1c-7d3e-4df0-b0d9-6bc3d3627c34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717501154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2717501154
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1838214062
Short name T716
Test name
Test status
Simulation time 1876623299 ps
CPU time 4.34 seconds
Started May 05 12:41:33 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 197860 kb
Host smart-fb2ae74f-c1de-4918-ad96-097b0647a31d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838214062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1838214062
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2459121787
Short name T196
Test name
Test status
Simulation time 229352107 ps
CPU time 1.1 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 195720 kb
Host smart-4c815a9b-125d-452f-ba01-626296089717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459121787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2459121787
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3049479909
Short name T409
Test name
Test status
Simulation time 262059245 ps
CPU time 0.97 seconds
Started May 05 12:41:38 PM PDT 24
Finished May 05 12:41:40 PM PDT 24
Peak memory 196336 kb
Host smart-cad2b475-4927-4a0d-bd53-b6abeb073ae9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049479909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3049479909
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.518519856
Short name T523
Test name
Test status
Simulation time 17064349774 ps
CPU time 118.47 seconds
Started May 05 12:41:23 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 198084 kb
Host smart-6c8db199-a614-4f68-a3e4-9af9cb24ec6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518519856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.518519856
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4040062283
Short name T60
Test name
Test status
Simulation time 161351225493 ps
CPU time 2728.75 seconds
Started May 05 12:41:15 PM PDT 24
Finished May 05 01:26:50 PM PDT 24
Peak memory 198196 kb
Host smart-11e33cde-65ea-426d-a685-4d9f59569739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4040062283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4040062283
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3139020570
Short name T480
Test name
Test status
Simulation time 20829214 ps
CPU time 0.6 seconds
Started May 05 12:41:31 PM PDT 24
Finished May 05 12:41:32 PM PDT 24
Peak memory 193996 kb
Host smart-ff9cb39f-ace0-4e27-b5e8-0742d0c0db52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139020570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3139020570
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1632112940
Short name T197
Test name
Test status
Simulation time 47671726 ps
CPU time 0.61 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 193920 kb
Host smart-83f50138-0755-440c-9ab2-f50566fa872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632112940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1632112940
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1357365290
Short name T119
Test name
Test status
Simulation time 1548947111 ps
CPU time 26.95 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:42:14 PM PDT 24
Peak memory 196776 kb
Host smart-b8193fb7-1ab6-41d5-8553-e0a460ab72be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357365290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1357365290
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3248217824
Short name T508
Test name
Test status
Simulation time 74060300 ps
CPU time 0.99 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 197708 kb
Host smart-78e57572-02eb-4431-bc79-f65484697c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248217824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3248217824
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2231011035
Short name T588
Test name
Test status
Simulation time 145446279 ps
CPU time 0.8 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 195596 kb
Host smart-4654e4fc-e69c-4a8c-9c5b-c9417dc1be39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231011035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2231011035
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2063042026
Short name T105
Test name
Test status
Simulation time 115406115 ps
CPU time 1.41 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 196184 kb
Host smart-607972cd-bf69-4d97-9925-2f51e276c613
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063042026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2063042026
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.442153033
Short name T557
Test name
Test status
Simulation time 362245942 ps
CPU time 3.14 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 197524 kb
Host smart-371f0652-1eda-47cd-a0e8-e10c5b544bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442153033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
442153033
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2421959990
Short name T334
Test name
Test status
Simulation time 39339806 ps
CPU time 0.83 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 197144 kb
Host smart-f1a8d0c3-09e0-482c-a528-9febce834b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421959990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2421959990
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.71631494
Short name T541
Test name
Test status
Simulation time 47085449 ps
CPU time 1.04 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 196396 kb
Host smart-cd4accf4-8eff-4bbf-9487-338b5d6c0336
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71631494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_
pulldown.71631494
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2278663059
Short name T564
Test name
Test status
Simulation time 232765385 ps
CPU time 3.87 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 197876 kb
Host smart-67c2aaf3-7d2d-4e40-b664-43967df44b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278663059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2278663059
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3585923915
Short name T509
Test name
Test status
Simulation time 102860070 ps
CPU time 0.89 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 195400 kb
Host smart-468b32b2-f619-4249-a9a1-0fbf5d983966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585923915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3585923915
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.82898981
Short name T369
Test name
Test status
Simulation time 73034365 ps
CPU time 1.12 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 195456 kb
Host smart-7bf1bf69-9807-4cc7-8d90-83227c875266
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82898981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.82898981
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3016902222
Short name T624
Test name
Test status
Simulation time 63455706118 ps
CPU time 184.79 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:44:45 PM PDT 24
Peak memory 198124 kb
Host smart-d0e3ea81-1b46-4137-a2be-ae6944255aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016902222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3016902222
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2248204638
Short name T372
Test name
Test status
Simulation time 62786867 ps
CPU time 0.58 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 194000 kb
Host smart-ffb2aa57-e3ee-4b01-b02e-f39612199096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248204638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2248204638
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2768336728
Short name T685
Test name
Test status
Simulation time 21245452 ps
CPU time 0.6 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 193964 kb
Host smart-1d39eba3-3167-45d3-ac0a-4c277bfea383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768336728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2768336728
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4218029166
Short name T487
Test name
Test status
Simulation time 1416101452 ps
CPU time 19.45 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 196612 kb
Host smart-33b40a05-656b-4a41-b3d4-9816cb115d94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218029166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4218029166
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2743321263
Short name T537
Test name
Test status
Simulation time 267171642 ps
CPU time 0.87 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 196684 kb
Host smart-c1c0cec1-ab5c-4c86-baee-e69cad1703e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743321263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2743321263
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2004680770
Short name T208
Test name
Test status
Simulation time 1318762299 ps
CPU time 1.22 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 195964 kb
Host smart-73db9b28-9dff-41f9-af9c-9b4846394a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004680770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2004680770
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3500715478
Short name T284
Test name
Test status
Simulation time 162199705 ps
CPU time 3.31 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 197928 kb
Host smart-37e92ff6-7b73-45af-95de-82af9c661cd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500715478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3500715478
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3689316325
Short name T437
Test name
Test status
Simulation time 246755425 ps
CPU time 1.97 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:41:57 PM PDT 24
Peak memory 197004 kb
Host smart-5a53124c-dbde-4f13-a796-cdb4e30c3b83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689316325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3689316325
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.436894204
Short name T521
Test name
Test status
Simulation time 93053776 ps
CPU time 0.79 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 195356 kb
Host smart-03b74cd8-6da7-4cae-9cd6-f4e059d5e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436894204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.436894204
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3823621263
Short name T430
Test name
Test status
Simulation time 43506780 ps
CPU time 0.71 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:02 PM PDT 24
Peak memory 194368 kb
Host smart-a2ac3c8c-9384-44be-b735-2207e5e824a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823621263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3823621263
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1510500355
Short name T592
Test name
Test status
Simulation time 1844712583 ps
CPU time 5.17 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 197832 kb
Host smart-ca435560-cd94-4f38-b93c-a6fcd4416c90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510500355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1510500355
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1058795475
Short name T552
Test name
Test status
Simulation time 154208670 ps
CPU time 0.98 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:42 PM PDT 24
Peak memory 195272 kb
Host smart-e45ba1d7-c5b3-423b-818c-4af36656c065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058795475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1058795475
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2213350570
Short name T362
Test name
Test status
Simulation time 76915758 ps
CPU time 1.25 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:42:17 PM PDT 24
Peak memory 195484 kb
Host smart-fe69464a-7509-4291-9b8e-58924bd9651f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213350570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2213350570
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.998092973
Short name T180
Test name
Test status
Simulation time 17272166664 ps
CPU time 242.44 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:45:44 PM PDT 24
Peak memory 198060 kb
Host smart-9f8dde0c-a8ed-4318-8839-c4d64ec69034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998092973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.998092973
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.400005337
Short name T29
Test name
Test status
Simulation time 75176876833 ps
CPU time 1507.89 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 01:06:59 PM PDT 24
Peak memory 198132 kb
Host smart-e5ad3859-98a5-459c-a399-6c57c7af9dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=400005337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.400005337
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.34684614
Short name T158
Test name
Test status
Simulation time 52434690 ps
CPU time 0.59 seconds
Started May 05 12:41:48 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 194512 kb
Host smart-0cea95a2-71f6-44fe-bf5b-dd20758b69e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.34684614
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4021793536
Short name T620
Test name
Test status
Simulation time 235878565 ps
CPU time 0.69 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 194716 kb
Host smart-0af30bf2-614d-40a8-870e-cfe6281fac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021793536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4021793536
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.418999973
Short name T689
Test name
Test status
Simulation time 431212557 ps
CPU time 5.89 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 196856 kb
Host smart-c2a939c1-5eba-4c2f-8a0a-c215931fd5f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418999973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.418999973
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3823692258
Short name T132
Test name
Test status
Simulation time 184072999 ps
CPU time 0.9 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 195980 kb
Host smart-9d18fd71-0759-44cf-88fc-72ca62aa4114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823692258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3823692258
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.951528421
Short name T548
Test name
Test status
Simulation time 414159285 ps
CPU time 0.81 seconds
Started May 05 12:42:02 PM PDT 24
Finished May 05 12:42:04 PM PDT 24
Peak memory 195376 kb
Host smart-8453ad13-6bd2-40c9-862b-79e16d02c106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951528421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.951528421
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1422898626
Short name T644
Test name
Test status
Simulation time 339546289 ps
CPU time 3.21 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 197964 kb
Host smart-c3e7f3b2-adc2-4028-bc01-1406d97cb07b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422898626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1422898626
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1823142775
Short name T385
Test name
Test status
Simulation time 96639718 ps
CPU time 2.06 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 196396 kb
Host smart-153e5032-97d0-492d-83db-aae435bab1d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823142775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1823142775
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1548386348
Short name T301
Test name
Test status
Simulation time 85064342 ps
CPU time 0.7 seconds
Started May 05 12:41:41 PM PDT 24
Finished May 05 12:41:43 PM PDT 24
Peak memory 195320 kb
Host smart-f57678dc-b2b9-41f3-8d2b-5df913467941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548386348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1548386348
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.655120587
Short name T483
Test name
Test status
Simulation time 447449239 ps
CPU time 1.06 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 195804 kb
Host smart-6191020f-0f89-4608-a439-6ec884d0f8b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655120587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.655120587
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2776711081
Short name T463
Test name
Test status
Simulation time 266940131 ps
CPU time 6.18 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 197612 kb
Host smart-e1fce295-33b4-4941-804c-44e14f9da951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776711081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2776711081
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3471952054
Short name T233
Test name
Test status
Simulation time 249065732 ps
CPU time 1.27 seconds
Started May 05 12:41:34 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 195628 kb
Host smart-6d6095c0-272c-44a0-b6cf-02beb40b00ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471952054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3471952054
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1302534765
Short name T55
Test name
Test status
Simulation time 87164679 ps
CPU time 1.18 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 196616 kb
Host smart-898f738b-959c-478a-9780-977412319469
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302534765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1302534765
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4066016582
Short name T6
Test name
Test status
Simulation time 13767175014 ps
CPU time 37.68 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:42:23 PM PDT 24
Peak memory 198120 kb
Host smart-f21277df-8c8e-480b-bd06-ed6807493851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066016582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4066016582
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2404486539
Short name T674
Test name
Test status
Simulation time 32155928940 ps
CPU time 656.61 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:52:54 PM PDT 24
Peak memory 198224 kb
Host smart-1930ba1a-2d07-4f9d-8448-f97fd0c611ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2404486539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2404486539
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2181449325
Short name T434
Test name
Test status
Simulation time 51392075 ps
CPU time 0.59 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:52 PM PDT 24
Peak memory 194520 kb
Host smart-793d6074-3f6d-4068-bc8e-2a5b47d42bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181449325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2181449325
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3386761558
Short name T147
Test name
Test status
Simulation time 41937227 ps
CPU time 0.85 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 195364 kb
Host smart-d8ff6fc4-277f-43a2-804c-3b3004094ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386761558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3386761558
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1805519845
Short name T653
Test name
Test status
Simulation time 169600216 ps
CPU time 3.32 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 195636 kb
Host smart-313b0c63-bd10-4016-b68e-163fd6baa789
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805519845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1805519845
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.97373172
Short name T135
Test name
Test status
Simulation time 117593053 ps
CPU time 0.93 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:03 PM PDT 24
Peak memory 197148 kb
Host smart-5640e156-2d07-4637-87e4-95dc3d1c465c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97373172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.97373172
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2602556918
Short name T560
Test name
Test status
Simulation time 53795142 ps
CPU time 1.16 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 195628 kb
Host smart-775cb9fb-a8ee-4ee0-acd0-57bafadff8e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602556918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2602556918
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1879002889
Short name T465
Test name
Test status
Simulation time 581307740 ps
CPU time 2.82 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 198000 kb
Host smart-79b7ab6d-4629-4421-85e0-72ac5c237a93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879002889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1879002889
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.316096318
Short name T672
Test name
Test status
Simulation time 130613141 ps
CPU time 2.52 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 196984 kb
Host smart-4a71312e-8f0c-4166-b73d-d480be160931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316096318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
316096318
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3936704640
Short name T675
Test name
Test status
Simulation time 33840379 ps
CPU time 1.23 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:38 PM PDT 24
Peak memory 196988 kb
Host smart-7a01b20d-5488-4c1e-887a-6ac950a8237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936704640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3936704640
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.465133928
Short name T264
Test name
Test status
Simulation time 81408518 ps
CPU time 0.94 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 195924 kb
Host smart-9efbea6c-6589-481a-8b4c-9685266ca151
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465133928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.465133928
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.384593683
Short name T292
Test name
Test status
Simulation time 140213629 ps
CPU time 6.14 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 198028 kb
Host smart-6badbfff-fb57-4a5a-8eb1-060c7d11ea2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384593683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.384593683
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1112889094
Short name T549
Test name
Test status
Simulation time 74233786 ps
CPU time 0.84 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:51 PM PDT 24
Peak memory 195440 kb
Host smart-29ff486e-5a37-42b0-a6ea-cf7a9e1d7656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112889094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1112889094
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2782973942
Short name T473
Test name
Test status
Simulation time 128213902 ps
CPU time 0.99 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:03 PM PDT 24
Peak memory 196316 kb
Host smart-13c09649-bb26-4233-9cce-ba37be636506
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782973942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2782973942
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1032757319
Short name T357
Test name
Test status
Simulation time 49198157144 ps
CPU time 168.12 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:44:34 PM PDT 24
Peak memory 198108 kb
Host smart-54257dff-236b-4304-bddc-6d67d58013c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032757319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1032757319
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.854734087
Short name T610
Test name
Test status
Simulation time 38835233 ps
CPU time 0.57 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 193756 kb
Host smart-f007a027-e210-445c-8a90-5a8311b8e2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854734087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.854734087
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3036551515
Short name T451
Test name
Test status
Simulation time 85700541 ps
CPU time 1 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 195668 kb
Host smart-dd7d2457-92e7-49b6-9b97-d99c5284a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036551515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3036551515
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1094642202
Short name T665
Test name
Test status
Simulation time 2280074403 ps
CPU time 8.85 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 197948 kb
Host smart-12e9a15f-7f70-439d-82aa-e11601905228
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094642202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1094642202
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2586635107
Short name T308
Test name
Test status
Simulation time 30794617 ps
CPU time 0.69 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 194620 kb
Host smart-1cbbbc3f-b3e2-41e5-ba62-0f1749101f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586635107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2586635107
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2317497327
Short name T11
Test name
Test status
Simulation time 53741136 ps
CPU time 0.96 seconds
Started May 05 12:42:02 PM PDT 24
Finished May 05 12:42:04 PM PDT 24
Peak memory 196772 kb
Host smart-0d75736b-e96e-4766-bb6f-fb1013c6ae1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317497327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2317497327
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2548844598
Short name T199
Test name
Test status
Simulation time 87429998 ps
CPU time 3.32 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 198004 kb
Host smart-f7624533-0588-4a70-9eae-9262224dd88b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548844598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2548844598
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3387713752
Short name T498
Test name
Test status
Simulation time 183955978 ps
CPU time 1.48 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:00 PM PDT 24
Peak memory 195692 kb
Host smart-e6cbae31-01d8-409b-8021-f54bf5e106b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387713752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3387713752
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3050388539
Short name T581
Test name
Test status
Simulation time 72200475 ps
CPU time 0.84 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 196424 kb
Host smart-f1b1faec-5125-4ceb-ba2e-5467e84f4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050388539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3050388539
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2646298866
Short name T122
Test name
Test status
Simulation time 32791018 ps
CPU time 0.78 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:53 PM PDT 24
Peak memory 195336 kb
Host smart-3b6871ee-6223-4edc-a99e-3a2e6436a410
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646298866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2646298866
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1944657116
Short name T3
Test name
Test status
Simulation time 354013600 ps
CPU time 4.63 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 197836 kb
Host smart-a1099cfd-55c7-4eaf-9584-3506930b64a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944657116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1944657116
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2113864628
Short name T436
Test name
Test status
Simulation time 418732736 ps
CPU time 1.54 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:41:57 PM PDT 24
Peak memory 196824 kb
Host smart-da41e559-1cb8-4697-86bc-683114a87cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113864628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2113864628
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3701932485
Short name T464
Test name
Test status
Simulation time 170977876 ps
CPU time 1.17 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 195404 kb
Host smart-9dd30027-8375-45c2-8828-79b90c139439
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701932485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3701932485
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4267412639
Short name T378
Test name
Test status
Simulation time 3372762321 ps
CPU time 40.03 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 198092 kb
Host smart-6b231282-41ad-4162-b2fe-c6166dd2f0a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267412639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4267412639
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3573589531
Short name T346
Test name
Test status
Simulation time 13683568 ps
CPU time 0.6 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 194504 kb
Host smart-71e6765e-fe73-4908-bab8-984a94a5434d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573589531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3573589531
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.663789264
Short name T443
Test name
Test status
Simulation time 146006025 ps
CPU time 0.85 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:41:59 PM PDT 24
Peak memory 197228 kb
Host smart-dcd98614-e449-40e2-a270-bf3396b79392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663789264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.663789264
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1898729886
Short name T607
Test name
Test status
Simulation time 935002802 ps
CPU time 25.69 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 196556 kb
Host smart-5a7f2299-68e5-4e09-9082-2597cfd4fd81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898729886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1898729886
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2674607097
Short name T637
Test name
Test status
Simulation time 168641883 ps
CPU time 0.99 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 196488 kb
Host smart-c8e6042e-4c4d-4251-9c84-072e0eff4a14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674607097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2674607097
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1497053245
Short name T358
Test name
Test status
Simulation time 82181395 ps
CPU time 0.85 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:02 PM PDT 24
Peak memory 195440 kb
Host smart-4de8ed90-40a9-4d55-8385-c29e3b7add4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497053245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1497053245
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3294804950
Short name T572
Test name
Test status
Simulation time 116778532 ps
CPU time 2.43 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 198028 kb
Host smart-2e23e453-fed5-4677-b7f7-d8bd0030d53b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294804950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3294804950
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1490803209
Short name T265
Test name
Test status
Simulation time 1112577850 ps
CPU time 3.3 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 197088 kb
Host smart-888deade-c4a2-42bf-b8cb-2940bcff7649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490803209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1490803209
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2051710713
Short name T335
Test name
Test status
Simulation time 31553005 ps
CPU time 1.28 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 197880 kb
Host smart-4778cb02-0779-47f0-ba5a-5d45b8387403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051710713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2051710713
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1668533872
Short name T298
Test name
Test status
Simulation time 115411216 ps
CPU time 1.3 seconds
Started May 05 12:41:38 PM PDT 24
Finished May 05 12:41:40 PM PDT 24
Peak memory 197888 kb
Host smart-1a0dc8b3-8d41-42a2-9308-32e07d168a74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668533872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1668533872
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4175591256
Short name T605
Test name
Test status
Simulation time 1149041243 ps
CPU time 3.34 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 197856 kb
Host smart-03f1ded3-1d0a-471a-abf3-f691d2daaa12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175591256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.4175591256
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3986507193
Short name T282
Test name
Test status
Simulation time 278328245 ps
CPU time 1.01 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 196292 kb
Host smart-13125310-8df7-4431-9b78-b185bf8834e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986507193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3986507193
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2915509200
Short name T65
Test name
Test status
Simulation time 158124187 ps
CPU time 1.18 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:01 PM PDT 24
Peak memory 195708 kb
Host smart-fa5ce02e-b742-44f0-bfe5-74d0a4e9a609
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915509200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2915509200
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1870221852
Short name T252
Test name
Test status
Simulation time 137496947020 ps
CPU time 166.32 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:44:36 PM PDT 24
Peak memory 198124 kb
Host smart-f0a504fd-39fc-4c04-9cd7-b9c0adcce9c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870221852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1870221852
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.813204047
Short name T384
Test name
Test status
Simulation time 45814230 ps
CPU time 0.59 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 193836 kb
Host smart-e3299d81-4f9b-4aa4-898b-4b3ed0441402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813204047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.813204047
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3487221815
Short name T12
Test name
Test status
Simulation time 38639905 ps
CPU time 0.91 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:41:57 PM PDT 24
Peak memory 195832 kb
Host smart-be46a70d-7400-420f-874e-c8a5a20bd1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487221815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3487221815
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1118962552
Short name T595
Test name
Test status
Simulation time 1942621147 ps
CPU time 16.87 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:14 PM PDT 24
Peak memory 196724 kb
Host smart-9edec999-7ace-4095-b0fb-10bbb0413cd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118962552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1118962552
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2608011406
Short name T460
Test name
Test status
Simulation time 89312162 ps
CPU time 0.67 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 195396 kb
Host smart-48070166-79f6-486b-8798-f3c947c6f68c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608011406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2608011406
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1227871232
Short name T332
Test name
Test status
Simulation time 87273577 ps
CPU time 1.47 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:03 PM PDT 24
Peak memory 197904 kb
Host smart-898a18fe-fc64-41f1-8d43-2a29ae0fc5cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227871232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1227871232
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3848802911
Short name T567
Test name
Test status
Simulation time 26253528 ps
CPU time 1.06 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 196356 kb
Host smart-a24853ad-62d8-427f-a8ae-4ec4670ac440
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848802911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3848802911
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1485829946
Short name T268
Test name
Test status
Simulation time 215977101 ps
CPU time 1.39 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 195728 kb
Host smart-82da1e7f-6741-4b87-aeb1-ab8a9eefa2b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485829946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1485829946
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2831588233
Short name T331
Test name
Test status
Simulation time 549972040 ps
CPU time 1.23 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:02 PM PDT 24
Peak memory 196828 kb
Host smart-cf63e04a-70ad-443e-9651-fcf1b2f802af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831588233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2831588233
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2608201323
Short name T116
Test name
Test status
Simulation time 70408573 ps
CPU time 1.3 seconds
Started May 05 12:41:48 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 196940 kb
Host smart-c87ca616-c636-4824-8e22-cd742eb97bb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608201323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2608201323
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1990067124
Short name T433
Test name
Test status
Simulation time 295303456 ps
CPU time 2.03 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 197672 kb
Host smart-c4b07bc7-4dcd-4778-829a-6b0b526af6c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990067124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1990067124
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.816507669
Short name T532
Test name
Test status
Simulation time 54138733 ps
CPU time 0.78 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:00 PM PDT 24
Peak memory 195284 kb
Host smart-0c300c1e-9629-4b41-852a-598e8e579811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816507669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.816507669
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1253408690
Short name T191
Test name
Test status
Simulation time 72783348 ps
CPU time 1.04 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:41:58 PM PDT 24
Peak memory 195448 kb
Host smart-ec804d87-a682-4b05-aa0a-375272ca3ab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253408690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1253408690
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2823264949
Short name T528
Test name
Test status
Simulation time 81669942880 ps
CPU time 183.63 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:44:56 PM PDT 24
Peak memory 198052 kb
Host smart-4e74a28a-eb9f-4ba7-934a-c1590d500c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823264949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2823264949
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.420900298
Short name T414
Test name
Test status
Simulation time 41347446 ps
CPU time 0.56 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:41:55 PM PDT 24
Peak memory 193856 kb
Host smart-539006f8-289b-4795-9e46-50037541b33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420900298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.420900298
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1443749360
Short name T257
Test name
Test status
Simulation time 42007011 ps
CPU time 0.9 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:42:16 PM PDT 24
Peak memory 195828 kb
Host smart-fc750ed2-8aba-4119-93c0-e4220e5055cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443749360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1443749360
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1802250200
Short name T603
Test name
Test status
Simulation time 3192990140 ps
CPU time 19.43 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:20 PM PDT 24
Peak memory 197344 kb
Host smart-21341f61-88e9-43b3-a492-f972955cdb7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802250200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1802250200
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2061156145
Short name T299
Test name
Test status
Simulation time 102052559 ps
CPU time 1 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:51 PM PDT 24
Peak memory 196240 kb
Host smart-40bf9d5f-ca26-4f4a-a92f-b2fe47fb4ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061156145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2061156145
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3953218431
Short name T70
Test name
Test status
Simulation time 79924395 ps
CPU time 0.7 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 194292 kb
Host smart-263c0755-c60a-41d0-9233-757f38b7b0ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953218431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3953218431
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.23122020
Short name T52
Test name
Test status
Simulation time 85438080 ps
CPU time 3.32 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 198084 kb
Host smart-0f09b9a7-acef-4581-8c38-967df0c9a9db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23122020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.gpio_intr_with_filter_rand_intr_event.23122020
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4243088287
Short name T280
Test name
Test status
Simulation time 194241655 ps
CPU time 1.44 seconds
Started May 05 12:41:37 PM PDT 24
Finished May 05 12:41:39 PM PDT 24
Peak memory 197488 kb
Host smart-6cd15dc9-97a7-456c-9e7e-f68769bbadd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243088287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4243088287
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.984442136
Short name T686
Test name
Test status
Simulation time 177860739 ps
CPU time 0.91 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 197168 kb
Host smart-08303e63-56e8-43b8-b108-ef12f3aecb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984442136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.984442136
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1188305827
Short name T113
Test name
Test status
Simulation time 262904953 ps
CPU time 1.25 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:51 PM PDT 24
Peak memory 197220 kb
Host smart-37258154-5705-4cf0-b7ff-06a0e1aeb18c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188305827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1188305827
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2226365174
Short name T353
Test name
Test status
Simulation time 367084381 ps
CPU time 4.06 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 197800 kb
Host smart-79482780-7ac1-4615-890e-8eefea0fd877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226365174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2226365174
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.70303356
Short name T226
Test name
Test status
Simulation time 83851583 ps
CPU time 1.37 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:04 PM PDT 24
Peak memory 197876 kb
Host smart-3aa1cb9d-7abf-47ee-8a9d-c1d7fe9658f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70303356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.70303356
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.777936979
Short name T237
Test name
Test status
Simulation time 112653991 ps
CPU time 0.75 seconds
Started May 05 12:41:46 PM PDT 24
Finished May 05 12:41:48 PM PDT 24
Peak memory 195196 kb
Host smart-acdc6332-d1be-419d-b997-3caa1158e609
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777936979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.777936979
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3796558039
Short name T347
Test name
Test status
Simulation time 42530030175 ps
CPU time 116.51 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:44:01 PM PDT 24
Peak memory 198068 kb
Host smart-722b81f1-7af0-4384-8201-3be0600f80d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796558039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3796558039
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.435824042
Short name T186
Test name
Test status
Simulation time 40687402 ps
CPU time 0.58 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 194716 kb
Host smart-2bd1184d-096d-49df-91ef-3817ee9aea88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435824042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.435824042
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2666590869
Short name T229
Test name
Test status
Simulation time 45827625 ps
CPU time 0.84 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 195160 kb
Host smart-ca674484-2c97-4f50-b123-16f0ee315c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666590869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2666590869
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.232620064
Short name T139
Test name
Test status
Simulation time 2712802583 ps
CPU time 26.74 seconds
Started May 05 12:40:17 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 197516 kb
Host smart-00751240-8b5c-425f-b451-67ca23d2903b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232620064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.232620064
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4201762317
Short name T254
Test name
Test status
Simulation time 70797047 ps
CPU time 1.01 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 197116 kb
Host smart-09376bdb-80a5-4b78-9133-ba739dc7da7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201762317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4201762317
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4017235924
Short name T619
Test name
Test status
Simulation time 234881845 ps
CPU time 1.05 seconds
Started May 05 12:40:28 PM PDT 24
Finished May 05 12:40:29 PM PDT 24
Peak memory 196684 kb
Host smart-364016e2-caea-4634-ba25-deb98950b77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017235924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4017235924
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.693124539
Short name T277
Test name
Test status
Simulation time 61011650 ps
CPU time 2.37 seconds
Started May 05 12:40:29 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 197972 kb
Host smart-eb97499a-3d44-425b-ace4-6a1ca875e9fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693124539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.693124539
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2314361626
Short name T514
Test name
Test status
Simulation time 92942817 ps
CPU time 2.22 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:51 PM PDT 24
Peak memory 195720 kb
Host smart-dbee4f63-5b72-4afe-8452-bb15233a4093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314361626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2314361626
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1838984084
Short name T418
Test name
Test status
Simulation time 77496652 ps
CPU time 0.98 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 195932 kb
Host smart-aa8faed4-07b7-4326-815f-164d3ec7fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838984084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1838984084
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3028646628
Short name T380
Test name
Test status
Simulation time 373592872 ps
CPU time 1.3 seconds
Started May 05 12:40:36 PM PDT 24
Finished May 05 12:40:38 PM PDT 24
Peak memory 197896 kb
Host smart-3d127dd5-3180-42b4-ae1a-9e9773228614
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028646628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3028646628
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3447387536
Short name T422
Test name
Test status
Simulation time 344179049 ps
CPU time 4.31 seconds
Started May 05 12:40:32 PM PDT 24
Finished May 05 12:40:37 PM PDT 24
Peak memory 197888 kb
Host smart-323dc270-10f1-4f24-9d89-50345992d7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447387536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3447387536
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4176817524
Short name T255
Test name
Test status
Simulation time 42761879 ps
CPU time 1.23 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 196344 kb
Host smart-b94c832a-fe52-47b7-9870-a2c198b268f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176817524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4176817524
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.487198032
Short name T517
Test name
Test status
Simulation time 55318453 ps
CPU time 1.09 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 195472 kb
Host smart-61755670-ff12-43c8-8845-7f54c30201e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487198032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.487198032
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3815401640
Short name T657
Test name
Test status
Simulation time 29166848143 ps
CPU time 57.3 seconds
Started May 05 12:40:47 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 198320 kb
Host smart-efb2b519-db9f-4fc3-a596-4078d69e19ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815401640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3815401640
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4287595665
Short name T270
Test name
Test status
Simulation time 11722668 ps
CPU time 0.58 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 193764 kb
Host smart-a5018639-437f-4f5e-ae7e-9ab05ef70a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287595665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4287595665
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2660645459
Short name T477
Test name
Test status
Simulation time 61036121 ps
CPU time 0.62 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 194024 kb
Host smart-f1459714-041d-4786-8bd2-1b930646c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660645459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2660645459
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3234888576
Short name T391
Test name
Test status
Simulation time 2627752607 ps
CPU time 16.97 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 196780 kb
Host smart-c2742d78-ffd9-4ce4-aae4-592ae4009f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234888576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3234888576
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1581433271
Short name T648
Test name
Test status
Simulation time 75740721 ps
CPU time 1.07 seconds
Started May 05 12:40:36 PM PDT 24
Finished May 05 12:40:38 PM PDT 24
Peak memory 196372 kb
Host smart-7652485d-bead-4082-98bf-eddc034a43e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581433271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1581433271
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3383441425
Short name T702
Test name
Test status
Simulation time 185937278 ps
CPU time 0.72 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 195248 kb
Host smart-ea1fc546-44c0-4e7e-9a8e-e67b50d72a13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383441425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3383441425
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1572745526
Short name T164
Test name
Test status
Simulation time 177484383 ps
CPU time 3.65 seconds
Started May 05 12:40:35 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 197976 kb
Host smart-34000a3d-ce50-4007-b630-e7d6e8879adf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572745526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1572745526
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3704063675
Short name T355
Test name
Test status
Simulation time 433384592 ps
CPU time 2.16 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:48 PM PDT 24
Peak memory 195984 kb
Host smart-a148f64f-88b8-4aad-995c-341762cbb798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704063675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3704063675
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3117437887
Short name T348
Test name
Test status
Simulation time 21545529 ps
CPU time 0.7 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 194176 kb
Host smart-0deacb20-5be3-4df0-a2e3-bdc9587312bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117437887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3117437887
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2787754778
Short name T176
Test name
Test status
Simulation time 48866777 ps
CPU time 0.93 seconds
Started May 05 12:40:39 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 195764 kb
Host smart-b19312e2-4997-4bc6-b42a-f3d11e70e20a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787754778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2787754778
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2216432504
Short name T663
Test name
Test status
Simulation time 119304747 ps
CPU time 3.35 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 197692 kb
Host smart-2781062e-4c7f-433d-8bb4-159fba9a3449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216432504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2216432504
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3537762829
Short name T227
Test name
Test status
Simulation time 129873523 ps
CPU time 1.03 seconds
Started May 05 12:40:58 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 196124 kb
Host smart-7d8d9e9d-0fe9-496c-9e5f-af782e57f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537762829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3537762829
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4066663693
Short name T424
Test name
Test status
Simulation time 218744693 ps
CPU time 1.06 seconds
Started May 05 12:40:32 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 196176 kb
Host smart-804977fa-4a4c-40d1-86ba-2eb215ebd339
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066663693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4066663693
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3504221383
Short name T2
Test name
Test status
Simulation time 2078795829 ps
CPU time 23.45 seconds
Started May 05 12:40:35 PM PDT 24
Finished May 05 12:41:00 PM PDT 24
Peak memory 197848 kb
Host smart-bda1506d-0b96-400f-af88-58e8b6c8369e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504221383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3504221383
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3935037826
Short name T616
Test name
Test status
Simulation time 28381328 ps
CPU time 0.6 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 192680 kb
Host smart-1d5703ea-aff9-4fb0-a493-daff9ea8c278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935037826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3935037826
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.612460368
Short name T568
Test name
Test status
Simulation time 21682203 ps
CPU time 0.74 seconds
Started May 05 12:40:49 PM PDT 24
Finished May 05 12:40:51 PM PDT 24
Peak memory 195256 kb
Host smart-be420b99-9607-4c26-bf34-ac0bf0ee159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612460368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.612460368
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3444361819
Short name T351
Test name
Test status
Simulation time 680017203 ps
CPU time 18.1 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:41:03 PM PDT 24
Peak memory 197836 kb
Host smart-aa2c3d00-814c-4c33-b031-2b3dc654b27a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444361819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3444361819
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1827298859
Short name T566
Test name
Test status
Simulation time 73694843 ps
CPU time 0.93 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 197096 kb
Host smart-2f98227e-b9ed-49cf-adee-eb819235f114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827298859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1827298859
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2438450328
Short name T309
Test name
Test status
Simulation time 361084177 ps
CPU time 1.42 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:48 PM PDT 24
Peak memory 197076 kb
Host smart-e72d945e-67ce-4099-812c-064f0d7fb9b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438450328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2438450328
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3556524650
Short name T219
Test name
Test status
Simulation time 71443152 ps
CPU time 1.53 seconds
Started May 05 12:40:39 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 196796 kb
Host smart-46cfd66a-6379-468a-9492-5068225b3e5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556524650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3556524650
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4906983
Short name T602
Test name
Test status
Simulation time 2123989494 ps
CPU time 2.87 seconds
Started May 05 12:40:46 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 197952 kb
Host smart-fc8302f3-bde0-4c64-a1cc-a7d6e5f5e8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4906983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.4906983
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2592691252
Short name T426
Test name
Test status
Simulation time 38170611 ps
CPU time 0.67 seconds
Started May 05 12:40:25 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 194908 kb
Host smart-641797bb-4c41-41a7-898c-1fb44dea1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592691252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2592691252
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.556432627
Short name T651
Test name
Test status
Simulation time 375766037 ps
CPU time 1.33 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 197888 kb
Host smart-49b5e7f6-8de7-486c-abae-35880cbf82fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556432627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.556432627
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2075603689
Short name T368
Test name
Test status
Simulation time 275349091 ps
CPU time 3.36 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 197892 kb
Host smart-faff3741-2475-42f1-9683-6ca1976cd100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075603689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2075603689
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2550923055
Short name T274
Test name
Test status
Simulation time 152269346 ps
CPU time 1.15 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 195600 kb
Host smart-c84fe6e0-ca7f-413f-a676-be4147591eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550923055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2550923055
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3332896435
Short name T455
Test name
Test status
Simulation time 1256857433 ps
CPU time 1.4 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 197064 kb
Host smart-f7b0c03d-8b31-490b-975f-b7c8fb441cb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332896435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3332896435
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3752610483
Short name T715
Test name
Test status
Simulation time 13515141814 ps
CPU time 136.77 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 198092 kb
Host smart-fda47868-e405-4c4e-badc-741f6f6df85b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752610483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3752610483
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1527098507
Short name T59
Test name
Test status
Simulation time 105043277258 ps
CPU time 674.79 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:52:13 PM PDT 24
Peak memory 198160 kb
Host smart-fcc8df57-dc84-4749-bc7b-f9dfb34fbe0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1527098507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1527098507
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4074124558
Short name T461
Test name
Test status
Simulation time 55603328 ps
CPU time 0.58 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 193864 kb
Host smart-a6c7cef4-d90c-49e2-b6f3-aee7fe3c35cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074124558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4074124558
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.363494455
Short name T371
Test name
Test status
Simulation time 184053913 ps
CPU time 0.86 seconds
Started May 05 12:40:47 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 196276 kb
Host smart-fec00467-0461-442b-8c37-a0d5ccdddd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363494455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.363494455
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3096683143
Short name T221
Test name
Test status
Simulation time 272281543 ps
CPU time 4.41 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 196128 kb
Host smart-9a0a780a-98be-43cd-a886-a607a513e19f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096683143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3096683143
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1088140234
Short name T71
Test name
Test status
Simulation time 311128594 ps
CPU time 0.91 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 196064 kb
Host smart-4191d0b4-6148-42d4-92ce-21fca5de1703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088140234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1088140234
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.106596419
Short name T410
Test name
Test status
Simulation time 531312215 ps
CPU time 1.17 seconds
Started May 05 12:40:57 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 195760 kb
Host smart-8d778a45-35e3-448d-9664-f7f3b80fddde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106596419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.106596419
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.697958404
Short name T22
Test name
Test status
Simulation time 114838348 ps
CPU time 2.78 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:37 PM PDT 24
Peak memory 197948 kb
Host smart-a112d299-8f2c-4098-8c96-56cd2251a19c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697958404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.697958404
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1038620342
Short name T345
Test name
Test status
Simulation time 76440205 ps
CPU time 1.4 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:41 PM PDT 24
Peak memory 195884 kb
Host smart-afccc03b-f890-4519-b74d-25180cbed8be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038620342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1038620342
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2314809850
Short name T272
Test name
Test status
Simulation time 24238970 ps
CPU time 0.98 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 195664 kb
Host smart-edfca838-4209-4771-ab72-89b2a59af57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314809850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2314809850
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2767036343
Short name T505
Test name
Test status
Simulation time 74468975 ps
CPU time 1.24 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 196860 kb
Host smart-8d8eba55-3e48-45ad-a007-268970c23a9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767036343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2767036343
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.257379738
Short name T489
Test name
Test status
Simulation time 30999266 ps
CPU time 1.41 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 197976 kb
Host smart-4e352157-71bb-499f-bcc8-cab893cdbeae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257379738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.257379738
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2189521047
Short name T56
Test name
Test status
Simulation time 89692448 ps
CPU time 1.37 seconds
Started May 05 12:40:40 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 196396 kb
Host smart-49d3fb3a-769a-47c0-8963-0700336bc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189521047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2189521047
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3115601419
Short name T294
Test name
Test status
Simulation time 94676734 ps
CPU time 1.22 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 196648 kb
Host smart-7ee46638-0aba-4ac6-97b9-cdff6838ca22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115601419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3115601419
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.156501700
Short name T413
Test name
Test status
Simulation time 27306833646 ps
CPU time 181.66 seconds
Started May 05 12:40:26 PM PDT 24
Finished May 05 12:43:29 PM PDT 24
Peak memory 198004 kb
Host smart-cc497c2e-f8b7-42aa-91e7-7a2c1ec0512b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156501700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.156501700
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2931608913
Short name T370
Test name
Test status
Simulation time 15820739 ps
CPU time 0.61 seconds
Started May 05 12:40:51 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 193980 kb
Host smart-56398145-03c0-4dc8-ba23-cabffd588241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931608913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2931608913
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.40567489
Short name T596
Test name
Test status
Simulation time 112751654 ps
CPU time 0.87 seconds
Started May 05 12:40:45 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 196260 kb
Host smart-9110a516-f8a1-462a-94d4-3e6765ad675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40567489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.40567489
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2190941367
Short name T574
Test name
Test status
Simulation time 2764436569 ps
CPU time 10.93 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:56 PM PDT 24
Peak memory 196776 kb
Host smart-da4e7bd6-575c-4eee-9754-502715ff581f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190941367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2190941367
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2077425992
Short name T478
Test name
Test status
Simulation time 120152019 ps
CPU time 0.79 seconds
Started May 05 12:40:46 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 196500 kb
Host smart-35f0f819-0651-4030-8fd9-3ff8c5efa273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077425992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2077425992
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2374952141
Short name T584
Test name
Test status
Simulation time 186618716 ps
CPU time 1.44 seconds
Started May 05 12:40:44 PM PDT 24
Finished May 05 12:40:46 PM PDT 24
Peak memory 196496 kb
Host smart-1cbe8a3f-16fb-4686-bcf5-69940487b653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374952141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2374952141
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2877497360
Short name T241
Test name
Test status
Simulation time 44756704 ps
CPU time 1.84 seconds
Started May 05 12:40:30 PM PDT 24
Finished May 05 12:40:33 PM PDT 24
Peak memory 198020 kb
Host smart-c597ebd7-e644-4107-aa89-7abacb8d676e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877497360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2877497360
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1794590044
Short name T126
Test name
Test status
Simulation time 66772384 ps
CPU time 1.7 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:27 PM PDT 24
Peak memory 195628 kb
Host smart-8cb33050-484c-4592-a478-2434fdb009ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794590044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1794590044
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3048866948
Short name T316
Test name
Test status
Simulation time 35994499 ps
CPU time 0.93 seconds
Started May 05 12:40:43 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 195940 kb
Host smart-2d8c6218-9601-45fa-a769-4946901d547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048866948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3048866948
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.498824725
Short name T190
Test name
Test status
Simulation time 42634469 ps
CPU time 1.03 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 196676 kb
Host smart-cbeb5b1b-19f5-4010-b19f-835b39bd94ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498824725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.498824725
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2309427158
Short name T587
Test name
Test status
Simulation time 397713633 ps
CPU time 4.79 seconds
Started May 05 12:40:53 PM PDT 24
Finished May 05 12:40:59 PM PDT 24
Peak memory 197864 kb
Host smart-7f1460ec-ef38-480b-b2b4-f8f63e705463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309427158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2309427158
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2237120061
Short name T386
Test name
Test status
Simulation time 33708080 ps
CPU time 0.97 seconds
Started May 05 12:40:42 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 196424 kb
Host smart-0cef27cc-0884-4218-8ca5-f1448319dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237120061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2237120061
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.612316645
Short name T306
Test name
Test status
Simulation time 51818163 ps
CPU time 1.11 seconds
Started May 05 12:40:25 PM PDT 24
Finished May 05 12:40:27 PM PDT 24
Peak memory 195448 kb
Host smart-8e84283c-4a9b-4fbd-b51b-93119b9464cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612316645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.612316645
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3608276639
Short name T684
Test name
Test status
Simulation time 5757107112 ps
CPU time 55.66 seconds
Started May 05 12:40:50 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 198156 kb
Host smart-c578f2ca-6a3e-4fed-a9a5-b47a55127707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608276639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3608276639
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.345468075
Short name T864
Test name
Test status
Simulation time 167362291 ps
CPU time 1.03 seconds
Started May 05 12:22:48 PM PDT 24
Finished May 05 12:22:50 PM PDT 24
Peak memory 196492 kb
Host smart-242bf9a0-0db4-4a3d-8d10-2a873a4abc50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=345468075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.345468075
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4106718147
Short name T865
Test name
Test status
Simulation time 139083716 ps
CPU time 1.17 seconds
Started May 05 12:22:07 PM PDT 24
Finished May 05 12:22:09 PM PDT 24
Peak memory 196700 kb
Host smart-0338cc84-b95f-47a1-96cf-bf30561f32da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106718147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4106718147
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.727736870
Short name T892
Test name
Test status
Simulation time 37702802 ps
CPU time 1.14 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:19 PM PDT 24
Peak memory 196644 kb
Host smart-4cb49eea-8a07-47d0-a5e9-ef8951a0ea88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=727736870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.727736870
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2911290702
Short name T873
Test name
Test status
Simulation time 238699223 ps
CPU time 1.16 seconds
Started May 05 12:19:12 PM PDT 24
Finished May 05 12:19:14 PM PDT 24
Peak memory 196596 kb
Host smart-1a921355-7b5f-4d09-bfbf-b2f77be5458a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911290702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2911290702
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2930416221
Short name T898
Test name
Test status
Simulation time 47878886 ps
CPU time 0.98 seconds
Started May 05 12:19:13 PM PDT 24
Finished May 05 12:19:14 PM PDT 24
Peak memory 198332 kb
Host smart-d25e216f-8b67-44cd-b694-8658c792f244
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2930416221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2930416221
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2440766271
Short name T843
Test name
Test status
Simulation time 59995221 ps
CPU time 1.2 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:18 PM PDT 24
Peak memory 198092 kb
Host smart-b4390578-c732-4a04-a8cf-7035e976e6d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440766271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2440766271
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.890982353
Short name T942
Test name
Test status
Simulation time 589113799 ps
CPU time 1.05 seconds
Started May 05 12:21:29 PM PDT 24
Finished May 05 12:21:30 PM PDT 24
Peak memory 196276 kb
Host smart-68c49462-7128-4c3f-9c93-6e4920316e9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=890982353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.890982353
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.612731880
Short name T901
Test name
Test status
Simulation time 60758925 ps
CPU time 1.1 seconds
Started May 05 12:19:26 PM PDT 24
Finished May 05 12:19:27 PM PDT 24
Peak memory 195972 kb
Host smart-96de9731-9423-4fe6-816c-5bc163f4ea05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612731880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.612731880
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3031670113
Short name T903
Test name
Test status
Simulation time 121681746 ps
CPU time 0.78 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:19 PM PDT 24
Peak memory 196156 kb
Host smart-e414160f-b978-4a84-b94b-ce4dfdb29083
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3031670113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3031670113
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2523729528
Short name T858
Test name
Test status
Simulation time 68610893 ps
CPU time 1.07 seconds
Started May 05 12:19:12 PM PDT 24
Finished May 05 12:19:14 PM PDT 24
Peak memory 197224 kb
Host smart-05261aee-8e56-45fd-acf7-1373fbace7f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523729528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2523729528
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2178080656
Short name T855
Test name
Test status
Simulation time 111004603 ps
CPU time 1.2 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 197604 kb
Host smart-ffd23815-b2c5-4a11-ad89-3d6975ae5ac4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2178080656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2178080656
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.871568603
Short name T883
Test name
Test status
Simulation time 337724867 ps
CPU time 1.38 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 197944 kb
Host smart-f0d22311-3c8b-4000-87f7-ee6b72fd4a97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871568603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.871568603
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4055244533
Short name T849
Test name
Test status
Simulation time 78552261 ps
CPU time 1.32 seconds
Started May 05 12:19:11 PM PDT 24
Finished May 05 12:19:13 PM PDT 24
Peak memory 198388 kb
Host smart-e63dbdb1-13a0-4d0b-8170-d8d78fe7dc3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4055244533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4055244533
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3684649186
Short name T936
Test name
Test status
Simulation time 172297678 ps
CPU time 1.34 seconds
Started May 05 12:20:27 PM PDT 24
Finished May 05 12:20:29 PM PDT 24
Peak memory 196968 kb
Host smart-677fb50c-59c0-42f8-b26c-f36f7215878d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684649186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3684649186
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3878595706
Short name T844
Test name
Test status
Simulation time 204190459 ps
CPU time 1.34 seconds
Started May 05 12:19:13 PM PDT 24
Finished May 05 12:19:15 PM PDT 24
Peak memory 196672 kb
Host smart-cf72024e-44e0-4269-b355-7cdc57f802ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3878595706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3878595706
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.42493386
Short name T853
Test name
Test status
Simulation time 54888223 ps
CPU time 1.46 seconds
Started May 05 12:19:03 PM PDT 24
Finished May 05 12:19:06 PM PDT 24
Peak memory 195508 kb
Host smart-a56c9c18-a057-407f-abc4-17c84cc8c92a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.42493386
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1904201789
Short name T877
Test name
Test status
Simulation time 289282268 ps
CPU time 1.29 seconds
Started May 05 12:19:18 PM PDT 24
Finished May 05 12:19:21 PM PDT 24
Peak memory 197924 kb
Host smart-577ef515-0376-48ca-9510-e25b47128fd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1904201789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1904201789
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284629223
Short name T939
Test name
Test status
Simulation time 60506130 ps
CPU time 1 seconds
Started May 05 12:19:16 PM PDT 24
Finished May 05 12:19:18 PM PDT 24
Peak memory 196564 kb
Host smart-e47f5ff6-1057-4b5d-86d0-2c9402891aa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284629223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.284629223
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3453993895
Short name T880
Test name
Test status
Simulation time 193472415 ps
CPU time 1.21 seconds
Started May 05 12:19:16 PM PDT 24
Finished May 05 12:19:18 PM PDT 24
Peak memory 196944 kb
Host smart-b060c848-eaed-46c9-90ae-7e1549fec687
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3453993895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3453993895
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4011631927
Short name T938
Test name
Test status
Simulation time 50269549 ps
CPU time 1.35 seconds
Started May 05 12:19:11 PM PDT 24
Finished May 05 12:19:13 PM PDT 24
Peak memory 198456 kb
Host smart-eb2f95a5-d13f-4c95-afc1-1f9ec9987c16
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011631927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4011631927
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.102393029
Short name T897
Test name
Test status
Simulation time 48078054 ps
CPU time 1 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:19 PM PDT 24
Peak memory 195848 kb
Host smart-474ae0a6-16d7-4509-8302-fecda3ec5461
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=102393029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.102393029
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912367052
Short name T918
Test name
Test status
Simulation time 301839741 ps
CPU time 1.26 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:19 PM PDT 24
Peak memory 195876 kb
Host smart-01cfc483-4f36-4dde-a562-977b4ffb6f11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912367052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2912367052
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3432552338
Short name T850
Test name
Test status
Simulation time 189171722 ps
CPU time 1.41 seconds
Started May 05 12:19:18 PM PDT 24
Finished May 05 12:19:22 PM PDT 24
Peak memory 196004 kb
Host smart-3f39e1b5-35d3-4659-9ef9-6fa1fd057faa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3432552338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3432552338
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2635431790
Short name T863
Test name
Test status
Simulation time 130751090 ps
CPU time 0.85 seconds
Started May 05 12:19:14 PM PDT 24
Finished May 05 12:19:15 PM PDT 24
Peak memory 196296 kb
Host smart-d43706aa-f34c-467c-b218-a3db1e1b978e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635431790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2635431790
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1155742323
Short name T851
Test name
Test status
Simulation time 429329503 ps
CPU time 1.13 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 195984 kb
Host smart-1a117f20-878e-4842-9d13-ac04e9d8104d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1155742323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1155742323
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164901038
Short name T900
Test name
Test status
Simulation time 31421801 ps
CPU time 0.83 seconds
Started May 05 12:19:15 PM PDT 24
Finished May 05 12:19:18 PM PDT 24
Peak memory 195136 kb
Host smart-faf41863-20b5-4638-8644-70b356d12947
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164901038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2164901038
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2843545633
Short name T846
Test name
Test status
Simulation time 62897124 ps
CPU time 0.79 seconds
Started May 05 12:19:03 PM PDT 24
Finished May 05 12:19:05 PM PDT 24
Peak memory 193240 kb
Host smart-75a8f27a-6435-4d03-925a-1d800362aa7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2843545633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2843545633
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1033470876
Short name T875
Test name
Test status
Simulation time 197309811 ps
CPU time 0.95 seconds
Started May 05 12:19:18 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 195412 kb
Host smart-ff0edae0-7231-4754-8fb4-90ce6f722301
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033470876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1033470876
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3172728365
Short name T866
Test name
Test status
Simulation time 255646555 ps
CPU time 1.41 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 196664 kb
Host smart-e6079af5-14a9-40da-9e90-f43058dedf4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3172728365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3172728365
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3170083425
Short name T862
Test name
Test status
Simulation time 58214005 ps
CPU time 1.15 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:12 PM PDT 24
Peak memory 196348 kb
Host smart-c70ff1c9-69fc-4778-80b5-f5fd90c26b38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170083425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3170083425
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.76691889
Short name T923
Test name
Test status
Simulation time 271888450 ps
CPU time 1.37 seconds
Started May 05 12:21:55 PM PDT 24
Finished May 05 12:21:56 PM PDT 24
Peak memory 196828 kb
Host smart-d07a74bb-4c8d-4819-83a7-7d2b29a13f43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=76691889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.76691889
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833124056
Short name T867
Test name
Test status
Simulation time 69899667 ps
CPU time 1.26 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 196324 kb
Host smart-74f9dd4a-7121-4fc0-85a0-f20138fbd251
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833124056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.833124056
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2884664142
Short name T930
Test name
Test status
Simulation time 770694858 ps
CPU time 1.31 seconds
Started May 05 12:20:23 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195464 kb
Host smart-6f2a17be-8381-4796-8655-17d17f5b4df1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2884664142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2884664142
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520860520
Short name T879
Test name
Test status
Simulation time 46710080 ps
CPU time 1.6 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195468 kb
Host smart-a5695b6c-06fc-4d6c-b5fa-048fc575714e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520860520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2520860520
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3078390794
Short name T916
Test name
Test status
Simulation time 84287449 ps
CPU time 1.08 seconds
Started May 05 12:20:24 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 197816 kb
Host smart-3493387f-ad43-44f8-9625-d83e3c81a9dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3078390794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3078390794
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926657546
Short name T886
Test name
Test status
Simulation time 152927227 ps
CPU time 1.22 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 195816 kb
Host smart-deadad71-8b00-44f2-a91b-055a37968a3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926657546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.926657546
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.202309061
Short name T908
Test name
Test status
Simulation time 226919525 ps
CPU time 1.34 seconds
Started May 05 12:25:08 PM PDT 24
Finished May 05 12:25:12 PM PDT 24
Peak memory 196732 kb
Host smart-3ee032ee-fc18-436d-b905-12e655ac4627
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=202309061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.202309061
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045603125
Short name T881
Test name
Test status
Simulation time 352521180 ps
CPU time 1.38 seconds
Started May 05 12:19:56 PM PDT 24
Finished May 05 12:19:58 PM PDT 24
Peak memory 196960 kb
Host smart-66fab938-c030-4ae8-9ca9-b5f0c07b3cea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045603125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2045603125
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3057861843
Short name T920
Test name
Test status
Simulation time 99772198 ps
CPU time 1.58 seconds
Started May 05 12:23:53 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 196636 kb
Host smart-80e96e1f-50ea-407b-af54-99f34cf001f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3057861843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3057861843
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.824223884
Short name T856
Test name
Test status
Simulation time 72203098 ps
CPU time 0.84 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:24 PM PDT 24
Peak memory 193880 kb
Host smart-386be085-25fc-48fd-b0f8-00e131906bb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824223884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.824223884
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2469374457
Short name T931
Test name
Test status
Simulation time 490485919 ps
CPU time 1.35 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 196280 kb
Host smart-b30af6d0-9daf-4707-80f1-84d5e2e821ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2469374457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2469374457
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1627410952
Short name T896
Test name
Test status
Simulation time 84356396 ps
CPU time 0.84 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 196340 kb
Host smart-0dc10f55-d30a-42cf-a7c6-8389912155c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627410952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1627410952
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1765501282
Short name T941
Test name
Test status
Simulation time 86886943 ps
CPU time 1.61 seconds
Started May 05 12:20:00 PM PDT 24
Finished May 05 12:20:02 PM PDT 24
Peak memory 197448 kb
Host smart-281fd66c-70ed-4390-a5d3-bd9f28430fd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1765501282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1765501282
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1023443140
Short name T940
Test name
Test status
Simulation time 73943506 ps
CPU time 1.39 seconds
Started May 05 12:20:23 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195340 kb
Host smart-2d3d16b6-6330-4427-9f3d-9c02838c9007
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023443140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1023443140
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3103834954
Short name T919
Test name
Test status
Simulation time 70322758 ps
CPU time 1.1 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:24:54 PM PDT 24
Peak memory 196704 kb
Host smart-7b82e027-73ea-488b-a24f-d06d778d0e84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3103834954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3103834954
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3572132796
Short name T871
Test name
Test status
Simulation time 75452821 ps
CPU time 0.93 seconds
Started May 05 12:21:58 PM PDT 24
Finished May 05 12:22:00 PM PDT 24
Peak memory 196676 kb
Host smart-6dd87f90-0d1d-4a51-89d1-c68c672b6fb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572132796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3572132796
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.325417743
Short name T860
Test name
Test status
Simulation time 51851488 ps
CPU time 0.86 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:19 PM PDT 24
Peak memory 195760 kb
Host smart-9bfaafa4-ebf1-441b-85e1-f641441fd371
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=325417743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.325417743
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4282094221
Short name T894
Test name
Test status
Simulation time 231334094 ps
CPU time 1.26 seconds
Started May 05 12:19:12 PM PDT 24
Finished May 05 12:19:14 PM PDT 24
Peak memory 195356 kb
Host smart-b4d2dc5c-cafe-4537-bedc-f9177568a363
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282094221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4282094221
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.244596412
Short name T924
Test name
Test status
Simulation time 68371476 ps
CPU time 1.13 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 195060 kb
Host smart-12c5ef16-7f78-41c1-a0a9-2d1829fe8954
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=244596412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.244596412
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3823460281
Short name T889
Test name
Test status
Simulation time 77934675 ps
CPU time 1.04 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 193932 kb
Host smart-6e324115-44c2-42c3-af12-7b0b12481689
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823460281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3823460281
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1919899095
Short name T902
Test name
Test status
Simulation time 74151781 ps
CPU time 1.37 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 193940 kb
Host smart-4e55a518-bafa-4f80-b50c-8ae0cfaa2b2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1919899095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1919899095
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2676568740
Short name T882
Test name
Test status
Simulation time 282166098 ps
CPU time 1.24 seconds
Started May 05 12:20:02 PM PDT 24
Finished May 05 12:20:04 PM PDT 24
Peak memory 196800 kb
Host smart-e33f24de-0539-4fa2-9dc6-1d230ecb4499
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676568740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2676568740
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.386099728
Short name T861
Test name
Test status
Simulation time 80221125 ps
CPU time 1.35 seconds
Started May 05 12:19:55 PM PDT 24
Finished May 05 12:19:57 PM PDT 24
Peak memory 197272 kb
Host smart-18834192-68d0-41ca-b52e-4cd182c39310
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=386099728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.386099728
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1044568716
Short name T891
Test name
Test status
Simulation time 93255189 ps
CPU time 1.04 seconds
Started May 05 12:20:46 PM PDT 24
Finished May 05 12:20:48 PM PDT 24
Peak memory 197084 kb
Host smart-a50f7a0e-c81a-490b-820c-2a2337142459
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044568716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1044568716
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3868892282
Short name T913
Test name
Test status
Simulation time 119241040 ps
CPU time 1.05 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 195464 kb
Host smart-3ff6fbbc-13d8-4df1-a755-51feb7ea132a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3868892282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3868892282
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269711478
Short name T885
Test name
Test status
Simulation time 94153089 ps
CPU time 1.4 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 195584 kb
Host smart-1ca98748-a82e-44fb-bbe7-6de0f95a367c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269711478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3269711478
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4076442018
Short name T854
Test name
Test status
Simulation time 95433420 ps
CPU time 1.47 seconds
Started May 05 12:21:28 PM PDT 24
Finished May 05 12:21:30 PM PDT 24
Peak memory 196740 kb
Host smart-cdde4109-4477-4d70-83c4-2e3b00b99a0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4076442018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4076442018
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.428502688
Short name T859
Test name
Test status
Simulation time 284479017 ps
CPU time 1.14 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 195624 kb
Host smart-639f5681-56fa-480e-bc7c-a69b5520db63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428502688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.428502688
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.387641576
Short name T910
Test name
Test status
Simulation time 221148433 ps
CPU time 1.25 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 194120 kb
Host smart-d4060893-66d9-4ed2-beb6-ddf57edebdb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=387641576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.387641576
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1125665381
Short name T907
Test name
Test status
Simulation time 67774732 ps
CPU time 1.27 seconds
Started May 05 12:20:23 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195284 kb
Host smart-10f4a4cf-4814-42e5-8072-5056cdc1b051
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125665381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1125665381
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.597227277
Short name T872
Test name
Test status
Simulation time 216217056 ps
CPU time 1.22 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:56 PM PDT 24
Peak memory 196508 kb
Host smart-7476f75d-65d5-4dfc-baf3-8b8f0de80e34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=597227277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.597227277
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80701998
Short name T847
Test name
Test status
Simulation time 64867948 ps
CPU time 0.79 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 195140 kb
Host smart-0aeb29b3-ee2d-4850-ac93-a9f5dfec0eca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80701998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.80701998
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.293354392
Short name T876
Test name
Test status
Simulation time 1000840477 ps
CPU time 1.52 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 197788 kb
Host smart-ee16abc4-c645-41e3-b359-e0ca29645437
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=293354392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.293354392
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1936882231
Short name T911
Test name
Test status
Simulation time 76184654 ps
CPU time 1.27 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:51 PM PDT 24
Peak memory 197732 kb
Host smart-f9cd5207-b3d0-4c2a-a63f-193962db1038
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936882231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1936882231
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.435494532
Short name T887
Test name
Test status
Simulation time 49040830 ps
CPU time 1.2 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 196616 kb
Host smart-f5ac9388-ed03-4184-9d99-7faefb53ca04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=435494532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.435494532
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064085886
Short name T932
Test name
Test status
Simulation time 257929830 ps
CPU time 0.93 seconds
Started May 05 12:22:24 PM PDT 24
Finished May 05 12:22:26 PM PDT 24
Peak memory 195784 kb
Host smart-f7026fba-e41d-44be-9fb0-1c3787294a8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064085886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3064085886
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3008953703
Short name T890
Test name
Test status
Simulation time 64668475 ps
CPU time 1.28 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195124 kb
Host smart-4464b741-ea4a-441e-bbc5-73ea83be5fcd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3008953703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3008953703
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.72238066
Short name T868
Test name
Test status
Simulation time 145998309 ps
CPU time 1.14 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 194304 kb
Host smart-de86d8e9-bd16-4d40-8204-f964076ad8f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72238066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.72238066
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3511223015
Short name T878
Test name
Test status
Simulation time 42215001 ps
CPU time 0.9 seconds
Started May 05 12:19:14 PM PDT 24
Finished May 05 12:19:16 PM PDT 24
Peak memory 196920 kb
Host smart-ab86a774-9d1c-422b-bf33-543d26d7a357
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3511223015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3511223015
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2038511752
Short name T927
Test name
Test status
Simulation time 71246678 ps
CPU time 1.08 seconds
Started May 05 12:19:33 PM PDT 24
Finished May 05 12:19:35 PM PDT 24
Peak memory 196720 kb
Host smart-4cec6b16-9845-4944-978e-099f99984b9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038511752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2038511752
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1753511706
Short name T915
Test name
Test status
Simulation time 267703476 ps
CPU time 1.34 seconds
Started May 05 12:20:23 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195340 kb
Host smart-6aa177a1-7407-479d-b749-93ce6af8ba16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1753511706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1753511706
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2430329796
Short name T928
Test name
Test status
Simulation time 104445779 ps
CPU time 1.09 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:23:55 PM PDT 24
Peak memory 197816 kb
Host smart-c9112388-b580-4d70-8c1c-0945e34183a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430329796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2430329796
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2119438289
Short name T912
Test name
Test status
Simulation time 53789780 ps
CPU time 1.2 seconds
Started May 05 12:21:10 PM PDT 24
Finished May 05 12:21:12 PM PDT 24
Peak memory 198104 kb
Host smart-e3a63ab9-9656-407b-ba83-d65fca63cc8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2119438289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2119438289
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2323803959
Short name T921
Test name
Test status
Simulation time 22731700 ps
CPU time 0.72 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 195192 kb
Host smart-734908ab-0dc5-49d4-abc8-28106d3cc4dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323803959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2323803959
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2164725818
Short name T845
Test name
Test status
Simulation time 96941723 ps
CPU time 1.78 seconds
Started May 05 12:20:22 PM PDT 24
Finished May 05 12:20:25 PM PDT 24
Peak memory 195776 kb
Host smart-aea6a41f-b20e-4929-8e8f-26cc1377019d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2164725818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2164725818
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4150403623
Short name T925
Test name
Test status
Simulation time 52972136 ps
CPU time 1.16 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:03 PM PDT 24
Peak memory 196576 kb
Host smart-372452ae-1ccd-453c-b454-e7f40d6522fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150403623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4150403623
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3453012972
Short name T874
Test name
Test status
Simulation time 67743475 ps
CPU time 0.87 seconds
Started May 05 12:20:03 PM PDT 24
Finished May 05 12:20:05 PM PDT 24
Peak memory 195748 kb
Host smart-329450bd-a6d2-46bf-9299-ff765a67614c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3453012972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3453012972
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.347962226
Short name T926
Test name
Test status
Simulation time 254960716 ps
CPU time 1.17 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 195236 kb
Host smart-55321be5-5235-4e5e-bdee-4d804adee4e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347962226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.347962226
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4200483032
Short name T935
Test name
Test status
Simulation time 166941333 ps
CPU time 1.04 seconds
Started May 05 12:24:49 PM PDT 24
Finished May 05 12:24:53 PM PDT 24
Peak memory 196404 kb
Host smart-73968d46-2213-4c67-b20b-60931cad0983
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4200483032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4200483032
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1788767740
Short name T906
Test name
Test status
Simulation time 42337517 ps
CPU time 1.16 seconds
Started May 05 12:22:46 PM PDT 24
Finished May 05 12:22:47 PM PDT 24
Peak memory 196636 kb
Host smart-778eff2b-853d-43ea-af0c-16b1d66d408b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788767740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1788767740
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1441595634
Short name T869
Test name
Test status
Simulation time 61561002 ps
CPU time 1.18 seconds
Started May 05 12:22:10 PM PDT 24
Finished May 05 12:22:11 PM PDT 24
Peak memory 196812 kb
Host smart-4e747884-ab35-45a7-9e41-9c977105e214
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1441595634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1441595634
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.33145517
Short name T884
Test name
Test status
Simulation time 142572929 ps
CPU time 0.86 seconds
Started May 05 12:20:41 PM PDT 24
Finished May 05 12:20:42 PM PDT 24
Peak memory 196236 kb
Host smart-cc41f5d8-7351-41ce-a834-9e8a39293f7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.33145517
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1273477511
Short name T929
Test name
Test status
Simulation time 88093880 ps
CPU time 1.23 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:51 PM PDT 24
Peak memory 196080 kb
Host smart-e46285fd-ab0a-4bee-8cd9-83af50f84dc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1273477511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1273477511
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.932581152
Short name T888
Test name
Test status
Simulation time 57195187 ps
CPU time 0.9 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:07 PM PDT 24
Peak memory 193820 kb
Host smart-c9e7a4c5-62a0-4e85-9359-7dd67673fb20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932581152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.932581152
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.259778986
Short name T937
Test name
Test status
Simulation time 42175473 ps
CPU time 1.18 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:17 PM PDT 24
Peak memory 196852 kb
Host smart-d709de03-96d7-4d35-8556-c7499ac61dc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=259778986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.259778986
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577975707
Short name T904
Test name
Test status
Simulation time 124837650 ps
CPU time 1.25 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 195464 kb
Host smart-b6b99387-a72f-4882-9bdb-6c8eaa034bcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577975707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3577975707
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2966020002
Short name T852
Test name
Test status
Simulation time 58119382 ps
CPU time 1.07 seconds
Started May 05 12:23:53 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 195668 kb
Host smart-a44f42e1-e34b-4c82-af02-fcdb74c463c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2966020002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2966020002
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811159226
Short name T934
Test name
Test status
Simulation time 366284195 ps
CPU time 1.06 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 195976 kb
Host smart-a4aebd93-1f29-4b23-b4ac-881063aa84d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811159226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1811159226
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2894306323
Short name T857
Test name
Test status
Simulation time 34684909 ps
CPU time 0.85 seconds
Started May 05 12:25:05 PM PDT 24
Finished May 05 12:25:08 PM PDT 24
Peak memory 197468 kb
Host smart-e87091be-a061-406e-bde1-26b6ecebbeb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2894306323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2894306323
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1384305368
Short name T893
Test name
Test status
Simulation time 47979061 ps
CPU time 1.25 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 196696 kb
Host smart-edc12ce3-92da-4855-b007-24cbb86a5755
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384305368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1384305368
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4220445414
Short name T905
Test name
Test status
Simulation time 211484163 ps
CPU time 1.04 seconds
Started May 05 12:19:12 PM PDT 24
Finished May 05 12:19:14 PM PDT 24
Peak memory 197772 kb
Host smart-12b5aa3f-5d19-4c8e-83f8-d4d1d7227a73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4220445414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4220445414
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2027472885
Short name T933
Test name
Test status
Simulation time 393939675 ps
CPU time 1.22 seconds
Started May 05 12:21:58 PM PDT 24
Finished May 05 12:22:00 PM PDT 24
Peak memory 198080 kb
Host smart-e2296340-dbec-4a17-9f0a-cbe8a543596c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027472885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2027472885
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2610837323
Short name T899
Test name
Test status
Simulation time 287221174 ps
CPU time 1.17 seconds
Started May 05 12:19:17 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 196524 kb
Host smart-3b8df579-55ad-4462-96ac-3c5702f28f19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2610837323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2610837323
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3722848331
Short name T922
Test name
Test status
Simulation time 81445070 ps
CPU time 0.71 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:24:54 PM PDT 24
Peak memory 195548 kb
Host smart-6ae4eabf-db40-4636-bac0-d425000ad0a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722848331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3722848331
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.957012601
Short name T914
Test name
Test status
Simulation time 187836901 ps
CPU time 1.23 seconds
Started May 05 12:21:57 PM PDT 24
Finished May 05 12:21:58 PM PDT 24
Peak memory 196516 kb
Host smart-f81c448b-a00b-4ed0-91ea-a2581b8fa1bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=957012601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.957012601
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4226402761
Short name T909
Test name
Test status
Simulation time 57406650 ps
CPU time 0.97 seconds
Started May 05 12:19:26 PM PDT 24
Finished May 05 12:19:27 PM PDT 24
Peak memory 196592 kb
Host smart-ca1318db-6ace-4595-afd7-c0d3902dcd05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226402761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4226402761
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1117577491
Short name T870
Test name
Test status
Simulation time 143633684 ps
CPU time 1.07 seconds
Started May 05 12:23:30 PM PDT 24
Finished May 05 12:23:32 PM PDT 24
Peak memory 196076 kb
Host smart-aec2063b-c34c-4a7e-b33e-b303314069cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1117577491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1117577491
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1138095465
Short name T917
Test name
Test status
Simulation time 83855839 ps
CPU time 0.85 seconds
Started May 05 12:19:12 PM PDT 24
Finished May 05 12:19:13 PM PDT 24
Peak memory 194148 kb
Host smart-bf62f4be-f4e3-4494-a658-51b63e5c64c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138095465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1138095465
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1650262538
Short name T895
Test name
Test status
Simulation time 117650147 ps
CPU time 1.06 seconds
Started May 05 12:19:18 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 196940 kb
Host smart-3a57330d-f597-4737-afc5-97cc210e28d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1650262538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1650262538
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716846928
Short name T848
Test name
Test status
Simulation time 32653921 ps
CPU time 1.02 seconds
Started May 05 12:19:14 PM PDT 24
Finished May 05 12:19:15 PM PDT 24
Peak memory 196492 kb
Host smart-b7a4053c-0731-4e2c-a5e6-c8f5d67a247b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716846928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2716846928
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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