cp_pins | cp_stable_cycles | cp_pin_value | cp_filter_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59261 |
1 |
|
|
T12 |
527 |
|
T102 |
1481 |
|
T103 |
2202 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[1] |
50076 |
1 |
|
|
T12 |
2158 |
|
T102 |
82 |
|
T103 |
739 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57876 |
1 |
|
|
T12 |
951 |
|
T102 |
205 |
|
T103 |
1791 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46561 |
1 |
|
|
T12 |
1006 |
|
T102 |
150 |
|
T103 |
2020 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
10 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1742 |
1 |
|
|
T12 |
53 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1725 |
1 |
|
|
T12 |
51 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
10 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1713 |
1 |
|
|
T12 |
51 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1697 |
1 |
|
|
T12 |
50 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
10 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1684 |
1 |
|
|
T12 |
51 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
772 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1666 |
1 |
|
|
T12 |
48 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
10 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1649 |
1 |
|
|
T12 |
51 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
772 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1636 |
1 |
|
|
T12 |
46 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
9 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1609 |
1 |
|
|
T12 |
52 |
|
T102 |
3 |
|
T103 |
34 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1602 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
9 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T12 |
52 |
|
T102 |
3 |
|
T103 |
34 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T12 |
42 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
9 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1547 |
1 |
|
|
T12 |
51 |
|
T102 |
3 |
|
T103 |
34 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
764 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T12 |
42 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
9 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1516 |
1 |
|
|
T12 |
50 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
764 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1495 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1476 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1465 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1432 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1410 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
26 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1404 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1384 |
1 |
|
|
T12 |
44 |
|
T102 |
3 |
|
T103 |
26 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1377 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1332 |
1 |
|
|
T12 |
42 |
|
T102 |
3 |
|
T103 |
24 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1345 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1298 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
24 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1312 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
9 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1262 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
36 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1272 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[0] |
60540 |
1 |
|
|
T12 |
2173 |
|
T102 |
91 |
|
T103 |
1345 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48327 |
1 |
|
|
T12 |
720 |
|
T102 |
1377 |
|
T103 |
1339 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[0] |
61933 |
1 |
|
|
T12 |
1234 |
|
T102 |
182 |
|
T103 |
2726 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43264 |
1 |
|
|
T12 |
746 |
|
T102 |
136 |
|
T103 |
1228 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1741 |
1 |
|
|
T12 |
29 |
|
T102 |
10 |
|
T103 |
65 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1708 |
1 |
|
|
T12 |
34 |
|
T102 |
10 |
|
T103 |
60 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1712 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
64 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1664 |
1 |
|
|
T12 |
33 |
|
T102 |
10 |
|
T103 |
59 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T12 |
28 |
|
T102 |
8 |
|
T103 |
63 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1635 |
1 |
|
|
T12 |
33 |
|
T102 |
10 |
|
T103 |
58 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1649 |
1 |
|
|
T12 |
28 |
|
T102 |
7 |
|
T103 |
60 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1603 |
1 |
|
|
T12 |
33 |
|
T102 |
10 |
|
T103 |
57 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1618 |
1 |
|
|
T12 |
26 |
|
T102 |
7 |
|
T103 |
60 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
784 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1577 |
1 |
|
|
T12 |
33 |
|
T102 |
10 |
|
T103 |
56 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
17 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1578 |
1 |
|
|
T12 |
25 |
|
T102 |
7 |
|
T103 |
58 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
784 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1544 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
56 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1535 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
56 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
778 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
55 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1496 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
56 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
778 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1490 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
54 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T12 |
24 |
|
T102 |
5 |
|
T103 |
55 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1460 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
54 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1420 |
1 |
|
|
T12 |
24 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
54 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1383 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
51 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1345 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1350 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
50 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1312 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
48 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
48 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1284 |
1 |
|
|
T12 |
19 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1284 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
47 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
16 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T12 |
19 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
773 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
22 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1240 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59807 |
1 |
|
|
T12 |
954 |
|
T102 |
182 |
|
T103 |
2813 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47015 |
1 |
|
|
T12 |
1915 |
|
T102 |
1397 |
|
T103 |
1521 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[0] |
61657 |
1 |
|
|
T12 |
1205 |
|
T102 |
91 |
|
T103 |
1054 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46793 |
1 |
|
|
T12 |
739 |
|
T102 |
193 |
|
T103 |
1243 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
19 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1696 |
1 |
|
|
T12 |
36 |
|
T102 |
7 |
|
T103 |
61 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1712 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
63 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
19 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T12 |
36 |
|
T102 |
7 |
|
T103 |
58 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1673 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
752 |
1 |
|
|
T12 |
19 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1639 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
57 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T12 |
33 |
|
T102 |
6 |
|
T103 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
752 |
1 |
|
|
T12 |
19 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1606 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
55 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
61 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
747 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T12 |
32 |
|
T102 |
7 |
|
T103 |
52 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1588 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
60 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
747 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
51 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T12 |
31 |
|
T102 |
6 |
|
T103 |
60 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1499 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1517 |
1 |
|
|
T12 |
30 |
|
T102 |
6 |
|
T103 |
59 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1460 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1490 |
1 |
|
|
T12 |
30 |
|
T102 |
6 |
|
T103 |
57 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1428 |
1 |
|
|
T12 |
30 |
|
T102 |
6 |
|
T103 |
46 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
56 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1389 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1425 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
55 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1352 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
43 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1395 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
54 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1369 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
40 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1346 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T12 |
26 |
|
T102 |
6 |
|
T103 |
39 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1311 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
38 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1280 |
1 |
|
|
T12 |
26 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58763 |
1 |
|
|
T12 |
833 |
|
T102 |
155 |
|
T103 |
2912 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48529 |
1 |
|
|
T12 |
805 |
|
T102 |
170 |
|
T103 |
972 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[0] |
62455 |
1 |
|
|
T12 |
2133 |
|
T102 |
156 |
|
T103 |
1438 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44856 |
1 |
|
|
T12 |
925 |
|
T102 |
1318 |
|
T103 |
1377 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1725 |
1 |
|
|
T12 |
44 |
|
T102 |
7 |
|
T103 |
53 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1724 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
58 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1694 |
1 |
|
|
T12 |
44 |
|
T102 |
7 |
|
T103 |
53 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1695 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
58 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1673 |
1 |
|
|
T12 |
43 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1654 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
56 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T12 |
41 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1611 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
54 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1609 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1587 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1578 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
50 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1557 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
49 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T12 |
36 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T12 |
15 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1516 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
47 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1493 |
1 |
|
|
T12 |
35 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1485 |
1 |
|
|
T12 |
36 |
|
T102 |
6 |
|
T103 |
45 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1458 |
1 |
|
|
T12 |
35 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
45 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1432 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1416 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1397 |
1 |
|
|
T12 |
33 |
|
T102 |
5 |
|
T103 |
49 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1384 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1364 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
48 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1347 |
1 |
|
|
T12 |
33 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
46 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1312 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
39 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1282 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
44 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
25 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
39 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T12 |
19 |
|
T102 |
6 |
|
T103 |
20 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1247 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
44 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57632 |
1 |
|
|
T12 |
882 |
|
T102 |
194 |
|
T103 |
1764 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49786 |
1 |
|
|
T12 |
1003 |
|
T102 |
1341 |
|
T103 |
2060 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57135 |
1 |
|
|
T12 |
2098 |
|
T102 |
261 |
|
T103 |
2043 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48569 |
1 |
|
|
T12 |
798 |
|
T102 |
34 |
|
T103 |
1093 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
14 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1802 |
1 |
|
|
T12 |
42 |
|
T102 |
5 |
|
T103 |
38 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1792 |
1 |
|
|
T12 |
45 |
|
T102 |
5 |
|
T103 |
42 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
14 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1765 |
1 |
|
|
T12 |
42 |
|
T102 |
5 |
|
T103 |
37 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1759 |
1 |
|
|
T12 |
44 |
|
T102 |
4 |
|
T103 |
42 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
14 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1731 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1716 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
41 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
741 |
1 |
|
|
T12 |
14 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1696 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1676 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
40 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1660 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
40 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1635 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
34 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1622 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
40 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
31 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
740 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1579 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
39 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1547 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
740 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1546 |
1 |
|
|
T12 |
36 |
|
T102 |
3 |
|
T103 |
39 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
28 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1505 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1475 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
28 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1469 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
38 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1438 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1439 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1404 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1402 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1371 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T12 |
32 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1337 |
1 |
|
|
T12 |
36 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
30 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1300 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1294 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58696 |
1 |
|
|
T12 |
952 |
|
T102 |
413 |
|
T103 |
1852 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47865 |
1 |
|
|
T12 |
569 |
|
T102 |
43 |
|
T103 |
2224 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55707 |
1 |
|
|
T12 |
1128 |
|
T102 |
1467 |
|
T103 |
1676 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[1] |
50527 |
1 |
|
|
T12 |
2280 |
|
T102 |
10 |
|
T103 |
1008 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1797 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
52 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1795 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1752 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1758 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1710 |
1 |
|
|
T12 |
28 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1726 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1684 |
1 |
|
|
T12 |
26 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1689 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T12 |
25 |
|
T102 |
1 |
|
T103 |
48 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1656 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1634 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1567 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
45 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1613 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
38 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1534 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1539 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1463 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1512 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
35 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
42 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1483 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
35 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1394 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1451 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
34 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1350 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1421 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
34 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1309 |
1 |
|
|
T12 |
21 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1388 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
33 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1268 |
1 |
|
|
T12 |
21 |
|
T102 |
1 |
|
T103 |
38 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
32 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1363 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
33 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58813 |
1 |
|
|
T12 |
1294 |
|
T102 |
1396 |
|
T103 |
1169 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48431 |
1 |
|
|
T12 |
600 |
|
T102 |
67 |
|
T103 |
1328 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55002 |
1 |
|
|
T12 |
882 |
|
T102 |
416 |
|
T103 |
2810 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[1] |
51509 |
1 |
|
|
T12 |
2166 |
|
T102 |
21 |
|
T103 |
1226 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1775 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
63 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1769 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
60 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1736 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
62 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1734 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
58 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1703 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
62 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1715 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
58 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1683 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
58 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
60 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1655 |
1 |
|
|
T12 |
36 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
59 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1622 |
1 |
|
|
T12 |
35 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1570 |
1 |
|
|
T12 |
29 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1599 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
52 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T12 |
14 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T12 |
29 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1563 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1495 |
1 |
|
|
T12 |
28 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1450 |
1 |
|
|
T12 |
27 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1489 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T12 |
26 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
48 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1379 |
1 |
|
|
T12 |
26 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1414 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
48 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1342 |
1 |
|
|
T12 |
25 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1303 |
1 |
|
|
T12 |
25 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1343 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
13 |
|
T102 |
5 |
|
T103 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1265 |
1 |
|
|
T12 |
25 |
|
T102 |
3 |
|
T103 |
50 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
13 |
|
T102 |
4 |
|
T103 |
25 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1310 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58650 |
1 |
|
|
T12 |
1145 |
|
T102 |
161 |
|
T103 |
1887 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[1] |
52004 |
1 |
|
|
T12 |
2059 |
|
T102 |
125 |
|
T103 |
2129 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54854 |
1 |
|
|
T12 |
724 |
|
T102 |
146 |
|
T103 |
1749 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48156 |
1 |
|
|
T12 |
877 |
|
T102 |
1380 |
|
T103 |
1090 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1776 |
1 |
|
|
T12 |
44 |
|
T102 |
5 |
|
T103 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1781 |
1 |
|
|
T12 |
44 |
|
T102 |
7 |
|
T103 |
52 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1734 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1739 |
1 |
|
|
T12 |
42 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1696 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
41 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1703 |
1 |
|
|
T12 |
41 |
|
T102 |
6 |
|
T103 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1672 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1669 |
1 |
|
|
T12 |
41 |
|
T102 |
6 |
|
T103 |
49 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
39 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1643 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
743 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1592 |
1 |
|
|
T12 |
37 |
|
T102 |
5 |
|
T103 |
39 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1603 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T12 |
36 |
|
T102 |
5 |
|
T103 |
39 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1574 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
45 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T12 |
36 |
|
T102 |
5 |
|
T103 |
39 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1538 |
1 |
|
|
T12 |
39 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
37 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1502 |
1 |
|
|
T12 |
37 |
|
T102 |
5 |
|
T103 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1467 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1469 |
1 |
|
|
T12 |
37 |
|
T102 |
5 |
|
T103 |
41 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
733 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1431 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
733 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1404 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
34 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1398 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
733 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1374 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
33 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1356 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
733 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1336 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
33 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1311 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
38 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
733 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
29 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1303 |
1 |
|
|
T12 |
29 |
|
T102 |
4 |
|
T103 |
32 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
12 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1287 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
38 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[0] |
64209 |
1 |
|
|
T12 |
804 |
|
T102 |
165 |
|
T103 |
2775 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47160 |
1 |
|
|
T12 |
908 |
|
T102 |
204 |
|
T103 |
1040 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56056 |
1 |
|
|
T12 |
1011 |
|
T102 |
45 |
|
T103 |
1672 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46346 |
1 |
|
|
T12 |
2167 |
|
T102 |
1391 |
|
T103 |
1237 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
752 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1754 |
1 |
|
|
T12 |
41 |
|
T102 |
8 |
|
T103 |
46 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1767 |
1 |
|
|
T12 |
38 |
|
T102 |
8 |
|
T103 |
48 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
752 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1713 |
1 |
|
|
T12 |
41 |
|
T102 |
8 |
|
T103 |
43 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1735 |
1 |
|
|
T12 |
38 |
|
T102 |
8 |
|
T103 |
48 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
747 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T12 |
40 |
|
T102 |
8 |
|
T103 |
43 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1699 |
1 |
|
|
T12 |
38 |
|
T102 |
8 |
|
T103 |
48 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
747 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1661 |
1 |
|
|
T12 |
40 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1672 |
1 |
|
|
T12 |
38 |
|
T102 |
8 |
|
T103 |
46 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1629 |
1 |
|
|
T12 |
37 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1639 |
1 |
|
|
T12 |
36 |
|
T102 |
8 |
|
T103 |
45 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
742 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T12 |
37 |
|
T102 |
8 |
|
T103 |
38 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1601 |
1 |
|
|
T12 |
35 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T12 |
35 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1566 |
1 |
|
|
T12 |
35 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T12 |
11 |
|
T102 |
3 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1538 |
1 |
|
|
T12 |
34 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1533 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1510 |
1 |
|
|
T12 |
32 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1498 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1463 |
1 |
|
|
T12 |
32 |
|
T102 |
8 |
|
T103 |
35 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1467 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
43 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T12 |
31 |
|
T102 |
8 |
|
T103 |
34 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1432 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1396 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T12 |
30 |
|
T102 |
6 |
|
T103 |
41 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1355 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T12 |
28 |
|
T102 |
6 |
|
T103 |
39 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1316 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
37 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
11 |
|
T102 |
2 |
|
T103 |
32 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1281 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
31 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1287 |
1 |
|
|
T12 |
26 |
|
T102 |
5 |
|
T103 |
36 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[0] |
69294 |
1 |
|
|
T12 |
2242 |
|
T102 |
78 |
|
T103 |
1923 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45060 |
1 |
|
|
T12 |
1084 |
|
T102 |
181 |
|
T103 |
1150 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54101 |
1 |
|
|
T12 |
527 |
|
T102 |
43 |
|
T103 |
1597 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44941 |
1 |
|
|
T12 |
898 |
|
T102 |
1468 |
|
T103 |
1996 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1744 |
1 |
|
|
T12 |
41 |
|
T102 |
11 |
|
T103 |
53 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1764 |
1 |
|
|
T12 |
42 |
|
T102 |
13 |
|
T103 |
60 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1709 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
52 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1728 |
1 |
|
|
T12 |
42 |
|
T102 |
12 |
|
T103 |
59 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
51 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1695 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
57 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1663 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
54 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1629 |
1 |
|
|
T12 |
41 |
|
T102 |
10 |
|
T103 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1643 |
1 |
|
|
T12 |
40 |
|
T102 |
10 |
|
T103 |
53 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
28 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1592 |
1 |
|
|
T12 |
40 |
|
T102 |
10 |
|
T103 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1600 |
1 |
|
|
T12 |
37 |
|
T102 |
10 |
|
T103 |
53 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1558 |
1 |
|
|
T12 |
39 |
|
T102 |
10 |
|
T103 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1567 |
1 |
|
|
T12 |
37 |
|
T102 |
10 |
|
T103 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T12 |
37 |
|
T102 |
10 |
|
T103 |
49 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T12 |
36 |
|
T102 |
10 |
|
T103 |
48 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
756 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1495 |
1 |
|
|
T12 |
36 |
|
T102 |
10 |
|
T103 |
48 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1478 |
1 |
|
|
T12 |
34 |
|
T102 |
9 |
|
T103 |
46 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
756 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1465 |
1 |
|
|
T12 |
36 |
|
T102 |
9 |
|
T103 |
47 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1447 |
1 |
|
|
T12 |
34 |
|
T102 |
9 |
|
T103 |
44 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1428 |
1 |
|
|
T12 |
36 |
|
T102 |
8 |
|
T103 |
47 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T12 |
32 |
|
T102 |
8 |
|
T103 |
44 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1398 |
1 |
|
|
T12 |
36 |
|
T102 |
8 |
|
T103 |
47 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1385 |
1 |
|
|
T12 |
30 |
|
T102 |
8 |
|
T103 |
43 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T12 |
34 |
|
T102 |
8 |
|
T103 |
46 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1354 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
41 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T12 |
34 |
|
T102 |
8 |
|
T103 |
44 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1317 |
1 |
|
|
T12 |
28 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1290 |
1 |
|
|
T12 |
34 |
|
T102 |
8 |
|
T103 |
44 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
21 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1281 |
1 |
|
|
T12 |
27 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57478 |
1 |
|
|
T12 |
622 |
|
T102 |
78 |
|
T103 |
2848 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49826 |
1 |
|
|
T12 |
990 |
|
T102 |
1435 |
|
T103 |
1332 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[0] |
59024 |
1 |
|
|
T12 |
474 |
|
T102 |
73 |
|
T103 |
1481 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48424 |
1 |
|
|
T12 |
2562 |
|
T102 |
238 |
|
T103 |
1099 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1718 |
1 |
|
|
T12 |
54 |
|
T102 |
10 |
|
T103 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1718 |
1 |
|
|
T12 |
56 |
|
T102 |
9 |
|
T103 |
44 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1685 |
1 |
|
|
T12 |
52 |
|
T102 |
10 |
|
T103 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1680 |
1 |
|
|
T12 |
55 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1648 |
1 |
|
|
T12 |
51 |
|
T102 |
10 |
|
T103 |
44 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1642 |
1 |
|
|
T12 |
54 |
|
T102 |
8 |
|
T103 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1603 |
1 |
|
|
T12 |
49 |
|
T102 |
8 |
|
T103 |
44 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1603 |
1 |
|
|
T12 |
53 |
|
T102 |
8 |
|
T103 |
40 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T12 |
49 |
|
T102 |
8 |
|
T103 |
44 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1580 |
1 |
|
|
T12 |
52 |
|
T102 |
8 |
|
T103 |
38 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T12 |
49 |
|
T102 |
8 |
|
T103 |
43 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1552 |
1 |
|
|
T12 |
51 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1508 |
1 |
|
|
T12 |
49 |
|
T102 |
7 |
|
T103 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
756 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1507 |
1 |
|
|
T12 |
49 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1483 |
1 |
|
|
T12 |
47 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
756 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1474 |
1 |
|
|
T12 |
49 |
|
T102 |
8 |
|
T103 |
36 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1453 |
1 |
|
|
T12 |
45 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1440 |
1 |
|
|
T12 |
48 |
|
T102 |
8 |
|
T103 |
35 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T12 |
44 |
|
T102 |
6 |
|
T103 |
40 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1406 |
1 |
|
|
T12 |
48 |
|
T102 |
8 |
|
T103 |
34 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1378 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1367 |
1 |
|
|
T12 |
47 |
|
T102 |
8 |
|
T103 |
33 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1346 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1312 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
37 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1299 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
37 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1263 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
8 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T12 |
35 |
|
T102 |
5 |
|
T103 |
35 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
747 |
1 |
|
|
T12 |
6 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1234 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
33 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[0] |
61039 |
1 |
|
|
T12 |
1011 |
|
T102 |
382 |
|
T103 |
3094 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[1] |
50592 |
1 |
|
|
T12 |
887 |
|
T102 |
73 |
|
T103 |
988 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[0] |
59671 |
1 |
|
|
T12 |
1085 |
|
T102 |
1498 |
|
T103 |
1844 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43084 |
1 |
|
|
T12 |
1968 |
|
T102 |
16 |
|
T103 |
896 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1690 |
1 |
|
|
T12 |
33 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1701 |
1 |
|
|
T12 |
32 |
|
T102 |
2 |
|
T103 |
44 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T12 |
33 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1670 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
42 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
781 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
767 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1637 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
42 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
781 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1596 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
767 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1611 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
776 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1567 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1597 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
776 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1551 |
1 |
|
|
T12 |
26 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1520 |
1 |
|
|
T12 |
26 |
|
T102 |
2 |
|
T103 |
38 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1469 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T12 |
25 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1436 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
754 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T12 |
24 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1407 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
754 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1424 |
1 |
|
|
T12 |
23 |
|
T102 |
1 |
|
T103 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1367 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
34 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1392 |
1 |
|
|
T12 |
23 |
|
T102 |
1 |
|
T103 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1338 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
34 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T12 |
23 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1303 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T12 |
23 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
35 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
768 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T12 |
28 |
|
T102 |
1 |
|
T103 |
31 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
29 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1243 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
34 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59988 |
1 |
|
|
T12 |
1023 |
|
T102 |
197 |
|
T103 |
1318 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46890 |
1 |
|
|
T12 |
648 |
|
T102 |
1437 |
|
T103 |
1808 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[0] |
61324 |
1 |
|
|
T12 |
2299 |
|
T102 |
108 |
|
T103 |
2156 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46744 |
1 |
|
|
T12 |
863 |
|
T102 |
137 |
|
T103 |
1357 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1694 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
64 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1704 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
64 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T12 |
37 |
|
T102 |
6 |
|
T103 |
63 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1675 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
63 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1636 |
1 |
|
|
T12 |
37 |
|
T102 |
6 |
|
T103 |
63 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1647 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
61 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T12 |
37 |
|
T102 |
6 |
|
T103 |
62 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T12 |
32 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
60 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1580 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
60 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1531 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
59 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1536 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
54 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1493 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
57 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1504 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
51 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
54 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1470 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
50 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1431 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1436 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
49 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1392 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
46 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1370 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1359 |
1 |
|
|
T12 |
27 |
|
T102 |
2 |
|
T103 |
45 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1335 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1325 |
1 |
|
|
T12 |
27 |
|
T102 |
2 |
|
T103 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1307 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T12 |
26 |
|
T102 |
2 |
|
T103 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1267 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1260 |
1 |
|
|
T12 |
25 |
|
T102 |
2 |
|
T103 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
49 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T12 |
25 |
|
T102 |
2 |
|
T103 |
43 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[0] |
61211 |
1 |
|
|
T12 |
1073 |
|
T102 |
1349 |
|
T103 |
1613 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44688 |
1 |
|
|
T12 |
747 |
|
T102 |
140 |
|
T103 |
2202 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[0] |
63276 |
1 |
|
|
T12 |
1908 |
|
T102 |
305 |
|
T103 |
1595 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45091 |
1 |
|
|
T12 |
1106 |
|
T102 |
71 |
|
T103 |
1408 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
786 |
1 |
|
|
T12 |
16 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1704 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1705 |
1 |
|
|
T12 |
41 |
|
T102 |
2 |
|
T103 |
47 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
786 |
1 |
|
|
T12 |
16 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1663 |
1 |
|
|
T12 |
36 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1666 |
1 |
|
|
T12 |
41 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
16 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1622 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1643 |
1 |
|
|
T12 |
40 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
16 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1579 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1609 |
1 |
|
|
T12 |
39 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
780 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T12 |
36 |
|
T102 |
4 |
|
T103 |
42 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
784 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1589 |
1 |
|
|
T12 |
38 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
780 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
784 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1557 |
1 |
|
|
T12 |
38 |
|
T102 |
1 |
|
T103 |
45 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
775 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1487 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
776 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1524 |
1 |
|
|
T12 |
36 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
775 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1449 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
776 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T12 |
36 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1419 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
40 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T12 |
36 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1380 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
37 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T12 |
36 |
|
T102 |
1 |
|
T103 |
42 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1355 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
36 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1392 |
1 |
|
|
T12 |
35 |
|
T102 |
1 |
|
T103 |
42 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1310 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
36 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1361 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
42 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1264 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
36 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1231 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
35 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1293 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
27 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
35 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
771 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1257 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[0] |
64271 |
1 |
|
|
T12 |
2143 |
|
T102 |
290 |
|
T103 |
1523 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[1] |
41262 |
1 |
|
|
T12 |
755 |
|
T102 |
57 |
|
T103 |
1278 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[0] |
63133 |
1 |
|
|
T12 |
802 |
|
T102 |
1387 |
|
T103 |
2304 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45786 |
1 |
|
|
T12 |
908 |
|
T102 |
143 |
|
T103 |
1485 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
803 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1673 |
1 |
|
|
T12 |
52 |
|
T102 |
3 |
|
T103 |
59 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
803 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1674 |
1 |
|
|
T12 |
48 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
803 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1626 |
1 |
|
|
T12 |
52 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
803 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1644 |
1 |
|
|
T12 |
48 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
802 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1597 |
1 |
|
|
T12 |
50 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
802 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1625 |
1 |
|
|
T12 |
48 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
802 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1559 |
1 |
|
|
T12 |
49 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
802 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1590 |
1 |
|
|
T12 |
47 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1555 |
1 |
|
|
T12 |
47 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
796 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T12 |
44 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1508 |
1 |
|
|
T12 |
45 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
796 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1426 |
1 |
|
|
T12 |
43 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1468 |
1 |
|
|
T12 |
44 |
|
T102 |
3 |
|
T103 |
51 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
55 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
789 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1437 |
1 |
|
|
T12 |
42 |
|
T102 |
3 |
|
T103 |
51 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1358 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
789 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1411 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
51 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1323 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
50 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1369 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
49 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T12 |
35 |
|
T102 |
2 |
|
T103 |
49 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1337 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
49 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
791 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T12 |
35 |
|
T102 |
2 |
|
T103 |
48 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
48 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
791 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1217 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
47 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1277 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
46 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
791 |
1 |
|
|
T12 |
11 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1175 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
45 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1249 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
46 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[0] |
62661 |
1 |
|
|
T12 |
1050 |
|
T102 |
37 |
|
T103 |
1441 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44485 |
1 |
|
|
T12 |
946 |
|
T102 |
62 |
|
T103 |
1152 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58261 |
1 |
|
|
T12 |
803 |
|
T102 |
1584 |
|
T103 |
1513 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48449 |
1 |
|
|
T12 |
1907 |
|
T102 |
165 |
|
T103 |
2615 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
775 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1731 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1741 |
1 |
|
|
T12 |
40 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
775 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1699 |
1 |
|
|
T12 |
46 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1699 |
1 |
|
|
T12 |
37 |
|
T102 |
7 |
|
T103 |
53 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1671 |
1 |
|
|
T12 |
45 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1670 |
1 |
|
|
T12 |
35 |
|
T102 |
7 |
|
T103 |
52 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T12 |
45 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1637 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
13 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1608 |
1 |
|
|
T12 |
46 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1604 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
50 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
13 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1575 |
1 |
|
|
T12 |
44 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1556 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
49 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
13 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1524 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
13 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1511 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1486 |
1 |
|
|
T12 |
32 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1472 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1457 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
46 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1440 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
46 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
751 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1418 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1408 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1375 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
43 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1347 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1344 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
41 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1309 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1320 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
41 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T12 |
27 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1284 |
1 |
|
|
T12 |
32 |
|
T102 |
3 |
|
T103 |
39 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1241 |
1 |
|
|
T12 |
26 |
|
T102 |
7 |
|
T103 |
43 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58856 |
1 |
|
|
T12 |
2481 |
|
T102 |
1442 |
|
T103 |
1323 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[1] |
50361 |
1 |
|
|
T12 |
690 |
|
T102 |
98 |
|
T103 |
2432 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57905 |
1 |
|
|
T12 |
787 |
|
T102 |
170 |
|
T103 |
866 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46077 |
1 |
|
|
T12 |
925 |
|
T102 |
96 |
|
T103 |
1699 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
773 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1773 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
75 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1805 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
78 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
773 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1743 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
72 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1761 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
78 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1706 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
71 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
738 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1728 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
78 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1668 |
1 |
|
|
T12 |
28 |
|
T102 |
7 |
|
T103 |
70 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
738 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1689 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
74 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1636 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
70 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1662 |
1 |
|
|
T12 |
32 |
|
T102 |
7 |
|
T103 |
73 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1605 |
1 |
|
|
T12 |
26 |
|
T102 |
6 |
|
T103 |
69 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1620 |
1 |
|
|
T12 |
32 |
|
T102 |
7 |
|
T103 |
70 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
68 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1592 |
1 |
|
|
T12 |
32 |
|
T102 |
7 |
|
T103 |
69 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
759 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
67 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1549 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
69 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1482 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
63 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1513 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
69 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
62 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1476 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
68 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
60 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
67 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1361 |
1 |
|
|
T12 |
24 |
|
T102 |
5 |
|
T103 |
59 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1422 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
66 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T12 |
24 |
|
T102 |
4 |
|
T103 |
56 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1380 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
64 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1285 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
55 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1348 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
63 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
755 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
19 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
15 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1316 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
61 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[0] |
61465 |
1 |
|
|
T12 |
1353 |
|
T102 |
169 |
|
T103 |
3023 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[1] |
41896 |
1 |
|
|
T12 |
2157 |
|
T102 |
147 |
|
T103 |
1311 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[0] |
63563 |
1 |
|
|
T12 |
1001 |
|
T102 |
68 |
|
T103 |
1329 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47857 |
1 |
|
|
T12 |
498 |
|
T102 |
1407 |
|
T103 |
1045 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T12 |
32 |
|
T102 |
9 |
|
T103 |
46 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
785 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1673 |
1 |
|
|
T12 |
27 |
|
T102 |
11 |
|
T103 |
49 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1627 |
1 |
|
|
T12 |
32 |
|
T102 |
9 |
|
T103 |
46 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
785 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1641 |
1 |
|
|
T12 |
25 |
|
T102 |
11 |
|
T103 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1585 |
1 |
|
|
T12 |
32 |
|
T102 |
9 |
|
T103 |
46 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
785 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1616 |
1 |
|
|
T12 |
25 |
|
T102 |
10 |
|
T103 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T12 |
32 |
|
T102 |
9 |
|
T103 |
45 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
785 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1584 |
1 |
|
|
T12 |
24 |
|
T102 |
10 |
|
T103 |
47 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
795 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1532 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
45 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
782 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1562 |
1 |
|
|
T12 |
24 |
|
T102 |
10 |
|
T103 |
47 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
795 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
31 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
45 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
782 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1534 |
1 |
|
|
T12 |
24 |
|
T102 |
10 |
|
T103 |
45 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1456 |
1 |
|
|
T12 |
31 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
778 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1510 |
1 |
|
|
T12 |
23 |
|
T102 |
10 |
|
T103 |
45 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
3 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T12 |
30 |
|
T102 |
9 |
|
T103 |
42 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
778 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1485 |
1 |
|
|
T12 |
22 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
784 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T12 |
30 |
|
T102 |
9 |
|
T103 |
42 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1459 |
1 |
|
|
T12 |
21 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
784 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
41 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1434 |
1 |
|
|
T12 |
20 |
|
T102 |
8 |
|
T103 |
42 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1312 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
41 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1399 |
1 |
|
|
T12 |
19 |
|
T102 |
8 |
|
T103 |
41 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1274 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T12 |
18 |
|
T102 |
7 |
|
T103 |
39 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1231 |
1 |
|
|
T12 |
28 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1319 |
1 |
|
|
T12 |
16 |
|
T102 |
7 |
|
T103 |
35 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T12 |
27 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T12 |
15 |
|
T102 |
7 |
|
T103 |
35 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
30 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T12 |
27 |
|
T102 |
7 |
|
T103 |
39 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
27 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1245 |
1 |
|
|
T12 |
15 |
|
T102 |
7 |
|
T103 |
34 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56467 |
1 |
|
|
T12 |
1266 |
|
T102 |
1363 |
|
T103 |
1838 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49743 |
1 |
|
|
T12 |
1972 |
|
T102 |
112 |
|
T103 |
1246 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55304 |
1 |
|
|
T12 |
1063 |
|
T102 |
218 |
|
T103 |
1202 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[1] |
51385 |
1 |
|
|
T12 |
592 |
|
T102 |
110 |
|
T103 |
2350 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1764 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
57 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1771 |
1 |
|
|
T12 |
33 |
|
T102 |
6 |
|
T103 |
59 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1733 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
56 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1747 |
1 |
|
|
T12 |
33 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
762 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1704 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
55 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1704 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
762 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1673 |
1 |
|
|
T12 |
30 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1672 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
55 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1639 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
758 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1615 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
54 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1610 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1589 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
53 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
52 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1534 |
1 |
|
|
T12 |
26 |
|
T102 |
6 |
|
T103 |
52 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
49 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1485 |
1 |
|
|
T12 |
26 |
|
T102 |
6 |
|
T103 |
50 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1506 |
1 |
|
|
T12 |
29 |
|
T102 |
7 |
|
T103 |
49 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1453 |
1 |
|
|
T12 |
26 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T12 |
28 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1403 |
1 |
|
|
T12 |
26 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1441 |
1 |
|
|
T12 |
27 |
|
T102 |
7 |
|
T103 |
46 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1370 |
1 |
|
|
T12 |
24 |
|
T102 |
4 |
|
T103 |
46 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1407 |
1 |
|
|
T12 |
27 |
|
T102 |
7 |
|
T103 |
46 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1323 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T12 |
27 |
|
T102 |
7 |
|
T103 |
45 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1290 |
1 |
|
|
T12 |
22 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1342 |
1 |
|
|
T12 |
27 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1242 |
1 |
|
|
T12 |
21 |
|
T102 |
3 |
|
T103 |
42 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57073 |
1 |
|
|
T12 |
2137 |
|
T102 |
182 |
|
T103 |
1055 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46772 |
1 |
|
|
T12 |
1113 |
|
T102 |
1340 |
|
T103 |
1468 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56915 |
1 |
|
|
T12 |
1020 |
|
T102 |
304 |
|
T103 |
2395 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[1] |
52501 |
1 |
|
|
T12 |
667 |
|
T102 |
106 |
|
T103 |
1548 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1800 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
70 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1802 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
70 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1764 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
68 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1767 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
70 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1728 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
65 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1738 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
68 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1701 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
65 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1716 |
1 |
|
|
T12 |
33 |
|
T102 |
3 |
|
T103 |
68 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
63 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1674 |
1 |
|
|
T12 |
32 |
|
T102 |
3 |
|
T103 |
66 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1625 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
62 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1641 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
64 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
58 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1603 |
1 |
|
|
T12 |
28 |
|
T102 |
3 |
|
T103 |
63 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T12 |
16 |
|
T102 |
3 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1576 |
1 |
|
|
T12 |
27 |
|
T102 |
3 |
|
T103 |
58 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1531 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1535 |
1 |
|
|
T12 |
27 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
55 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1511 |
1 |
|
|
T12 |
26 |
|
T102 |
3 |
|
T103 |
57 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1450 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1477 |
1 |
|
|
T12 |
26 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1401 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1440 |
1 |
|
|
T12 |
25 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1356 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T12 |
22 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1320 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
51 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1357 |
1 |
|
|
T12 |
22 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
19 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
50 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
14 |
|
T102 |
3 |
|
T103 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T12 |
22 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[0] |
61028 |
1 |
|
|
T12 |
762 |
|
T102 |
341 |
|
T103 |
2539 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48304 |
1 |
|
|
T12 |
753 |
|
T102 |
56 |
|
T103 |
1077 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[0] |
61699 |
1 |
|
|
T12 |
2307 |
|
T102 |
1476 |
|
T103 |
2017 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44325 |
1 |
|
|
T12 |
1044 |
|
T102 |
23 |
|
T103 |
1113 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1661 |
1 |
|
|
T12 |
41 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1662 |
1 |
|
|
T12 |
43 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T12 |
41 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1636 |
1 |
|
|
T12 |
43 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T12 |
41 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1606 |
1 |
|
|
T12 |
42 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
770 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1582 |
1 |
|
|
T12 |
40 |
|
T102 |
1 |
|
T103 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
768 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1577 |
1 |
|
|
T12 |
41 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1547 |
1 |
|
|
T12 |
38 |
|
T102 |
1 |
|
T103 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
764 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1547 |
1 |
|
|
T12 |
41 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1512 |
1 |
|
|
T12 |
37 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
764 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1515 |
1 |
|
|
T12 |
40 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T12 |
37 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1480 |
1 |
|
|
T12 |
39 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T12 |
34 |
|
T102 |
1 |
|
T103 |
42 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1453 |
1 |
|
|
T12 |
38 |
|
T102 |
2 |
|
T103 |
39 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1420 |
1 |
|
|
T12 |
33 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1416 |
1 |
|
|
T12 |
37 |
|
T102 |
2 |
|
T103 |
38 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1385 |
1 |
|
|
T12 |
33 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1388 |
1 |
|
|
T12 |
37 |
|
T102 |
2 |
|
T103 |
38 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1349 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
36 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1353 |
1 |
|
|
T12 |
36 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1323 |
1 |
|
|
T12 |
32 |
|
T102 |
1 |
|
T103 |
35 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1326 |
1 |
|
|
T12 |
35 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1289 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1286 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
30 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1254 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
30 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
752 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
33 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1219 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56974 |
1 |
|
|
T12 |
2588 |
|
T102 |
148 |
|
T103 |
1718 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[1] |
51849 |
1 |
|
|
T12 |
749 |
|
T102 |
35 |
|
T103 |
1993 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58154 |
1 |
|
|
T12 |
962 |
|
T102 |
233 |
|
T103 |
1918 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46359 |
1 |
|
|
T12 |
670 |
|
T102 |
1466 |
|
T103 |
1104 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1764 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
56 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1751 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1726 |
1 |
|
|
T12 |
27 |
|
T102 |
4 |
|
T103 |
55 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1708 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1702 |
1 |
|
|
T12 |
26 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1677 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
49 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1665 |
1 |
|
|
T12 |
26 |
|
T102 |
4 |
|
T103 |
53 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1649 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
49 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1634 |
1 |
|
|
T12 |
25 |
|
T102 |
3 |
|
T103 |
49 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1618 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T12 |
23 |
|
T102 |
3 |
|
T103 |
49 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1588 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T12 |
22 |
|
T102 |
2 |
|
T103 |
46 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1551 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1512 |
1 |
|
|
T12 |
20 |
|
T102 |
2 |
|
T103 |
43 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
765 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1509 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1477 |
1 |
|
|
T12 |
19 |
|
T102 |
2 |
|
T103 |
42 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
763 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1477 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
46 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1455 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
41 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
763 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1451 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1422 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1413 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1378 |
1 |
|
|
T12 |
18 |
|
T102 |
2 |
|
T103 |
38 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1377 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T12 |
17 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1344 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
42 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1292 |
1 |
|
|
T12 |
16 |
|
T102 |
2 |
|
T103 |
34 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1314 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
41 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1258 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1273 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
41 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[0] |
60233 |
1 |
|
|
T12 |
965 |
|
T102 |
53 |
|
T103 |
1343 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46792 |
1 |
|
|
T12 |
879 |
|
T102 |
143 |
|
T103 |
1693 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[0] |
59565 |
1 |
|
|
T12 |
2380 |
|
T102 |
177 |
|
T103 |
2247 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47973 |
1 |
|
|
T12 |
594 |
|
T102 |
1458 |
|
T103 |
1361 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1718 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
61 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1723 |
1 |
|
|
T12 |
37 |
|
T102 |
7 |
|
T103 |
64 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
766 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
61 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1691 |
1 |
|
|
T12 |
36 |
|
T102 |
7 |
|
T103 |
63 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1650 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
59 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1651 |
1 |
|
|
T12 |
35 |
|
T102 |
7 |
|
T103 |
62 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
765 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1620 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
59 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1611 |
1 |
|
|
T12 |
34 |
|
T102 |
7 |
|
T103 |
61 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
58 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
757 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1597 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
60 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
20 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T12 |
40 |
|
T102 |
9 |
|
T103 |
57 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
757 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1552 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
58 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T12 |
38 |
|
T102 |
9 |
|
T103 |
56 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1515 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
57 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
754 |
1 |
|
|
T12 |
14 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1487 |
1 |
|
|
T12 |
38 |
|
T102 |
9 |
|
T103 |
56 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1478 |
1 |
|
|
T12 |
31 |
|
T102 |
7 |
|
T103 |
56 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1457 |
1 |
|
|
T12 |
37 |
|
T102 |
9 |
|
T103 |
56 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1427 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
750 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T12 |
37 |
|
T102 |
8 |
|
T103 |
54 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1397 |
1 |
|
|
T12 |
29 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1396 |
1 |
|
|
T12 |
35 |
|
T102 |
8 |
|
T103 |
52 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1359 |
1 |
|
|
T12 |
28 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1289 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1299 |
1 |
|
|
T12 |
31 |
|
T102 |
6 |
|
T103 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1260 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
749 |
1 |
|
|
T12 |
13 |
|
T102 |
1 |
|
T103 |
19 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1263 |
1 |
|
|
T12 |
31 |
|
T102 |
6 |
|
T103 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
745 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
17 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1218 |
1 |
|
|
T12 |
23 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[0] |
60011 |
1 |
|
|
T12 |
1198 |
|
T102 |
241 |
|
T103 |
1611 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[1] |
53402 |
1 |
|
|
T12 |
459 |
|
T102 |
1317 |
|
T103 |
1075 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55973 |
1 |
|
|
T12 |
2392 |
|
T102 |
267 |
|
T103 |
2769 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43539 |
1 |
|
|
T12 |
903 |
|
T102 |
43 |
|
T103 |
1180 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1819 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1813 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1786 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1771 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1747 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1737 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T12 |
17 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1716 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1700 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
51 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1693 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1670 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1657 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
48 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1643 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1613 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
48 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1594 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1552 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
48 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1538 |
1 |
|
|
T12 |
24 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1512 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
47 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1500 |
1 |
|
|
T12 |
23 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1473 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1447 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
44 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1419 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
43 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1380 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T12 |
19 |
|
T102 |
5 |
|
T103 |
41 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1340 |
1 |
|
|
T12 |
28 |
|
T102 |
3 |
|
T103 |
42 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
16 |
|
T102 |
4 |
|
T103 |
26 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1326 |
1 |
|
|
T12 |
18 |
|
T102 |
5 |
|
T103 |
41 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
17 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1299 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59976 |
1 |
|
|
T12 |
1182 |
|
T102 |
192 |
|
T103 |
2098 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47527 |
1 |
|
|
T12 |
1755 |
|
T102 |
25 |
|
T103 |
1431 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56345 |
1 |
|
|
T12 |
1392 |
|
T102 |
1499 |
|
T103 |
1535 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49496 |
1 |
|
|
T12 |
631 |
|
T102 |
136 |
|
T103 |
1435 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1796 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
63 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1807 |
1 |
|
|
T12 |
26 |
|
T102 |
6 |
|
T103 |
65 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1761 |
1 |
|
|
T12 |
26 |
|
T102 |
4 |
|
T103 |
62 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1779 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
65 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1725 |
1 |
|
|
T12 |
26 |
|
T102 |
4 |
|
T103 |
61 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1752 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
64 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T12 |
24 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1722 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
63 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T12 |
24 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1682 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
61 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1598 |
1 |
|
|
T12 |
24 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
60 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1566 |
1 |
|
|
T12 |
23 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1608 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1532 |
1 |
|
|
T12 |
22 |
|
T102 |
2 |
|
T103 |
54 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1571 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1493 |
1 |
|
|
T12 |
21 |
|
T102 |
2 |
|
T103 |
52 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1538 |
1 |
|
|
T12 |
25 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1453 |
1 |
|
|
T12 |
21 |
|
T102 |
2 |
|
T103 |
52 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1503 |
1 |
|
|
T12 |
23 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T12 |
20 |
|
T102 |
1 |
|
T103 |
51 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1470 |
1 |
|
|
T12 |
23 |
|
T102 |
6 |
|
T103 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1372 |
1 |
|
|
T12 |
20 |
|
T102 |
1 |
|
T103 |
51 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1441 |
1 |
|
|
T12 |
23 |
|
T102 |
6 |
|
T103 |
57 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1339 |
1 |
|
|
T12 |
20 |
|
T102 |
1 |
|
T103 |
49 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1405 |
1 |
|
|
T12 |
23 |
|
T102 |
6 |
|
T103 |
55 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1310 |
1 |
|
|
T12 |
19 |
|
T102 |
1 |
|
T103 |
48 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1372 |
1 |
|
|
T12 |
22 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T12 |
18 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T12 |
21 |
|
T102 |
4 |
|
T103 |
20 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1338 |
1 |
|
|
T12 |
22 |
|
T102 |
6 |
|
T103 |
51 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[0] |
60717 |
1 |
|
|
T12 |
1110 |
|
T102 |
1512 |
|
T103 |
1361 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46583 |
1 |
|
|
T12 |
1711 |
|
T102 |
108 |
|
T103 |
1235 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57158 |
1 |
|
|
T12 |
945 |
|
T102 |
154 |
|
T103 |
1612 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48811 |
1 |
|
|
T12 |
909 |
|
T102 |
80 |
|
T103 |
2398 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1762 |
1 |
|
|
T12 |
38 |
|
T102 |
4 |
|
T103 |
58 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1748 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
64 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
761 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1731 |
1 |
|
|
T12 |
38 |
|
T102 |
4 |
|
T103 |
58 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
775 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1724 |
1 |
|
|
T12 |
41 |
|
T102 |
3 |
|
T103 |
63 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1703 |
1 |
|
|
T12 |
38 |
|
T102 |
4 |
|
T103 |
58 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1690 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
61 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
760 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
55 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
774 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1660 |
1 |
|
|
T12 |
40 |
|
T102 |
3 |
|
T103 |
60 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1622 |
1 |
|
|
T12 |
36 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1636 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
59 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
757 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1588 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
53 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
769 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1608 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
59 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1578 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
21 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1521 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
762 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1541 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
50 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1503 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
56 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
746 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1432 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
47 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
759 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1461 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1391 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1428 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
51 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
745 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1402 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
50 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
744 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1319 |
1 |
|
|
T12 |
28 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
50 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
744 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T12 |
25 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1335 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
50 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
744 |
1 |
|
|
T12 |
20 |
|
T102 |
5 |
|
T103 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
41 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
758 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
19 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1294 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
50 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56575 |
1 |
|
|
T12 |
815 |
|
T102 |
1465 |
|
T103 |
1500 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49812 |
1 |
|
|
T12 |
1022 |
|
T102 |
45 |
|
T103 |
921 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55495 |
1 |
|
|
T12 |
2350 |
|
T102 |
252 |
|
T103 |
1854 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[1] |
50940 |
1 |
|
|
T12 |
725 |
|
T102 |
74 |
|
T103 |
2436 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
777 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1765 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
53 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1794 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
54 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
777 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1733 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1761 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1706 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1721 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
774 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1670 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1686 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1646 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1650 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
772 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1600 |
1 |
|
|
T12 |
31 |
|
T102 |
4 |
|
T103 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1617 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1585 |
1 |
|
|
T12 |
28 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
767 |
1 |
|
|
T12 |
16 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1526 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
46 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
742 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1545 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1496 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
45 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1507 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
48 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
764 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1454 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
42 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
739 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1481 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1425 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
40 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1446 |
1 |
|
|
T12 |
25 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1396 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
40 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T12 |
24 |
|
T102 |
5 |
|
T103 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T12 |
30 |
|
T102 |
2 |
|
T103 |
39 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1384 |
1 |
|
|
T12 |
24 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1336 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
763 |
1 |
|
|
T12 |
15 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T12 |
28 |
|
T102 |
2 |
|
T103 |
36 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
4 |
|
T103 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1301 |
1 |
|
|
T12 |
23 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58475 |
1 |
|
|
T12 |
1114 |
|
T102 |
1422 |
|
T103 |
1905 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45677 |
1 |
|
|
T12 |
1895 |
|
T102 |
21 |
|
T103 |
965 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[0] |
61024 |
1 |
|
|
T12 |
1390 |
|
T102 |
302 |
|
T103 |
2639 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48971 |
1 |
|
|
T12 |
603 |
|
T102 |
141 |
|
T103 |
1163 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
751 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1733 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
55 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1734 |
1 |
|
|
T12 |
28 |
|
T102 |
1 |
|
T103 |
56 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
751 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1704 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1708 |
1 |
|
|
T12 |
26 |
|
T102 |
1 |
|
T103 |
56 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1680 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1682 |
1 |
|
|
T12 |
26 |
|
T102 |
1 |
|
T103 |
55 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
748 |
1 |
|
|
T12 |
13 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
750 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T12 |
26 |
|
T102 |
1 |
|
T103 |
55 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
744 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1613 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1614 |
1 |
|
|
T12 |
25 |
|
T102 |
1 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
744 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
51 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1586 |
1 |
|
|
T12 |
25 |
|
T102 |
1 |
|
T103 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
49 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1559 |
1 |
|
|
T12 |
25 |
|
T102 |
1 |
|
T103 |
51 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1503 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
47 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
738 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
49 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1462 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
47 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1494 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T12 |
29 |
|
T102 |
2 |
|
T103 |
44 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1469 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1390 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
43 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1353 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1392 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
40 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1365 |
1 |
|
|
T12 |
24 |
|
T102 |
1 |
|
T103 |
44 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T12 |
27 |
|
T102 |
1 |
|
T103 |
39 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1325 |
1 |
|
|
T12 |
22 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
6 |
|
T103 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T12 |
27 |
|
T102 |
1 |
|
T103 |
38 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
18 |
|
T102 |
6 |
|
T103 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T12 |
20 |
|
T102 |
1 |
|
T103 |
41 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59147 |
1 |
|
|
T12 |
1009 |
|
T102 |
75 |
|
T103 |
1558 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46510 |
1 |
|
|
T12 |
1924 |
|
T102 |
127 |
|
T103 |
1345 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[0] |
62436 |
1 |
|
|
T12 |
1146 |
|
T102 |
206 |
|
T103 |
1289 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45840 |
1 |
|
|
T12 |
819 |
|
T102 |
1426 |
|
T103 |
2334 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1702 |
1 |
|
|
T12 |
37 |
|
T102 |
9 |
|
T103 |
59 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1700 |
1 |
|
|
T12 |
38 |
|
T102 |
9 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
800 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T12 |
36 |
|
T102 |
8 |
|
T103 |
58 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1666 |
1 |
|
|
T12 |
36 |
|
T102 |
9 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T12 |
35 |
|
T102 |
8 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1628 |
1 |
|
|
T12 |
36 |
|
T102 |
9 |
|
T103 |
53 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
798 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1599 |
1 |
|
|
T12 |
35 |
|
T102 |
8 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1583 |
1 |
|
|
T12 |
35 |
|
T102 |
9 |
|
T103 |
49 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
797 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1572 |
1 |
|
|
T12 |
35 |
|
T102 |
7 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
803 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1553 |
1 |
|
|
T12 |
34 |
|
T102 |
9 |
|
T103 |
48 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
797 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
27 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T12 |
33 |
|
T102 |
7 |
|
T103 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
803 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1518 |
1 |
|
|
T12 |
34 |
|
T102 |
9 |
|
T103 |
48 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T12 |
32 |
|
T102 |
6 |
|
T103 |
53 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
795 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1480 |
1 |
|
|
T12 |
34 |
|
T102 |
9 |
|
T103 |
46 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
15 |
|
T102 |
2 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1463 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
795 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1450 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
45 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
789 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1429 |
1 |
|
|
T12 |
30 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
789 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
789 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1395 |
1 |
|
|
T12 |
29 |
|
T102 |
5 |
|
T103 |
52 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
789 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1399 |
1 |
|
|
T12 |
33 |
|
T102 |
9 |
|
T103 |
43 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
788 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1366 |
1 |
|
|
T12 |
27 |
|
T102 |
5 |
|
T103 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1357 |
1 |
|
|
T12 |
33 |
|
T102 |
8 |
|
T103 |
41 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
788 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1338 |
1 |
|
|
T12 |
27 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1324 |
1 |
|
|
T12 |
33 |
|
T102 |
8 |
|
T103 |
39 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1311 |
1 |
|
|
T12 |
27 |
|
T102 |
4 |
|
T103 |
49 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1285 |
1 |
|
|
T12 |
30 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1286 |
1 |
|
|
T12 |
27 |
|
T102 |
4 |
|
T103 |
47 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1246 |
1 |
|
|
T12 |
30 |
|
T102 |
8 |
|
T103 |
37 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
787 |
1 |
|
|
T12 |
15 |
|
T102 |
1 |
|
T103 |
26 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1257 |
1 |
|
|
T12 |
27 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
788 |
1 |
|
|
T12 |
13 |
|
T102 |
2 |
|
T103 |
31 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1209 |
1 |
|
|
T12 |
29 |
|
T102 |
8 |
|
T103 |
36 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53080 |
1 |
|
|
T12 |
1112 |
|
T102 |
159 |
|
T103 |
1515 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[1] |
51968 |
1 |
|
|
T12 |
767 |
|
T102 |
71 |
|
T103 |
1512 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57207 |
1 |
|
|
T12 |
1116 |
|
T102 |
1501 |
|
T103 |
1170 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[1] |
50353 |
1 |
|
|
T12 |
1730 |
|
T102 |
132 |
|
T103 |
2405 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1833 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
54 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1831 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
59 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1801 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1798 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
57 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1769 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
53 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1757 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
56 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1742 |
1 |
|
|
T12 |
37 |
|
T102 |
5 |
|
T103 |
51 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1715 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
55 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1699 |
1 |
|
|
T12 |
35 |
|
T102 |
5 |
|
T103 |
48 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1681 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1662 |
1 |
|
|
T12 |
34 |
|
T102 |
5 |
|
T103 |
46 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1650 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
45 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1618 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
54 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T12 |
20 |
|
T102 |
4 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1588 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
45 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1579 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1558 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1536 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T12 |
29 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
44 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T12 |
28 |
|
T102 |
3 |
|
T103 |
53 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1456 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
43 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1410 |
1 |
|
|
T12 |
24 |
|
T102 |
2 |
|
T103 |
52 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1427 |
1 |
|
|
T12 |
30 |
|
T102 |
4 |
|
T103 |
42 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1375 |
1 |
|
|
T12 |
23 |
|
T102 |
2 |
|
T103 |
51 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1380 |
1 |
|
|
T12 |
29 |
|
T102 |
4 |
|
T103 |
39 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1333 |
1 |
|
|
T12 |
23 |
|
T102 |
2 |
|
T103 |
48 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T12 |
20 |
|
T102 |
3 |
|
T103 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1350 |
1 |
|
|
T12 |
29 |
|
T102 |
4 |
|
T103 |
38 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T12 |
22 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1294 |
1 |
|
|
T12 |
22 |
|
T102 |
2 |
|
T103 |
48 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56747 |
1 |
|
|
T12 |
664 |
|
T102 |
199 |
|
T103 |
1861 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48550 |
1 |
|
|
T12 |
1040 |
|
T102 |
100 |
|
T103 |
1029 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[0] |
64078 |
1 |
|
|
T12 |
2255 |
|
T102 |
120 |
|
T103 |
2800 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43922 |
1 |
|
|
T12 |
879 |
|
T102 |
1356 |
|
T103 |
1115 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
795 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1728 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
43 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1719 |
1 |
|
|
T12 |
43 |
|
T102 |
7 |
|
T103 |
50 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
795 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1691 |
1 |
|
|
T12 |
41 |
|
T102 |
5 |
|
T103 |
42 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1696 |
1 |
|
|
T12 |
42 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
794 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1650 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1661 |
1 |
|
|
T12 |
41 |
|
T102 |
7 |
|
T103 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
794 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1616 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
805 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1632 |
1 |
|
|
T12 |
41 |
|
T102 |
6 |
|
T103 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1571 |
1 |
|
|
T12 |
40 |
|
T102 |
5 |
|
T103 |
40 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
802 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1604 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
47 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
792 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T12 |
39 |
|
T102 |
5 |
|
T103 |
37 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
802 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1568 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
45 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
786 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1506 |
1 |
|
|
T12 |
38 |
|
T102 |
5 |
|
T103 |
36 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
797 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1537 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
45 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
786 |
1 |
|
|
T12 |
12 |
|
T102 |
7 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1462 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
33 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
797 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1502 |
1 |
|
|
T12 |
40 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1431 |
1 |
|
|
T12 |
37 |
|
T102 |
4 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
794 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1459 |
1 |
|
|
T12 |
38 |
|
T102 |
6 |
|
T103 |
44 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1400 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
794 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1419 |
1 |
|
|
T12 |
37 |
|
T102 |
6 |
|
T103 |
43 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1376 |
1 |
|
|
T12 |
35 |
|
T102 |
4 |
|
T103 |
31 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1389 |
1 |
|
|
T12 |
36 |
|
T102 |
6 |
|
T103 |
43 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
31 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T12 |
35 |
|
T102 |
6 |
|
T103 |
42 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1315 |
1 |
|
|
T12 |
34 |
|
T102 |
4 |
|
T103 |
30 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1317 |
1 |
|
|
T12 |
34 |
|
T102 |
6 |
|
T103 |
40 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1292 |
1 |
|
|
T12 |
33 |
|
T102 |
4 |
|
T103 |
29 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1276 |
1 |
|
|
T12 |
32 |
|
T102 |
5 |
|
T103 |
38 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
783 |
1 |
|
|
T12 |
11 |
|
T102 |
6 |
|
T103 |
32 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1249 |
1 |
|
|
T12 |
32 |
|
T102 |
4 |
|
T103 |
29 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
792 |
1 |
|
|
T12 |
10 |
|
T102 |
5 |
|
T103 |
25 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1248 |
1 |
|
|
T12 |
31 |
|
T102 |
5 |
|
T103 |
38 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57041 |
1 |
|
|
T12 |
967 |
|
T102 |
1601 |
|
T103 |
1297 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44418 |
1 |
|
|
T12 |
716 |
|
T102 |
91 |
|
T103 |
982 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[0] |
66071 |
1 |
|
|
T12 |
2336 |
|
T102 |
152 |
|
T103 |
1952 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46020 |
1 |
|
|
T12 |
885 |
|
T102 |
50 |
|
T103 |
2542 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1780 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
54 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1758 |
1 |
|
|
T12 |
34 |
|
T102 |
2 |
|
T103 |
55 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1752 |
1 |
|
|
T12 |
39 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
761 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1724 |
1 |
|
|
T12 |
33 |
|
T102 |
2 |
|
T103 |
55 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1724 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
52 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1687 |
1 |
|
|
T12 |
32 |
|
T102 |
2 |
|
T103 |
55 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T12 |
12 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T12 |
38 |
|
T102 |
3 |
|
T103 |
49 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
760 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1657 |
1 |
|
|
T12 |
31 |
|
T102 |
2 |
|
T103 |
53 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1648 |
1 |
|
|
T12 |
37 |
|
T102 |
3 |
|
T103 |
46 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
757 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1626 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
52 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1607 |
1 |
|
|
T12 |
35 |
|
T102 |
3 |
|
T103 |
46 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
757 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1591 |
1 |
|
|
T12 |
31 |
|
T102 |
1 |
|
T103 |
52 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1567 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
45 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T12 |
34 |
|
T102 |
3 |
|
T103 |
43 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
755 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1512 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
50 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1499 |
1 |
|
|
T12 |
33 |
|
T102 |
3 |
|
T103 |
42 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T12 |
30 |
|
T102 |
1 |
|
T103 |
49 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1476 |
1 |
|
|
T12 |
33 |
|
T102 |
3 |
|
T103 |
41 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
748 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T12 |
29 |
|
T102 |
1 |
|
T103 |
49 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T12 |
33 |
|
T102 |
3 |
|
T103 |
41 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1413 |
1 |
|
|
T12 |
27 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1421 |
1 |
|
|
T12 |
32 |
|
T102 |
3 |
|
T103 |
39 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1381 |
1 |
|
|
T12 |
27 |
|
T102 |
1 |
|
T103 |
47 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1367 |
1 |
|
|
T12 |
31 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1348 |
1 |
|
|
T12 |
27 |
|
T102 |
1 |
|
T103 |
46 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1335 |
1 |
|
|
T12 |
30 |
|
T102 |
3 |
|
T103 |
37 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1319 |
1 |
|
|
T12 |
27 |
|
T103 |
45 |
|
T104 |
27 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T12 |
11 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1292 |
1 |
|
|
T12 |
29 |
|
T102 |
3 |
|
T103 |
35 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
746 |
1 |
|
|
T12 |
17 |
|
T102 |
5 |
|
T103 |
22 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T12 |
25 |
|
T103 |
45 |
|
T104 |
26 |