Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4065161	1			T25	1		T1	27026		T11	1
all_pins[1]	4065161	1			T25	1		T1	27026		T11	1
all_pins[2]	4065161	1			T25	1		T1	27026		T11	1
all_pins[3]	4065161	1			T25	1		T1	27026		T11	1
all_pins[4]	4065161	1			T25	1		T1	27026		T11	1
all_pins[5]	4065161	1			T25	1		T1	27026		T11	1
all_pins[6]	4065161	1			T25	1		T1	27026		T11	1
all_pins[7]	4065161	1			T25	1		T1	27026		T11	1
all_pins[8]	4065161	1			T25	1		T1	27026		T11	1
all_pins[9]	4065161	1			T25	1		T1	27026		T11	1
all_pins[10]	4065161	1			T25	1		T1	27026		T11	1
all_pins[11]	4065161	1			T25	1		T1	27026		T11	1
all_pins[12]	4065161	1			T25	1		T1	27026		T11	1
all_pins[13]	4065161	1			T25	1		T1	27026		T11	1
all_pins[14]	4065161	1			T25	1		T1	27026		T11	1
all_pins[15]	4065161	1			T25	1		T1	27026		T11	1
all_pins[16]	4065161	1			T25	1		T1	27026		T11	1
all_pins[17]	4065161	1			T25	1		T1	27026		T11	1
all_pins[18]	4065161	1			T25	1		T1	27026		T11	1
all_pins[19]	4065161	1			T25	1		T1	27026		T11	1
all_pins[20]	4065161	1			T25	1		T1	27026		T11	1
all_pins[21]	4065161	1			T25	1		T1	27026		T11	1
all_pins[22]	4065161	1			T25	1		T1	27026		T11	1
all_pins[23]	4065161	1			T25	1		T1	27026		T11	1
all_pins[24]	4065161	1			T25	1		T1	27026		T11	1
all_pins[25]	4065161	1			T25	1		T1	27026		T11	1
all_pins[26]	4065161	1			T25	1		T1	27026		T11	1
all_pins[27]	4065161	1			T25	1		T1	27026		T11	1
all_pins[28]	4065161	1			T25	1		T1	27026		T11	1
all_pins[29]	4065161	1			T25	1		T1	27026		T11	1
all_pins[30]	4065161	1			T25	1		T1	27026		T11	1
all_pins[31]	4065161	1			T25	1		T1	27026		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	80822788	1			T25	32		T1	537010		T11	32
values[0x1]	49262364	1			T1	327822		T12	1064		T13	2724
transitions[0x0=>0x1]	29528532	1			T1	195544		T12	570		T13	1597
transitions[0x1=>0x0]	29528373	1			T1	195544		T12	570		T13	1597

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2523256	1			T25	1		T1	16919		T11	1
all_pins[0]	values[0x1]	1541905	1			T1	10107		T12	27		T13	85
all_pins[0]	transitions[0x0=>0x1]	955682	1			T1	5972		T12	19		T13	50
all_pins[0]	transitions[0x1=>0x0]	951481	1			T1	6377		T12	18		T13	31
all_pins[1]	values[0x0]	2527118	1			T25	1		T1	17131		T11	1
all_pins[1]	values[0x1]	1538043	1			T1	9895		T12	39		T13	100
all_pins[1]	transitions[0x0=>0x1]	917410	1			T1	5968		T12	23		T13	72
all_pins[1]	transitions[0x1=>0x0]	921272	1			T1	6180		T12	11		T13	57
all_pins[2]	values[0x0]	2523729	1			T25	1		T1	16919		T11	1
all_pins[2]	values[0x1]	1541432	1			T1	10107		T12	35		T13	97
all_pins[2]	transitions[0x0=>0x1]	925014	1			T1	6270		T12	15		T13	49
all_pins[2]	transitions[0x1=>0x0]	921625	1			T1	6058		T12	19		T13	52
all_pins[3]	values[0x0]	2527046	1			T25	1		T1	16359		T11	1
all_pins[3]	values[0x1]	1538115	1			T1	10667		T12	24		T13	89
all_pins[3]	transitions[0x0=>0x1]	918496	1			T1	6311		T12	15		T13	63
all_pins[3]	transitions[0x1=>0x0]	921813	1			T1	5751		T12	26		T13	71
all_pins[4]	values[0x0]	2525801	1			T25	1		T1	16819		T11	1
all_pins[4]	values[0x1]	1539360	1			T1	10207		T12	37		T13	106
all_pins[4]	transitions[0x0=>0x1]	923521	1			T1	5909		T12	24		T13	63
all_pins[4]	transitions[0x1=>0x0]	922276	1			T1	6369		T12	11		T13	46
all_pins[5]	values[0x0]	2524932	1			T25	1		T1	16646		T11	1
all_pins[5]	values[0x1]	1540229	1			T1	10380		T12	33		T13	79
all_pins[5]	transitions[0x0=>0x1]	924012	1			T1	6368		T12	14		T13	24
all_pins[5]	transitions[0x1=>0x0]	923143	1			T1	6195		T12	18		T13	51
all_pins[6]	values[0x0]	2520290	1			T25	1		T1	16717		T11	1
all_pins[6]	values[0x1]	1544871	1			T1	10309		T12	32		T13	100
all_pins[6]	transitions[0x0=>0x1]	923027	1			T1	5955		T12	17		T13	63
all_pins[6]	transitions[0x1=>0x0]	918385	1			T1	6026		T12	18		T13	42
all_pins[7]	values[0x0]	2527482	1			T25	1		T1	16660		T11	1
all_pins[7]	values[0x1]	1537679	1			T1	10366		T12	32		T13	104
all_pins[7]	transitions[0x0=>0x1]	916759	1			T1	6155		T12	17		T13	47
all_pins[7]	transitions[0x1=>0x0]	923951	1			T1	6098		T12	17		T13	43
all_pins[8]	values[0x0]	2524580	1			T25	1		T1	16557		T11	1
all_pins[8]	values[0x1]	1540581	1			T1	10469		T12	30		T13	82
all_pins[8]	transitions[0x0=>0x1]	921950	1			T1	6197		T12	19		T13	44
all_pins[8]	transitions[0x1=>0x0]	919048	1			T1	6094		T12	21		T13	66
all_pins[9]	values[0x0]	2521295	1			T25	1		T1	16807		T11	1
all_pins[9]	values[0x1]	1543866	1			T1	10219		T12	41		T13	82
all_pins[9]	transitions[0x0=>0x1]	922484	1			T1	5957		T12	22		T13	40
all_pins[9]	transitions[0x1=>0x0]	919199	1			T1	6207		T12	11		T13	40
all_pins[10]	values[0x0]	2526882	1			T25	1		T1	17164		T11	1
all_pins[10]	values[0x1]	1538279	1			T1	9862		T12	33		T13	65
all_pins[10]	transitions[0x0=>0x1]	918578	1			T1	5832		T12	16		T13	36
all_pins[10]	transitions[0x1=>0x0]	924165	1			T1	6189		T12	24		T13	53
all_pins[11]	values[0x0]	2531196	1			T25	1		T1	16838		T11	1
all_pins[11]	values[0x1]	1533965	1			T1	10188		T12	35		T13	83
all_pins[11]	transitions[0x0=>0x1]	915603	1			T1	6335		T12	21		T13	65
all_pins[11]	transitions[0x1=>0x0]	919917	1			T1	6009		T12	19		T13	47
all_pins[12]	values[0x0]	2523453	1			T25	1		T1	16674		T11	1
all_pins[12]	values[0x1]	1541708	1			T1	10352		T12	28		T13	93
all_pins[12]	transitions[0x0=>0x1]	925707	1			T1	6257		T12	14		T13	47
all_pins[12]	transitions[0x1=>0x0]	917964	1			T1	6093		T12	21		T13	37
all_pins[13]	values[0x0]	2523108	1			T25	1		T1	16669		T11	1
all_pins[13]	values[0x1]	1542053	1			T1	10357		T12	34		T13	77
all_pins[13]	transitions[0x0=>0x1]	923794	1			T1	6064		T12	18		T13	45
all_pins[13]	transitions[0x1=>0x0]	923449	1			T1	6059		T12	12		T13	61
all_pins[14]	values[0x0]	2527517	1			T25	1		T1	17411		T11	1
all_pins[14]	values[0x1]	1537644	1			T1	9615		T12	37		T13	80
all_pins[14]	transitions[0x0=>0x1]	921163	1			T1	5597		T12	16		T13	59
all_pins[14]	transitions[0x1=>0x0]	925572	1			T1	6339		T12	13		T13	56
all_pins[15]	values[0x0]	2529352	1			T25	1		T1	16438		T11	1
all_pins[15]	values[0x1]	1535809	1			T1	10588		T12	36		T13	65
all_pins[15]	transitions[0x0=>0x1]	923090	1			T1	6545		T12	19		T13	46
all_pins[15]	transitions[0x1=>0x0]	924925	1			T1	5572		T12	20		T13	61
all_pins[16]	values[0x0]	2516872	1			T25	1		T1	16746		T11	1
all_pins[16]	values[0x1]	1548289	1			T1	10280		T12	42		T13	50
all_pins[16]	transitions[0x0=>0x1]	928951	1			T1	5960		T12	19		T13	34
all_pins[16]	transitions[0x1=>0x0]	916471	1			T1	6268		T12	13		T13	49
all_pins[17]	values[0x0]	2525437	1			T25	1		T1	16787		T11	1
all_pins[17]	values[0x1]	1539724	1			T1	10239		T12	29		T13	69
all_pins[17]	transitions[0x0=>0x1]	916879	1			T1	6096		T12	12		T13	37
all_pins[17]	transitions[0x1=>0x0]	925444	1			T1	6137		T12	25		T13	18
all_pins[18]	values[0x0]	2523295	1			T25	1		T1	16276		T11	1
all_pins[18]	values[0x1]	1541866	1			T1	10750		T12	46		T13	108
all_pins[18]	transitions[0x0=>0x1]	923335	1			T1	6557		T12	26		T13	70
all_pins[18]	transitions[0x1=>0x0]	921193	1			T1	6046		T12	9		T13	31
all_pins[19]	values[0x0]	2525110	1			T25	1		T1	17046		T11	1
all_pins[19]	values[0x1]	1540051	1			T1	9980		T12	34		T13	67
all_pins[19]	transitions[0x0=>0x1]	920745	1			T1	5632		T12	13		T13	27
all_pins[19]	transitions[0x1=>0x0]	922560	1			T1	6402		T12	25		T13	68
all_pins[20]	values[0x0]	2524349	1			T25	1		T1	17029		T11	1
all_pins[20]	values[0x1]	1540812	1			T1	9997		T12	34		T13	99
all_pins[20]	transitions[0x0=>0x1]	922184	1			T1	5997		T12	14		T13	70
all_pins[20]	transitions[0x1=>0x0]	921423	1			T1	5980		T12	14		T13	38
all_pins[21]	values[0x0]	2524884	1			T25	1		T1	16829		T11	1
all_pins[21]	values[0x1]	1540277	1			T1	10197		T12	30		T13	52
all_pins[21]	transitions[0x0=>0x1]	923280	1			T1	6368		T12	17		T13	26
all_pins[21]	transitions[0x1=>0x0]	923815	1			T1	6168		T12	21		T13	73
all_pins[22]	values[0x0]	2531175	1			T25	1		T1	17044		T11	1
all_pins[22]	values[0x1]	1533986	1			T1	9982		T12	40		T13	85
all_pins[22]	transitions[0x0=>0x1]	917254	1			T1	5974		T12	26		T13	52
all_pins[22]	transitions[0x1=>0x0]	923545	1			T1	6189		T12	16		T13	19
all_pins[23]	values[0x0]	2528737	1			T25	1		T1	16697		T11	1
all_pins[23]	values[0x1]	1536424	1			T1	10329		T12	31		T13	113
all_pins[23]	transitions[0x0=>0x1]	922652	1			T1	6284		T12	14		T13	69
all_pins[23]	transitions[0x1=>0x0]	920214	1			T1	5937		T12	23		T13	41
all_pins[24]	values[0x0]	2530235	1			T25	1		T1	16807		T11	1
all_pins[24]	values[0x1]	1534926	1			T1	10219		T12	32		T13	79
all_pins[24]	transitions[0x0=>0x1]	920806	1			T1	5967		T12	17		T13	41
all_pins[24]	transitions[0x1=>0x0]	922304	1			T1	6077		T12	16		T13	75
all_pins[25]	values[0x0]	2530202	1			T25	1		T1	16685		T11	1
all_pins[25]	values[0x1]	1534959	1			T1	10341		T12	34		T13	119
all_pins[25]	transitions[0x0=>0x1]	919785	1			T1	6088		T12	17		T13	80
all_pins[25]	transitions[0x1=>0x0]	919752	1			T1	5966		T12	15		T13	40
all_pins[26]	values[0x0]	2526829	1			T25	1		T1	16438		T11	1
all_pins[26]	values[0x1]	1538332	1			T1	10588		T12	31		T13	81
all_pins[26]	transitions[0x0=>0x1]	926083	1			T1	6337		T12	14		T13	34
all_pins[26]	transitions[0x1=>0x0]	922710	1			T1	6090		T12	17		T13	72
all_pins[27]	values[0x0]	2522045	1			T25	1		T1	17257		T11	1
all_pins[27]	values[0x1]	1543116	1			T1	9769		T12	29		T13	101
all_pins[27]	transitions[0x0=>0x1]	925033	1			T1	5694		T12	14		T13	67
all_pins[27]	transitions[0x1=>0x0]	920249	1			T1	6513		T12	16		T13	47
all_pins[28]	values[0x0]	2524742	1			T25	1		T1	16695		T11	1
all_pins[28]	values[0x1]	1540419	1			T1	10331		T12	32		T13	63
all_pins[28]	transitions[0x0=>0x1]	921936	1			T1	6421		T12	21		T13	28
all_pins[28]	transitions[0x1=>0x0]	924633	1			T1	5859		T12	18		T13	66
all_pins[29]	values[0x0]	2525188	1			T25	1		T1	16520		T11	1
all_pins[29]	values[0x1]	1539973	1			T1	10506		T12	24		T13	88
all_pins[29]	transitions[0x0=>0x1]	922162	1			T1	6327		T12	16		T13	58
all_pins[29]	transitions[0x1=>0x0]	922608	1			T1	6152		T12	24		T13	33
all_pins[30]	values[0x0]	2529353	1			T25	1		T1	16912		T11	1
all_pins[30]	values[0x1]	1535808	1			T1	10114		T12	37		T13	97
all_pins[30]	transitions[0x0=>0x1]	919491	1			T1	5830		T12	30		T13	54
all_pins[30]	transitions[0x1=>0x0]	923656	1			T1	6222		T12	17		T13	45
all_pins[31]	values[0x0]	2527298	1			T25	1		T1	16514		T11	1
all_pins[31]	values[0x1]	1537863	1			T1	10512		T12	26		T13	66
all_pins[31]	transitions[0x0=>0x1]	921666	1			T1	6320		T12	11		T13	37
all_pins[31]	transitions[0x1=>0x0]	919611	1			T1	5922		T12	22		T13	68