Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13630724	1			T25	1		T1	95735		T11	290
all_values[1]	13630724	1			T25	1		T1	95735		T11	290
all_values[2]	13630724	1			T25	1		T1	95735		T11	290
all_values[3]	13630724	1			T25	1		T1	95735		T11	290
all_values[4]	13630724	1			T25	1		T1	95735		T11	290
all_values[5]	13630724	1			T25	1		T1	95735		T11	290
all_values[6]	13630724	1			T25	1		T1	95735		T11	290
all_values[7]	13630724	1			T25	1		T1	95735		T11	290
all_values[8]	13630724	1			T25	1		T1	95735		T11	290
all_values[9]	13630724	1			T25	1		T1	95735		T11	290
all_values[10]	13630724	1			T25	1		T1	95735		T11	290
all_values[11]	13630724	1			T25	1		T1	95735		T11	290
all_values[12]	13630724	1			T25	1		T1	95735		T11	290
all_values[13]	13630724	1			T25	1		T1	95735		T11	290
all_values[14]	13630724	1			T25	1		T1	95735		T11	290
all_values[15]	13630724	1			T25	1		T1	95735		T11	290
all_values[16]	13630724	1			T25	1		T1	95735		T11	290
all_values[17]	13630724	1			T25	1		T1	95735		T11	290
all_values[18]	13630724	1			T25	1		T1	95735		T11	290
all_values[19]	13630724	1			T25	1		T1	95735		T11	290
all_values[20]	13630724	1			T25	1		T1	95735		T11	290
all_values[21]	13630724	1			T25	1		T1	95735		T11	290
all_values[22]	13630724	1			T25	1		T1	95735		T11	290
all_values[23]	13630724	1			T25	1		T1	95735		T11	290
all_values[24]	13630724	1			T25	1		T1	95735		T11	290
all_values[25]	13630724	1			T25	1		T1	95735		T11	290
all_values[26]	13630724	1			T25	1		T1	95735		T11	290
all_values[27]	13630724	1			T25	1		T1	95735		T11	290
all_values[28]	13630724	1			T25	1		T1	95735		T11	290
all_values[29]	13630724	1			T25	1		T1	95735		T11	290
all_values[30]	13630724	1			T25	1		T1	95735		T11	290
all_values[31]	13630724	1			T25	1		T1	95735		T11	290

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252462395

1

T25

32

T1

174664

T11

9280

auto[1]

183720773

1

T1

131687

T13

8498

T16

894110

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104156533

1

T25

32

T1

660561

T11

9280

auto[1]

332026635

1

T1

240295

T13

16789

T16

159896

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431395155

1

T25

32

T1

301775

T11

9280

auto[1]

4788013

1

T1

45762

T13

814

T16

25919

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2698337	1			T25	1		T1	16609		T11	290
all_values[0]	auto[0]	auto[0]	auto[1]	5110525	1			T1	36599		T13	290		T16	24064
all_values[0]	auto[0]	auto[1]	auto[0]	554290	1			T1	3874		T13	38		T16	3138
all_values[0]	auto[0]	auto[1]	auto[1]	5118086	1			T1	37258		T13	213		T16	25136
all_values[0]	auto[1]	auto[0]	auto[1]	75243	1			T1	712		T13	15		T16	414
all_values[0]	auto[1]	auto[1]	auto[1]	74243	1			T1	683		T13	12		T16	395
all_values[1]	auto[0]	auto[0]	auto[0]	2699941	1			T25	1		T1	16738		T11	290
all_values[1]	auto[0]	auto[0]	auto[1]	5130995	1			T1	36663		T13	177		T16	25283
all_values[1]	auto[0]	auto[1]	auto[0]	552931	1			T1	4359		T13	57		T16	3070
all_values[1]	auto[0]	auto[1]	auto[1]	5097449	1			T1	36515		T13	263		T16	24353
all_values[1]	auto[1]	auto[0]	auto[1]	74889	1			T1	760		T13	10		T16	389
all_values[1]	auto[1]	auto[1]	auto[1]	74519	1			T1	700		T13	14		T16	404
all_values[2]	auto[0]	auto[0]	auto[0]	2697680	1			T25	1		T1	16580		T11	290
all_values[2]	auto[0]	auto[0]	auto[1]	5097132	1			T1	39047		T13	258		T16	26141
all_values[2]	auto[0]	auto[1]	auto[0]	557206	1			T1	3652		T13	28		T16	3112
all_values[2]	auto[0]	auto[1]	auto[1]	5129059	1			T1	35024		T13	267		T16	23023
all_values[2]	auto[1]	auto[0]	auto[1]	75544	1			T1	713		T13	18		T16	465
all_values[2]	auto[1]	auto[1]	auto[1]	74103	1			T1	719		T13	12		T16	366
all_values[3]	auto[0]	auto[0]	auto[0]	2700816	1			T25	1		T1	16616		T11	290
all_values[3]	auto[0]	auto[0]	auto[1]	5098290	1			T1	36283		T13	266		T16	23955
all_values[3]	auto[0]	auto[1]	auto[0]	557547	1			T1	3774		T13	20		T16	2914
all_values[3]	auto[0]	auto[1]	auto[1]	5124438	1			T1	37608		T13	229		T16	25814
all_values[3]	auto[1]	auto[0]	auto[1]	75237	1			T1	685		T13	13		T16	422
all_values[3]	auto[1]	auto[1]	auto[1]	74396	1			T1	769		T13	10		T16	410
all_values[4]	auto[0]	auto[0]	auto[0]	2693504	1			T25	1		T1	16613		T11	290
all_values[4]	auto[0]	auto[0]	auto[1]	5134851	1			T1	38027		T13	204		T16	22783
all_values[4]	auto[0]	auto[1]	auto[0]	551058	1			T1	3360		T13	26		T16	3228
all_values[4]	auto[0]	auto[1]	auto[1]	5102192	1			T1	36305		T13	309		T16	25144
all_values[4]	auto[1]	auto[0]	auto[1]	74955	1			T1	741		T13	11		T16	400
all_values[4]	auto[1]	auto[1]	auto[1]	74164	1			T1	689		T13	14		T16	425
all_values[5]	auto[0]	auto[0]	auto[0]	2702096	1			T25	1		T1	16371		T11	290
all_values[5]	auto[0]	auto[0]	auto[1]	5123246	1			T1	36477		T13	236		T16	24778
all_values[5]	auto[0]	auto[1]	auto[0]	557372	1			T1	3734		T13	20		T16	3074
all_values[5]	auto[0]	auto[1]	auto[1]	5098510	1			T1	37736		T13	257		T16	24542
all_values[5]	auto[1]	auto[0]	auto[1]	74529	1			T1	695		T13	12		T16	436
all_values[5]	auto[1]	auto[1]	auto[1]	74971	1			T1	722		T13	13		T16	367
all_values[6]	auto[0]	auto[0]	auto[0]	2683851	1			T25	1		T1	16494		T11	290
all_values[6]	auto[0]	auto[0]	auto[1]	5133056	1			T1	37487		T13	267		T16	24479
all_values[6]	auto[0]	auto[1]	auto[0]	555156	1			T1	3844		T13	36		T16	3132
all_values[6]	auto[0]	auto[1]	auto[1]	5109134	1			T1	36474		T13	253		T16	24655
all_values[6]	auto[1]	auto[0]	auto[1]	74679	1			T1	746		T13	18		T16	367
all_values[6]	auto[1]	auto[1]	auto[1]	74848	1			T1	690		T13	9		T16	421
all_values[7]	auto[0]	auto[0]	auto[0]	2700358	1			T25	1		T1	16399		T11	290
all_values[7]	auto[0]	auto[0]	auto[1]	5134992	1			T1	38061		T13	217		T16	25235
all_values[7]	auto[0]	auto[1]	auto[0]	559932	1			T1	3490		T13	29		T16	3288
all_values[7]	auto[0]	auto[1]	auto[1]	5085485	1			T1	36323		T13	238		T16	23698
all_values[7]	auto[1]	auto[0]	auto[1]	74956	1			T1	733		T13	12		T16	438
all_values[7]	auto[1]	auto[1]	auto[1]	75001	1			T1	729		T13	15		T16	394
all_values[8]	auto[0]	auto[0]	auto[0]	2702895	1			T25	1		T1	16728		T11	290
all_values[8]	auto[0]	auto[0]	auto[1]	5137142	1			T1	36006		T13	315		T16	25458
all_values[8]	auto[0]	auto[1]	auto[0]	552366	1			T1	3857		T13	22		T16	3141
all_values[8]	auto[0]	auto[1]	auto[1]	5088462	1			T1	37730		T13	218		T16	23912
all_values[8]	auto[1]	auto[0]	auto[1]	75181	1			T1	705		T13	16		T16	365
all_values[8]	auto[1]	auto[1]	auto[1]	74678	1			T1	709		T13	8		T16	421
all_values[9]	auto[0]	auto[0]	auto[0]	2697576	1			T25	1		T1	16517		T11	290
all_values[9]	auto[0]	auto[0]	auto[1]	5085245	1			T1	36925		T13	292		T16	24680
all_values[9]	auto[0]	auto[1]	auto[0]	560431	1			T1	3856		T13	17		T16	2986
all_values[9]	auto[0]	auto[1]	auto[1]	5138028	1			T1	37026		T13	221		T16	24580
all_values[9]	auto[1]	auto[0]	auto[1]	74960	1			T1	726		T13	13		T16	419
all_values[9]	auto[1]	auto[1]	auto[1]	74484	1			T1	685		T13	13		T16	419
all_values[10]	auto[0]	auto[0]	auto[0]	2694332	1			T25	1		T1	16767		T11	290
all_values[10]	auto[0]	auto[0]	auto[1]	5120733	1			T1	36411		T13	276		T16	23205
all_values[10]	auto[0]	auto[1]	auto[0]	563683	1			T1	4114		T13	34		T16	3008
all_values[10]	auto[0]	auto[1]	auto[1]	5102382	1			T1	37031		T13	197		T16	25994
all_values[10]	auto[1]	auto[0]	auto[1]	74810	1			T1	705		T13	14		T16	376
all_values[10]	auto[1]	auto[1]	auto[1]	74784	1			T1	707		T13	10		T16	434
all_values[11]	auto[0]	auto[0]	auto[0]	2701887	1			T25	1		T1	16859		T11	290
all_values[11]	auto[0]	auto[0]	auto[1]	5118105	1			T1	36680		T13	341		T16	25815
all_values[11]	auto[0]	auto[1]	auto[0]	557992	1			T1	4021		T13	22		T16	2965
all_values[11]	auto[0]	auto[1]	auto[1]	5103579	1			T1	36760		T13	180		T16	23506
all_values[11]	auto[1]	auto[0]	auto[1]	75052	1			T1	679		T13	22		T16	394
all_values[11]	auto[1]	auto[1]	auto[1]	74109	1			T1	736		T13	8		T16	425
all_values[12]	auto[0]	auto[0]	auto[0]	2687403	1			T25	1		T1	16518		T11	290
all_values[12]	auto[0]	auto[0]	auto[1]	5107666	1			T1	36595		T13	283		T16	25277
all_values[12]	auto[0]	auto[1]	auto[0]	557578	1			T1	3808		T13	7		T16	3054
all_values[12]	auto[0]	auto[1]	auto[1]	5128877	1			T1	37429		T13	244		T16	23665
all_values[12]	auto[1]	auto[0]	auto[1]	74773	1			T1	687		T13	22		T16	418
all_values[12]	auto[1]	auto[1]	auto[1]	74427	1			T1	698		T13	8		T16	409
all_values[13]	auto[0]	auto[0]	auto[0]	2691552	1			T25	1		T1	16581		T11	290
all_values[13]	auto[0]	auto[0]	auto[1]	5103567	1			T1	38322		T13	356		T16	24318
all_values[13]	auto[0]	auto[1]	auto[0]	557621	1			T1	3551		T13	13		T16	3677
all_values[13]	auto[0]	auto[1]	auto[1]	5128159	1			T1	35865		T13	200		T16	23972
all_values[13]	auto[1]	auto[0]	auto[1]	74798	1			T1	641		T13	20		T16	443
all_values[13]	auto[1]	auto[1]	auto[1]	75027	1			T1	775		T13	8		T16	421
all_values[14]	auto[0]	auto[0]	auto[0]	2697925	1			T25	1		T1	17067		T11	290
all_values[14]	auto[0]	auto[0]	auto[1]	5137369	1			T1	37461		T13	278		T16	24486
all_values[14]	auto[0]	auto[1]	auto[0]	554990	1			T1	3784		T13	56		T16	3112
all_values[14]	auto[0]	auto[1]	auto[1]	5090389	1			T1	35981		T13	191		T16	24691
all_values[14]	auto[1]	auto[0]	auto[1]	75005	1			T1	716		T13	11		T16	423
all_values[14]	auto[1]	auto[1]	auto[1]	75046	1			T1	726		T13	10		T16	385
all_values[15]	auto[0]	auto[0]	auto[0]	2697011	1			T25	1		T1	16344		T11	290
all_values[15]	auto[0]	auto[0]	auto[1]	5115015	1			T1	36128		T13	320		T16	23625
all_values[15]	auto[0]	auto[1]	auto[0]	561241	1			T1	4092		T13	19		T16	3034
all_values[15]	auto[0]	auto[1]	auto[1]	5108130	1			T1	37701		T13	150		T16	25528
all_values[15]	auto[1]	auto[0]	auto[1]	74986	1			T1	741		T13	19		T16	388
all_values[15]	auto[1]	auto[1]	auto[1]	74341	1			T1	729		T13	10		T16	416
all_values[16]	auto[0]	auto[0]	auto[0]	2685510	1			T25	1		T1	16900		T11	290
all_values[16]	auto[0]	auto[0]	auto[1]	5119551	1			T1	39162		T13	372		T16	24723
all_values[16]	auto[0]	auto[1]	auto[0]	558541	1			T1	3801		T13	38		T16	3199
all_values[16]	auto[0]	auto[1]	auto[1]	5117595	1			T1	34444		T13	137		T16	24516
all_values[16]	auto[1]	auto[0]	auto[1]	74977	1			T1	748		T13	17		T16	379
all_values[16]	auto[1]	auto[1]	auto[1]	74550	1			T1	680		T13	9		T16	404
all_values[17]	auto[0]	auto[0]	auto[0]	2688570	1			T25	1		T1	16841		T11	290
all_values[17]	auto[0]	auto[0]	auto[1]	5110301	1			T1	36297		T13	229		T16	24821
all_values[17]	auto[0]	auto[1]	auto[0]	563654	1			T1	3716		T13	35		T16	3042
all_values[17]	auto[0]	auto[1]	auto[1]	5118457	1			T1	37452		T13	222		T16	24449
all_values[17]	auto[1]	auto[0]	auto[1]	74950	1			T1	677		T13	13		T16	439
all_values[17]	auto[1]	auto[1]	auto[1]	74792	1			T1	752		T13	13		T16	377
all_values[18]	auto[0]	auto[0]	auto[0]	2692641	1			T25	1		T1	16850		T11	290
all_values[18]	auto[0]	auto[0]	auto[1]	5108008	1			T1	37095		T13	278		T16	22724
all_values[18]	auto[0]	auto[1]	auto[0]	559117	1			T1	3554		T13	38		T16	3000
all_values[18]	auto[0]	auto[1]	auto[1]	5121265	1			T1	36832		T13	211		T16	26585
all_values[18]	auto[1]	auto[0]	auto[1]	75521	1			T1	711		T13	11		T16	410
all_values[18]	auto[1]	auto[1]	auto[1]	74172	1			T1	693		T13	11		T16	398
all_values[19]	auto[0]	auto[0]	auto[0]	2691911	1			T25	1		T1	17089		T11	290
all_values[19]	auto[0]	auto[0]	auto[1]	5129743	1			T1	37792		T13	304		T16	25901
all_values[19]	auto[0]	auto[1]	auto[0]	560080	1			T1	4069		T13	34		T16	2913
all_values[19]	auto[0]	auto[1]	auto[1]	5099601	1			T1	35333		T13	165		T16	23350
all_values[19]	auto[1]	auto[0]	auto[1]	74718	1			T1	749		T13	15		T16	392
all_values[19]	auto[1]	auto[1]	auto[1]	74671	1			T1	703		T13	8		T16	398
all_values[20]	auto[0]	auto[0]	auto[0]	2695359	1			T25	1		T1	16691		T11	290
all_values[20]	auto[0]	auto[0]	auto[1]	5113923	1			T1	38098		T13	282		T16	24509
all_values[20]	auto[0]	auto[1]	auto[0]	560803	1			T1	4001		T13	26		T16	2994
all_values[20]	auto[0]	auto[1]	auto[1]	5110543	1			T1	35498		T13	239		T16	24907
all_values[20]	auto[1]	auto[0]	auto[1]	75185	1			T1	763		T13	19		T16	417
all_values[20]	auto[1]	auto[1]	auto[1]	74911	1			T1	684		T13	9		T16	360
all_values[21]	auto[0]	auto[0]	auto[0]	2696362	1			T25	1		T1	16996		T11	290
all_values[21]	auto[0]	auto[0]	auto[1]	5126430	1			T1	37600		T13	233		T16	27476
all_values[21]	auto[0]	auto[1]	auto[0]	557997	1			T1	3618		T13	58		T16	2974
all_values[21]	auto[0]	auto[1]	auto[1]	5100094	1			T1	36057		T13	183		T16	21855
all_values[21]	auto[1]	auto[0]	auto[1]	75226	1			T1	733		T13	15		T16	418
all_values[21]	auto[1]	auto[1]	auto[1]	74615	1			T1	731		T13	12		T16	394
all_values[22]	auto[0]	auto[0]	auto[0]	2700745	1			T25	1		T1	17482		T11	290
all_values[22]	auto[0]	auto[0]	auto[1]	5140367	1			T1	37141		T13	262		T16	23981
all_values[22]	auto[0]	auto[1]	auto[0]	556568	1			T1	3841		T13	31		T16	2757
all_values[22]	auto[0]	auto[1]	auto[1]	5083612	1			T1	35900		T13	256		T16	25714
all_values[22]	auto[1]	auto[0]	auto[1]	74976	1			T1	706		T13	14		T16	411
all_values[22]	auto[1]	auto[1]	auto[1]	74456	1			T1	665		T13	12		T16	424
all_values[23]	auto[0]	auto[0]	auto[0]	2701402	1			T25	1		T1	16701		T11	290
all_values[23]	auto[0]	auto[0]	auto[1]	5104995	1			T1	38160		T13	176		T16	25198
all_values[23]	auto[0]	auto[1]	auto[0]	558925	1			T1	3881		T13	73		T16	3067
all_values[23]	auto[0]	auto[1]	auto[1]	5115527	1			T1	35542		T13	286		T16	23603
all_values[23]	auto[1]	auto[0]	auto[1]	74992	1			T1	704		T13	8		T16	420
all_values[23]	auto[1]	auto[1]	auto[1]	74883	1			T1	747		T13	16		T16	380
all_values[24]	auto[0]	auto[0]	auto[0]	2703415	1			T25	1		T1	16725		T11	290
all_values[24]	auto[0]	auto[0]	auto[1]	5105388	1			T1	39830		T13	297		T16	24083
all_values[24]	auto[0]	auto[1]	auto[0]	558782	1			T1	3607		T13	13		T16	3137
all_values[24]	auto[0]	auto[1]	auto[1]	5113520	1			T1	34123		T13	228		T16	24973
all_values[24]	auto[1]	auto[0]	auto[1]	75442	1			T1	723		T13	14		T16	408
all_values[24]	auto[1]	auto[1]	auto[1]	74177	1			T1	727		T13	8		T16	416
all_values[25]	auto[0]	auto[0]	auto[0]	2701112	1			T25	1		T1	16763		T11	290
all_values[25]	auto[0]	auto[0]	auto[1]	5141893	1			T1	37107		T13	247		T16	24817
all_values[25]	auto[0]	auto[1]	auto[0]	563025	1			T1	4551		T13	9		T16	2952
all_values[25]	auto[0]	auto[1]	auto[1]	5075283	1			T1	35891		T13	282		T16	24189
all_values[25]	auto[1]	auto[0]	auto[1]	74885	1			T1	710		T13	14		T16	433
all_values[25]	auto[1]	auto[1]	auto[1]	74526	1			T1	713		T13	14		T16	388
all_values[26]	auto[0]	auto[0]	auto[0]	2704343	1			T25	1		T1	16332		T11	290
all_values[26]	auto[0]	auto[0]	auto[1]	5102099	1			T1	35022		T13	259		T16	25109
all_values[26]	auto[0]	auto[1]	auto[0]	559029	1			T1	5426		T13	58		T16	3096
all_values[26]	auto[0]	auto[1]	auto[1]	5115599	1			T1	37492		T13	222		T16	24066
all_values[26]	auto[1]	auto[0]	auto[1]	75231	1			T1	741		T13	15		T16	371
all_values[26]	auto[1]	auto[1]	auto[1]	74423	1			T1	722		T13	10		T16	394
all_values[27]	auto[0]	auto[0]	auto[0]	2695996	1			T25	1		T1	16716		T11	290
all_values[27]	auto[0]	auto[0]	auto[1]	5118972	1			T1	39019		T13	229		T16	25926
all_values[27]	auto[0]	auto[1]	auto[0]	560731	1			T1	3700		T13	17		T16	2668
all_values[27]	auto[0]	auto[1]	auto[1]	5105291	1			T1	34894		T13	301		T16	23809
all_values[27]	auto[1]	auto[0]	auto[1]	75344	1			T1	705		T13	15		T16	441
all_values[27]	auto[1]	auto[1]	auto[1]	74390	1			T1	701		T13	7		T16	385
all_values[28]	auto[0]	auto[0]	auto[0]	2695658	1			T25	1		T1	17035		T11	290
all_values[28]	auto[0]	auto[0]	auto[1]	5097270	1			T1	34909		T13	279		T16	24245
all_values[28]	auto[0]	auto[1]	auto[0]	560523	1			T1	4344		T13	42		T16	3233
all_values[28]	auto[0]	auto[1]	auto[1]	5127065	1			T1	38050		T13	231		T16	24960
all_values[28]	auto[1]	auto[0]	auto[1]	75236	1			T1	646		T13	14		T16	379
all_values[28]	auto[1]	auto[1]	auto[1]	74972	1			T1	751		T13	10		T16	423
all_values[29]	auto[0]	auto[0]	auto[0]	2690400	1			T25	1		T1	17027		T11	290
all_values[29]	auto[0]	auto[0]	auto[1]	5135122	1			T1	36347		T13	302		T16	24369
all_values[29]	auto[0]	auto[1]	auto[0]	557918	1			T1	3724		T13	30		T16	3452
all_values[29]	auto[0]	auto[1]	auto[1]	5097279	1			T1	37201		T13	219		T16	24375
all_values[29]	auto[1]	auto[0]	auto[1]	75367	1			T1	682		T13	11		T16	407
all_values[29]	auto[1]	auto[1]	auto[1]	74638	1			T1	754		T13	10		T16	386
all_values[30]	auto[0]	auto[0]	auto[0]	2701351	1			T25	1		T1	17129		T11	290
all_values[30]	auto[0]	auto[0]	auto[1]	5123468	1			T1	36977		T13	320		T16	23950
all_values[30]	auto[0]	auto[1]	auto[0]	561381	1			T1	3887		T13	11		T16	3117
all_values[30]	auto[0]	auto[1]	auto[1]	5095056	1			T1	36285		T13	196		T16	25004
all_values[30]	auto[1]	auto[0]	auto[1]	74782	1			T1	744		T13	17		T16	388
all_values[30]	auto[1]	auto[1]	auto[1]	74686	1			T1	713		T13	11		T16	400
all_values[31]	auto[0]	auto[0]	auto[0]	2687495	1			T25	1		T1	16602		T11	290
all_values[31]	auto[0]	auto[0]	auto[1]	5116289	1			T1	34409		T13	345		T16	25023
all_values[31]	auto[0]	auto[1]	auto[0]	568631	1			T1	3991		T13	12		T16	3111
all_values[31]	auto[0]	auto[1]	auto[1]	5108728	1			T1	39300		T13	177		T16	24038
all_values[31]	auto[1]	auto[0]	auto[1]	74784	1			T1	698		T13	12		T16	390
all_values[31]	auto[1]	auto[1]	auto[1]	74797	1			T1	735		T13	10		T16	420

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal