Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[1]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[2]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[3]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[4]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[5]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[6]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[7]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[8]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[9]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[10]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[11]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[12]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[13]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[14]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[15]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[16]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[17]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[18]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[19]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[20]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[21]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[22]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[23]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[24]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[25]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[26]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[27]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[28]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[29]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[30]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[31]	13445108	1			T25	1		T1	100821		T11	426

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254547105

1

T25

32

T1

103136

T11

4479

auto[1]

175696351

1

T1

219490

T11

9153

T12

17843

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

344883435

1

T25

32

T1

241346

T11

9312

auto[1]

85360021

1

T1

812804

T11

4320

T13

7774

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320051484

1

T25

32

T1

216017

T11

9274

auto[1]

110191972

1

T1

106609

T11

4358

T13

8706

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4955706	1			T25	1		T1	18125		T11	77
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3708473	1			T1	37366		T11	144		T12	626
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1343108	1			T1	13162		T11	74		T13	50
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1653916	1			T1	1324		T13	4		T14	10
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	454197	1			T1	18269		T11	73		T13	281
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1329708	1			T1	12575		T11	58		T13	95
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4950472	1			T25	1		T1	18123		T11	90
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3710087	1			T1	36805		T11	133		T12	570
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1345909	1			T1	12977		T11	64		T13	87
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1659702	1			T1	1351		T13	2		T14	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	453133	1			T1	18940		T11	82		T13	142
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1325805	1			T1	12625		T11	57		T13	121
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4950786	1			T25	1		T1	18050		T11	58
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3709025	1			T1	36409		T11	143		T12	592
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1339163	1			T1	12620		T11	69		T13	177
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1663815	1			T1	1430		T13	1		T14	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	455774	1			T1	19435		T11	64		T13	124
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1326545	1			T1	12877		T11	92		T13	86
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4936325	1			T25	1		T1	17870		T11	65
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3708270	1			T1	36210		T11	154		T12	578
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1338400	1			T1	12566		T11	103		T13	135
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1670521	1			T1	1540		T13	2		T14	47
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	457812	1			T1	19808		T11	50		T13	149
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1333780	1			T1	12827		T11	54		T13	114
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4948738	1			T25	1		T1	18101		T11	84
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3710533	1			T1	37637		T11	128		T12	555
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1344822	1			T1	12665		T11	38		T13	134
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1654935	1			T1	1254		T14	12		T15	200
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	454188	1			T1	18367		T11	82		T13	122
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1331892	1			T1	12797		T11	94		T13	162
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4952247	1			T25	1		T1	18069		T11	65
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3705896	1			T1	36590		T11	159		T12	636
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1340294	1			T1	12981		T11	70		T13	137
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1656659	1			T1	1447		T13	5		T14	27
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	455416	1			T1	18649		T11	74		T13	159
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1334596	1			T1	13085		T11	58		T13	91
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4955459	1			T25	1		T1	17977		T11	62
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3710881	1			T1	37274		T11	160		T12	554
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1339918	1			T1	12217		T11	92		T13	92
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1660168	1			T1	1525		T13	1		T14	48
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	453086	1			T1	19293		T11	60		T13	142
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1325596	1			T1	12535		T11	52		T13	120
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4956577	1			T25	1		T1	18015		T11	82
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3698952	1			T1	36129		T11	160		T12	520
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1339581	1			T1	12905		T11	52		T13	79
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1658745	1			T1	1455		T13	2		T14	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	454850	1			T1	19401		T11	68		T13	159
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1336403	1			T1	12916		T11	64		T13	122
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4949234	1			T25	1		T1	18034		T11	74
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3709247	1			T1	36786		T11	159		T12	598
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1346597	1			T1	13240		T11	58		T13	153
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1658450	1			T1	1411		T13	6		T14	37
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	454823	1			T1	18742		T11	69		T13	105
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1326757	1			T1	12608		T11	66		T13	110
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4948845	1			T25	1		T1	18269		T11	72
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3710410	1			T1	36708		T11	173		T12	501
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1341394	1			T1	12624		T11	50		T13	163
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1662218	1			T1	1308		T13	1		T14	49
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	452692	1			T1	19201		T11	77		T13	129
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1329549	1			T1	12711		T11	54		T13	56
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4955329	1			T25	1		T1	17948		T11	71
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3704806	1			T1	37000		T11	150		T12	543
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1341141	1			T1	12513		T11	54		T13	79
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1662583	1			T1	1459		T13	4		T14	30
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	452621	1			T1	19002		T11	77		T13	198
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1328628	1			T1	12899		T11	74		T13	121
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4950228	1			T25	1		T1	18133		T11	79
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3706165	1			T1	36584		T11	138		T12	556
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1341458	1			T1	12523		T11	61		T13	135
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1666850	1			T1	1408		T14	39		T15	255
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	454640	1			T1	19564		T11	100		T13	130
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1325767	1			T1	12609		T11	48		T13	186
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4945883	1			T25	1		T1	17887		T11	68
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3712528	1			T1	36565		T11	159		T12	581
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1345283	1			T1	12745		T11	56		T13	112
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1656829	1			T1	1517		T13	2		T14	33
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	455278	1			T1	19718		T11	62		T13	167
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1329307	1			T1	12389		T11	81		T13	108
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4949959	1			T25	1		T1	18107		T11	73
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3705449	1			T1	36686		T11	128		T12	574
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1341439	1			T1	13120		T11	66		T13	86
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1660909	1			T1	1347		T13	6		T14	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	456817	1			T1	18762		T11	60		T13	145
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1330535	1			T1	12799		T11	99		T13	80
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4946802	1			T25	1		T1	17971		T11	80
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3712006	1			T1	36227		T11	135		T12	503
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1341425	1			T1	12570		T11	80		T13	179
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1658283	1			T1	1500		T13	5		T14	25
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	455916	1			T1	19664		T11	51		T13	131
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1330676	1			T1	12889		T11	80		T13	118
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4948061	1			T25	1		T1	18012		T11	80
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3709912	1			T1	37242		T11	148		T12	490
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1342536	1			T1	12696		T11	50		T13	149
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1657989	1			T1	1330		T13	3		T14	42
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	452271	1			T1	19042		T11	78		T13	109
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1334339	1			T1	12499		T11	70		T13	91
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4953663	1			T25	1		T1	18014		T11	83
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3713251	1			T1	36118		T11	165		T12	528
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1339116	1			T1	13059		T11	62		T13	161
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1658960	1			T1	1512		T13	9		T14	22
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	452819	1			T1	19553		T11	54		T13	129
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1327299	1			T1	12565		T11	62		T13	130
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4946142	1			T25	1		T1	18050		T11	79
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3714452	1			T1	36740		T11	150		T12	488
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1337988	1			T1	12664		T11	62		T13	165
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1670478	1			T1	1422		T13	4		T14	34
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	454854	1			T1	19250		T11	73		T13	118
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1321194	1			T1	12695		T11	62		T13	103
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4954314	1			T25	1		T1	18008		T11	75
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3707560	1			T1	36890		T11	164		T12	534
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1339547	1			T1	13005		T11	83		T13	195
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1660070	1			T1	1418		T13	1		T14	37
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	456673	1			T1	19210		T11	42		T13	79
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1326944	1			T1	12290		T11	62		T13	59
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4944233	1			T25	1		T1	17976		T11	71
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3721262	1			T1	37108		T11	142		T12	513
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1338142	1			T1	12519		T11	54		T13	55
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1662156	1			T1	1562		T13	6		T14	44
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	454747	1			T1	19217		T11	77		T13	195
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1324568	1			T1	12439		T11	82		T13	128
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4957049	1			T25	1		T1	17898		T11	75
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3708107	1			T1	36584		T11	152		T12	623
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1338291	1			T1	12507		T11	40		T13	140
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1658477	1			T1	1487		T13	3		T14	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	457879	1			T1	19824		T11	87		T13	170
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1325305	1			T1	12521		T11	72		T13	101
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4961524	1			T25	1		T1	17869		T11	71
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3697320	1			T1	36431		T11	152		T12	458
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1334522	1			T1	12440		T11	64		T13	74
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1665955	1			T1	1565		T13	1		T14	55
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	455686	1			T1	20222		T11	66		T13	170
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1330101	1			T1	12294		T11	73		T13	122
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4959076	1			T25	1		T1	17870		T11	71
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3701579	1			T1	36342		T11	149		T12	566
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1334732	1			T1	13005		T11	70		T13	130
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1668354	1			T1	1543		T13	5		T14	29
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	455757	1			T1	19580		T11	58		T13	144
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1325610	1			T1	12481		T11	78		T13	131
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4956874	1			T25	1		T1	18066		T11	82
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3706798	1			T1	36339		T11	155		T12	610
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1338819	1			T1	12596		T11	82		T13	78
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1666266	1			T1	1518		T13	2		T14	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	454475	1			T1	19795		T11	45		T13	145
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1321876	1			T1	12507		T11	62		T13	167
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4954356	1			T25	1		T1	17928		T11	77
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3707524	1			T1	36949		T11	132		T12	571
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1338309	1			T1	12598		T11	62		T13	64
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1665019	1			T1	1501		T13	4		T14	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	452974	1			T1	19379		T11	69		T13	259
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1326926	1			T1	12466		T11	86		T13	67
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4955892	1			T25	1		T1	18155		T11	78
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3704062	1			T1	36180		T11	143		T12	561
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1339512	1			T1	12420		T11	82		T13	151
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1661746	1			T1	1516		T13	4		T14	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	455098	1			T1	19788		T11	44		T13	136
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1328798	1			T1	12762		T11	79		T13	165
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4948852	1			T25	1		T1	18102		T11	81
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3718082	1			T1	36986		T11	130		T12	529
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1342447	1			T1	13037		T11	67		T13	122
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1657867	1			T1	1406		T13	3		T14	41
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	455643	1			T1	18554		T11	74		T13	146
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1322217	1			T1	12736		T11	74		T13	172
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4965563	1			T25	1		T1	17929		T11	72
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3699843	1			T1	36458		T11	135		T12	587
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1337583	1			T1	13094		T11	56		T13	131
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1666103	1			T1	1473		T13	7		T14	44
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	453864	1			T1	19026		T11	91		T13	130
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1322152	1			T1	12841		T11	72		T13	125
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4960869	1			T25	1		T1	18085		T11	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3705335	1			T1	36255		T11	166		T12	571
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1340650	1			T1	13054		T11	60		T13	123
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1661015	1			T1	1491		T13	2		T14	41
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	453871	1			T1	19047		T11	46		T13	136
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1323368	1			T1	12889		T11	85		T13	124
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4963404	1			T25	1		T1	18140		T11	74
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3704881	1			T1	36909		T11	150		T12	545
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1336812	1			T1	13137		T11	86		T13	148
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1657798	1			T1	1347		T13	1		T14	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	454038	1			T1	18663		T11	50		T13	141
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1328175	1			T1	12625		T11	66		T13	104
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4948118	1			T25	1		T1	18036		T11	68
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3723973	1			T1	37570		T11	171		T12	568
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1338518	1			T1	12458		T11	83		T13	88
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1663378	1			T1	1364		T13	6		T14	49
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	452072	1			T1	19205		T11	58		T13	165
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1319049	1			T1	12188		T11	46		T13	214
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4963249	1			T25	1		T1	17989		T11	77
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3704479	1			T1	36909		T11	168		T12	614
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1339051	1			T1	12669		T11	46		T13	152
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1660555	1			T1	1441		T13	6		T14	45
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	457725	1			T1	19334		T11	73		T13	93
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1320049	1			T1	12479		T11	62		T13	157

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal