Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[1]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[2]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[3]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[4]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[5]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[6]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[7]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[8]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[9]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[10]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[11]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[12]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[13]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[14]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[15]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[16]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[17]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[18]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[19]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[20]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[21]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[22]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[23]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[24]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[25]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[26]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[27]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[28]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[29]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[30]	13445108	1			T25	1		T1	100821		T11	426
bins_for_gpio_bits[31]	13445108	1			T25	1		T1	100821		T11	426

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254547105

1

T25

32

T1

103136

T11

4479

auto[1]

175696351

1

T1

219490

T11

9153

T12

17843

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254541542

1

T25

32

T1

103168

T11

4485

auto[1]

175701914

1

T1

219459

T11

9147

T12

17843

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7714230	1			T25	1		T1	30222		T11	132
bins_for_gpio_bits[0]	auto[0]	auto[1]	238293	1			T1	2403		T11	19		T13	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	238500	1			T1	2389		T11	19		T13	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	5254085	1			T1	65807		T11	256		T12	626
bins_for_gpio_bits[1]	auto[0]	auto[0]	7717883	1			T25	1		T1	30104		T11	140
bins_for_gpio_bits[1]	auto[0]	auto[1]	237999	1			T1	2352		T11	14		T13	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	238200	1			T1	2347		T11	14		T13	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	5251026	1			T1	66018		T11	258		T12	570
bins_for_gpio_bits[2]	auto[0]	auto[0]	7715628	1			T25	1		T1	29771		T11	110
bins_for_gpio_bits[2]	auto[0]	auto[1]	237990	1			T1	2339		T11	18		T13	18
bins_for_gpio_bits[2]	auto[1]	auto[0]	238136	1			T1	2329		T11	17		T13	18
bins_for_gpio_bits[2]	auto[1]	auto[1]	5253354	1			T1	66382		T11	281		T12	592
bins_for_gpio_bits[3]	auto[0]	auto[0]	7706657	1			T25	1		T1	29667		T11	150
bins_for_gpio_bits[3]	auto[0]	auto[1]	238422	1			T1	2322		T11	19		T13	18
bins_for_gpio_bits[3]	auto[1]	auto[0]	238589	1			T1	2309		T11	18		T13	18
bins_for_gpio_bits[3]	auto[1]	auto[1]	5261440	1			T1	66523		T11	239		T12	578
bins_for_gpio_bits[4]	auto[0]	auto[0]	7709061	1			T25	1		T1	29670		T11	109
bins_for_gpio_bits[4]	auto[0]	auto[1]	239282	1			T1	2356		T11	13		T13	20
bins_for_gpio_bits[4]	auto[1]	auto[0]	239434	1			T1	2350		T11	13		T13	20
bins_for_gpio_bits[4]	auto[1]	auto[1]	5257331	1			T1	66445		T11	291		T12	555
bins_for_gpio_bits[5]	auto[0]	auto[0]	7710791	1			T25	1		T1	30084		T11	119
bins_for_gpio_bits[5]	auto[0]	auto[1]	238239	1			T1	2421		T11	16		T13	13
bins_for_gpio_bits[5]	auto[1]	auto[0]	238409	1			T1	2413		T11	16		T13	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	5257669	1			T1	65903		T11	275		T12	636
bins_for_gpio_bits[6]	auto[0]	auto[0]	7717368	1			T25	1		T1	29449		T11	135
bins_for_gpio_bits[6]	auto[0]	auto[1]	238039	1			T1	2278		T11	19		T13	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	238177	1			T1	2270		T11	19		T13	14
bins_for_gpio_bits[6]	auto[1]	auto[1]	5251524	1			T1	66824		T11	253		T12	554
bins_for_gpio_bits[7]	auto[0]	auto[0]	7715792	1			T25	1		T1	30073		T11	116
bins_for_gpio_bits[7]	auto[0]	auto[1]	238940	1			T1	2315		T11	18		T13	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	239111	1			T1	2302		T11	18		T13	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	5251265	1			T1	66131		T11	274		T12	520
bins_for_gpio_bits[8]	auto[0]	auto[0]	7715590	1			T25	1		T1	30334		T11	117
bins_for_gpio_bits[8]	auto[0]	auto[1]	238551	1			T1	2360		T11	15		T13	20
bins_for_gpio_bits[8]	auto[1]	auto[0]	238691	1			T1	2351		T11	15		T13	20
bins_for_gpio_bits[8]	auto[1]	auto[1]	5252276	1			T1	65776		T11	279		T12	598
bins_for_gpio_bits[9]	auto[0]	auto[0]	7713683	1			T25	1		T1	29876		T11	108
bins_for_gpio_bits[9]	auto[0]	auto[1]	238635	1			T1	2333		T11	14		T13	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	238774	1			T1	2325		T11	14		T13	20
bins_for_gpio_bits[9]	auto[1]	auto[1]	5254016	1			T1	66287		T11	290		T12	501
bins_for_gpio_bits[10]	auto[0]	auto[0]	7720129	1			T25	1		T1	29612		T11	113
bins_for_gpio_bits[10]	auto[0]	auto[1]	238731	1			T1	2313		T11	12		T13	15
bins_for_gpio_bits[10]	auto[1]	auto[0]	238924	1			T1	2308		T11	12		T13	15
bins_for_gpio_bits[10]	auto[1]	auto[1]	5247324	1			T1	66588		T11	289		T12	543
bins_for_gpio_bits[11]	auto[0]	auto[0]	7720610	1			T25	1		T1	29818		T11	123
bins_for_gpio_bits[11]	auto[0]	auto[1]	237808	1			T1	2262		T11	18		T13	22
bins_for_gpio_bits[11]	auto[1]	auto[0]	237926	1			T1	2246		T11	17		T13	22
bins_for_gpio_bits[11]	auto[1]	auto[1]	5248764	1			T1	66495		T11	268		T12	556
bins_for_gpio_bits[12]	auto[0]	auto[0]	7708893	1			T25	1		T1	29861		T11	108
bins_for_gpio_bits[12]	auto[0]	auto[1]	238913	1			T1	2296		T11	16		T13	16
bins_for_gpio_bits[12]	auto[1]	auto[0]	239102	1			T1	2288		T11	16		T13	16
bins_for_gpio_bits[12]	auto[1]	auto[1]	5258200	1			T1	66376		T11	286		T12	581
bins_for_gpio_bits[13]	auto[0]	auto[0]	7713180	1			T25	1		T1	30209		T11	120
bins_for_gpio_bits[13]	auto[0]	auto[1]	238952	1			T1	2377		T11	19		T13	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	239127	1			T1	2365		T11	19		T13	15
bins_for_gpio_bits[13]	auto[1]	auto[1]	5253849	1			T1	65870		T11	268		T12	574
bins_for_gpio_bits[14]	auto[0]	auto[0]	7707876	1			T25	1		T1	29757		T11	144
bins_for_gpio_bits[14]	auto[0]	auto[1]	238450	1			T1	2291		T11	16		T13	17
bins_for_gpio_bits[14]	auto[1]	auto[0]	238634	1			T1	2284		T11	16		T13	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5260148	1			T1	66489		T11	250		T12	503
bins_for_gpio_bits[15]	auto[0]	auto[0]	7709493	1			T25	1		T1	29728		T11	116
bins_for_gpio_bits[15]	auto[0]	auto[1]	238920	1			T1	2320		T11	14		T13	21
bins_for_gpio_bits[15]	auto[1]	auto[0]	239093	1			T1	2310		T11	14		T13	21
bins_for_gpio_bits[15]	auto[1]	auto[1]	5257602	1			T1	66463		T11	282		T12	490
bins_for_gpio_bits[16]	auto[0]	auto[0]	7712989	1			T25	1		T1	30229		T11	127
bins_for_gpio_bits[16]	auto[0]	auto[1]	238572	1			T1	2367		T11	18		T13	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	238750	1			T1	2356		T11	18		T13	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	5254797	1			T1	65869		T11	263		T12	528
bins_for_gpio_bits[17]	auto[0]	auto[0]	7715637	1			T25	1		T1	29811		T11	127
bins_for_gpio_bits[17]	auto[0]	auto[1]	238783	1			T1	2331		T11	14		T13	23
bins_for_gpio_bits[17]	auto[1]	auto[0]	238971	1			T1	2325		T11	14		T13	23
bins_for_gpio_bits[17]	auto[1]	auto[1]	5251717	1			T1	66354		T11	271		T12	488
bins_for_gpio_bits[18]	auto[0]	auto[0]	7715346	1			T25	1		T1	30112		T11	142
bins_for_gpio_bits[18]	auto[0]	auto[1]	238417	1			T1	2329		T11	17		T13	20
bins_for_gpio_bits[18]	auto[1]	auto[0]	238585	1			T1	2319		T11	16		T13	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	5252760	1			T1	66061		T11	251		T12	534
bins_for_gpio_bits[19]	auto[0]	auto[0]	7706204	1			T25	1		T1	29776		T11	110
bins_for_gpio_bits[19]	auto[0]	auto[1]	238158	1			T1	2288		T11	15		T13	13
bins_for_gpio_bits[19]	auto[1]	auto[0]	238327	1			T1	2281		T11	15		T13	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	5262419	1			T1	66476		T11	286		T12	513
bins_for_gpio_bits[20]	auto[0]	auto[0]	7715057	1			T25	1		T1	29611		T11	101
bins_for_gpio_bits[20]	auto[0]	auto[1]	238573	1			T1	2296		T11	14		T13	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	238760	1			T1	2281		T11	14		T13	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	5252718	1			T1	66633		T11	297		T12	623
bins_for_gpio_bits[21]	auto[0]	auto[0]	7723346	1			T25	1		T1	29580		T11	117
bins_for_gpio_bits[21]	auto[0]	auto[1]	238515	1			T1	2310		T11	18		T13	12
bins_for_gpio_bits[21]	auto[1]	auto[0]	238655	1			T1	2294		T11	18		T13	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	5244592	1			T1	66637		T11	273		T12	458
bins_for_gpio_bits[22]	auto[0]	auto[0]	7723359	1			T25	1		T1	30109		T11	124
bins_for_gpio_bits[22]	auto[0]	auto[1]	238632	1			T1	2319		T11	17		T13	20
bins_for_gpio_bits[22]	auto[1]	auto[0]	238803	1			T1	2309		T11	17		T13	20
bins_for_gpio_bits[22]	auto[1]	auto[1]	5244314	1			T1	66084		T11	268		T12	566
bins_for_gpio_bits[23]	auto[0]	auto[0]	7723242	1			T25	1		T1	29909		T11	144
bins_for_gpio_bits[23]	auto[0]	auto[1]	238520	1			T1	2277		T11	20		T13	18
bins_for_gpio_bits[23]	auto[1]	auto[0]	238717	1			T1	2271		T11	20		T13	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	5244629	1			T1	66364		T11	242		T12	610
bins_for_gpio_bits[24]	auto[0]	auto[0]	7718786	1			T25	1		T1	29730		T11	121
bins_for_gpio_bits[24]	auto[0]	auto[1]	238686	1			T1	2307		T11	18		T13	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	238898	1			T1	2297		T11	18		T13	7
bins_for_gpio_bits[24]	auto[1]	auto[1]	5248738	1			T1	66487		T11	269		T12	571
bins_for_gpio_bits[25]	auto[0]	auto[0]	7718130	1			T25	1		T1	29810		T11	140
bins_for_gpio_bits[25]	auto[0]	auto[1]	238847	1			T1	2291		T11	20		T13	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	239020	1			T1	2281		T11	20		T13	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	5249111	1			T1	66439		T11	246		T12	561
bins_for_gpio_bits[26]	auto[0]	auto[0]	7710427	1			T25	1		T1	30211		T11	134
bins_for_gpio_bits[26]	auto[0]	auto[1]	238548	1			T1	2345		T11	15		T13	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	238739	1			T1	2334		T11	14		T13	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	5257394	1			T1	65931		T11	263		T12	529
bins_for_gpio_bits[27]	auto[0]	auto[0]	7730694	1			T25	1		T1	30143		T11	109
bins_for_gpio_bits[27]	auto[0]	auto[1]	238359	1			T1	2362		T11	19		T13	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	238555	1			T1	2353		T11	19		T13	16
bins_for_gpio_bits[27]	auto[1]	auto[1]	5237500	1			T1	65963		T11	279		T12	587
bins_for_gpio_bits[28]	auto[0]	auto[0]	7723747	1			T25	1		T1	30325		T11	113
bins_for_gpio_bits[28]	auto[0]	auto[1]	238629	1			T1	2313		T11	16		T13	16
bins_for_gpio_bits[28]	auto[1]	auto[0]	238787	1			T1	2305		T11	16		T13	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5243945	1			T1	65878		T11	281		T12	571
bins_for_gpio_bits[29]	auto[0]	auto[0]	7719328	1			T25	1		T1	30296		T11	142
bins_for_gpio_bits[29]	auto[0]	auto[1]	238516	1			T1	2344		T11	18		T13	16
bins_for_gpio_bits[29]	auto[1]	auto[0]	238686	1			T1	2328		T11	18		T13	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	5248578	1			T1	65853		T11	248		T12	545
bins_for_gpio_bits[30]	auto[0]	auto[0]	7711948	1			T25	1		T1	29503		T11	132
bins_for_gpio_bits[30]	auto[0]	auto[1]	237853	1			T1	2365		T11	20		T13	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	238066	1			T1	2355		T11	19		T13	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	5257241	1			T1	66598		T11	255		T12	568
bins_for_gpio_bits[31]	auto[0]	auto[0]	7724887	1			T25	1		T1	29780		T11	111
bins_for_gpio_bits[31]	auto[0]	auto[1]	237779	1			T1	2329		T11	12		T13	18
bins_for_gpio_bits[31]	auto[1]	auto[0]	237968	1			T1	2319		T11	12		T13	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	5244474	1			T1	66393		T11	291		T12	614