Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884105 |
1 |
|
|
T25 |
1 |
|
T1 |
53920 |
|
T11 |
290 |
| auto[1] |
5746619 |
1 |
|
|
T1 |
41815 |
|
T13 |
263 |
|
T16 |
28669 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900032 |
1 |
|
|
T25 |
1 |
|
T1 |
90733 |
|
T11 |
290 |
| auto[1] |
730692 |
1 |
|
|
T1 |
5002 |
|
T13 |
10 |
|
T16 |
3200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903928 |
1 |
|
|
T25 |
1 |
|
T1 |
54640 |
|
T11 |
290 |
| auto[1] |
5726796 |
1 |
|
|
T1 |
41095 |
|
T13 |
335 |
|
T16 |
27078 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2504631 |
1 |
|
|
T1 |
18507 |
|
T13 |
160 |
|
T16 |
12097 |
| auto[1] |
auto[0] |
auto[1] |
366925 |
1 |
|
|
T1 |
2575 |
|
T13 |
5 |
|
T16 |
1647 |
| auto[1] |
auto[1] |
auto[0] |
2491473 |
1 |
|
|
T1 |
17586 |
|
T13 |
165 |
|
T16 |
11781 |
| auto[1] |
auto[1] |
auto[1] |
363767 |
1 |
|
|
T1 |
2427 |
|
T13 |
5 |
|
T16 |
1553 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905825 |
1 |
|
|
T25 |
1 |
|
T1 |
54161 |
|
T11 |
290 |
| auto[1] |
5724899 |
1 |
|
|
T1 |
41574 |
|
T13 |
334 |
|
T16 |
27827 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900977 |
1 |
|
|
T25 |
1 |
|
T1 |
91064 |
|
T11 |
290 |
| auto[1] |
729747 |
1 |
|
|
T1 |
4671 |
|
T13 |
10 |
|
T16 |
3344 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909402 |
1 |
|
|
T25 |
1 |
|
T1 |
55572 |
|
T11 |
290 |
| auto[1] |
5721322 |
1 |
|
|
T1 |
40163 |
|
T13 |
312 |
|
T16 |
28461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2499068 |
1 |
|
|
T1 |
17951 |
|
T13 |
156 |
|
T16 |
12595 |
| auto[1] |
auto[0] |
auto[1] |
365483 |
1 |
|
|
T1 |
2333 |
|
T13 |
5 |
|
T16 |
1705 |
| auto[1] |
auto[1] |
auto[0] |
2492507 |
1 |
|
|
T1 |
17541 |
|
T13 |
146 |
|
T16 |
12522 |
| auto[1] |
auto[1] |
auto[1] |
364264 |
1 |
|
|
T1 |
2338 |
|
T13 |
5 |
|
T16 |
1639 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889875 |
1 |
|
|
T25 |
1 |
|
T1 |
53883 |
|
T11 |
290 |
| auto[1] |
5740849 |
1 |
|
|
T1 |
41852 |
|
T13 |
241 |
|
T16 |
29436 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898152 |
1 |
|
|
T25 |
1 |
|
T1 |
90948 |
|
T11 |
290 |
| auto[1] |
732572 |
1 |
|
|
T1 |
4787 |
|
T13 |
15 |
|
T16 |
3509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884620 |
1 |
|
|
T25 |
1 |
|
T1 |
54729 |
|
T11 |
290 |
| auto[1] |
5746104 |
1 |
|
|
T1 |
41006 |
|
T13 |
436 |
|
T16 |
29564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2515006 |
1 |
|
|
T1 |
17801 |
|
T13 |
261 |
|
T16 |
11792 |
| auto[1] |
auto[0] |
auto[1] |
367618 |
1 |
|
|
T1 |
2244 |
|
T13 |
9 |
|
T16 |
1505 |
| auto[1] |
auto[1] |
auto[0] |
2498526 |
1 |
|
|
T1 |
18418 |
|
T13 |
160 |
|
T16 |
14263 |
| auto[1] |
auto[1] |
auto[1] |
364954 |
1 |
|
|
T1 |
2543 |
|
T13 |
6 |
|
T16 |
2004 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895044 |
1 |
|
|
T25 |
1 |
|
T1 |
54218 |
|
T11 |
290 |
| auto[1] |
5735680 |
1 |
|
|
T1 |
41517 |
|
T13 |
210 |
|
T16 |
26896 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897388 |
1 |
|
|
T25 |
1 |
|
T1 |
90888 |
|
T11 |
290 |
| auto[1] |
733336 |
1 |
|
|
T1 |
4847 |
|
T13 |
14 |
|
T16 |
3324 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7886069 |
1 |
|
|
T25 |
1 |
|
T1 |
53730 |
|
T11 |
290 |
| auto[1] |
5744655 |
1 |
|
|
T1 |
42005 |
|
T13 |
394 |
|
T16 |
28032 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2509108 |
1 |
|
|
T1 |
18338 |
|
T13 |
261 |
|
T16 |
12614 |
| auto[1] |
auto[0] |
auto[1] |
367141 |
1 |
|
|
T1 |
2494 |
|
T13 |
11 |
|
T16 |
1718 |
| auto[1] |
auto[1] |
auto[0] |
2502211 |
1 |
|
|
T1 |
18820 |
|
T13 |
119 |
|
T16 |
12094 |
| auto[1] |
auto[1] |
auto[1] |
366195 |
1 |
|
|
T1 |
2353 |
|
T13 |
3 |
|
T16 |
1606 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869842 |
1 |
|
|
T25 |
1 |
|
T1 |
53800 |
|
T11 |
290 |
| auto[1] |
5760882 |
1 |
|
|
T1 |
41935 |
|
T13 |
259 |
|
T16 |
27128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897003 |
1 |
|
|
T25 |
1 |
|
T1 |
90909 |
|
T11 |
290 |
| auto[1] |
733721 |
1 |
|
|
T1 |
4826 |
|
T13 |
9 |
|
T16 |
3183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878424 |
1 |
|
|
T25 |
1 |
|
T1 |
54522 |
|
T11 |
290 |
| auto[1] |
5752300 |
1 |
|
|
T1 |
41213 |
|
T13 |
281 |
|
T16 |
27761 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2502450 |
1 |
|
|
T1 |
18901 |
|
T13 |
141 |
|
T16 |
12679 |
| auto[1] |
auto[0] |
auto[1] |
366685 |
1 |
|
|
T1 |
2512 |
|
T13 |
2 |
|
T16 |
1705 |
| auto[1] |
auto[1] |
auto[0] |
2516129 |
1 |
|
|
T1 |
17486 |
|
T13 |
131 |
|
T16 |
11899 |
| auto[1] |
auto[1] |
auto[1] |
367036 |
1 |
|
|
T1 |
2314 |
|
T13 |
7 |
|
T16 |
1478 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869917 |
1 |
|
|
T25 |
1 |
|
T1 |
55544 |
|
T11 |
290 |
| auto[1] |
5760807 |
1 |
|
|
T1 |
40191 |
|
T13 |
221 |
|
T16 |
28070 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894244 |
1 |
|
|
T25 |
1 |
|
T1 |
90499 |
|
T11 |
290 |
| auto[1] |
736480 |
1 |
|
|
T1 |
5236 |
|
T13 |
14 |
|
T16 |
3346 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873256 |
1 |
|
|
T25 |
1 |
|
T1 |
52276 |
|
T11 |
290 |
| auto[1] |
5757468 |
1 |
|
|
T1 |
43459 |
|
T13 |
337 |
|
T16 |
28527 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2500785 |
1 |
|
|
T1 |
19524 |
|
T13 |
223 |
|
T16 |
12865 |
| auto[1] |
auto[0] |
auto[1] |
366269 |
1 |
|
|
T1 |
2759 |
|
T13 |
9 |
|
T16 |
1776 |
| auto[1] |
auto[1] |
auto[0] |
2520203 |
1 |
|
|
T1 |
18699 |
|
T13 |
100 |
|
T16 |
12316 |
| auto[1] |
auto[1] |
auto[1] |
370211 |
1 |
|
|
T1 |
2477 |
|
T13 |
5 |
|
T16 |
1570 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910299 |
1 |
|
|
T25 |
1 |
|
T1 |
55244 |
|
T11 |
290 |
| auto[1] |
5720425 |
1 |
|
|
T1 |
40491 |
|
T13 |
257 |
|
T16 |
28188 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12892879 |
1 |
|
|
T25 |
1 |
|
T1 |
91102 |
|
T11 |
290 |
| auto[1] |
737845 |
1 |
|
|
T1 |
4633 |
|
T13 |
10 |
|
T16 |
3233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7860791 |
1 |
|
|
T25 |
1 |
|
T1 |
55593 |
|
T11 |
290 |
| auto[1] |
5769933 |
1 |
|
|
T1 |
40142 |
|
T13 |
322 |
|
T16 |
27980 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2522832 |
1 |
|
|
T1 |
18987 |
|
T13 |
176 |
|
T16 |
12426 |
| auto[1] |
auto[0] |
auto[1] |
370386 |
1 |
|
|
T1 |
2526 |
|
T13 |
5 |
|
T16 |
1623 |
| auto[1] |
auto[1] |
auto[0] |
2509256 |
1 |
|
|
T1 |
16522 |
|
T13 |
136 |
|
T16 |
12321 |
| auto[1] |
auto[1] |
auto[1] |
367459 |
1 |
|
|
T1 |
2107 |
|
T13 |
5 |
|
T16 |
1610 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887012 |
1 |
|
|
T25 |
1 |
|
T1 |
53213 |
|
T11 |
290 |
| auto[1] |
5743712 |
1 |
|
|
T1 |
42522 |
|
T13 |
179 |
|
T16 |
28978 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898364 |
1 |
|
|
T25 |
1 |
|
T1 |
90994 |
|
T11 |
290 |
| auto[1] |
732360 |
1 |
|
|
T1 |
4741 |
|
T13 |
16 |
|
T16 |
3483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900168 |
1 |
|
|
T25 |
1 |
|
T1 |
54858 |
|
T11 |
290 |
| auto[1] |
5730556 |
1 |
|
|
T1 |
40877 |
|
T13 |
391 |
|
T16 |
29599 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2501263 |
1 |
|
|
T1 |
16990 |
|
T13 |
273 |
|
T16 |
11815 |
| auto[1] |
auto[0] |
auto[1] |
365940 |
1 |
|
|
T1 |
2211 |
|
T13 |
11 |
|
T16 |
1582 |
| auto[1] |
auto[1] |
auto[0] |
2496933 |
1 |
|
|
T1 |
19146 |
|
T13 |
102 |
|
T16 |
14301 |
| auto[1] |
auto[1] |
auto[1] |
366420 |
1 |
|
|
T1 |
2530 |
|
T13 |
5 |
|
T16 |
1901 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880038 |
1 |
|
|
T25 |
1 |
|
T1 |
56810 |
|
T11 |
290 |
| auto[1] |
5750686 |
1 |
|
|
T1 |
38925 |
|
T13 |
184 |
|
T16 |
28119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901249 |
1 |
|
|
T25 |
1 |
|
T1 |
91083 |
|
T11 |
290 |
| auto[1] |
729475 |
1 |
|
|
T1 |
4652 |
|
T13 |
8 |
|
T16 |
3099 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905898 |
1 |
|
|
T25 |
1 |
|
T1 |
55421 |
|
T11 |
290 |
| auto[1] |
5724826 |
1 |
|
|
T1 |
40314 |
|
T13 |
255 |
|
T16 |
26804 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2498537 |
1 |
|
|
T1 |
18401 |
|
T13 |
158 |
|
T16 |
12155 |
| auto[1] |
auto[0] |
auto[1] |
364801 |
1 |
|
|
T1 |
2364 |
|
T13 |
6 |
|
T16 |
1613 |
| auto[1] |
auto[1] |
auto[0] |
2496814 |
1 |
|
|
T1 |
17261 |
|
T13 |
89 |
|
T16 |
11550 |
| auto[1] |
auto[1] |
auto[1] |
364674 |
1 |
|
|
T1 |
2288 |
|
T13 |
2 |
|
T16 |
1486 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873821 |
1 |
|
|
T25 |
1 |
|
T1 |
53815 |
|
T11 |
290 |
| auto[1] |
5756903 |
1 |
|
|
T1 |
41920 |
|
T13 |
270 |
|
T16 |
27868 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12902592 |
1 |
|
|
T25 |
1 |
|
T1 |
90951 |
|
T11 |
290 |
| auto[1] |
728132 |
1 |
|
|
T1 |
4784 |
|
T13 |
21 |
|
T16 |
3201 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910780 |
1 |
|
|
T25 |
1 |
|
T1 |
54759 |
|
T11 |
290 |
| auto[1] |
5719944 |
1 |
|
|
T1 |
40976 |
|
T13 |
348 |
|
T16 |
27636 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2502514 |
1 |
|
|
T1 |
18335 |
|
T13 |
156 |
|
T16 |
12365 |
| auto[1] |
auto[0] |
auto[1] |
363981 |
1 |
|
|
T1 |
2426 |
|
T13 |
7 |
|
T16 |
1636 |
| auto[1] |
auto[1] |
auto[0] |
2489298 |
1 |
|
|
T1 |
17857 |
|
T13 |
171 |
|
T16 |
12070 |
| auto[1] |
auto[1] |
auto[1] |
364151 |
1 |
|
|
T1 |
2358 |
|
T13 |
14 |
|
T16 |
1565 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876170 |
1 |
|
|
T25 |
1 |
|
T1 |
54656 |
|
T11 |
290 |
| auto[1] |
5754554 |
1 |
|
|
T1 |
41079 |
|
T13 |
260 |
|
T16 |
29983 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898271 |
1 |
|
|
T25 |
1 |
|
T1 |
90828 |
|
T11 |
290 |
| auto[1] |
732453 |
1 |
|
|
T1 |
4907 |
|
T13 |
17 |
|
T16 |
3265 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892642 |
1 |
|
|
T25 |
1 |
|
T1 |
53674 |
|
T11 |
290 |
| auto[1] |
5738082 |
1 |
|
|
T1 |
42061 |
|
T13 |
355 |
|
T16 |
27791 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2498936 |
1 |
|
|
T1 |
17921 |
|
T13 |
194 |
|
T16 |
11798 |
| auto[1] |
auto[0] |
auto[1] |
365360 |
1 |
|
|
T1 |
2269 |
|
T13 |
8 |
|
T16 |
1452 |
| auto[1] |
auto[1] |
auto[0] |
2506693 |
1 |
|
|
T1 |
19233 |
|
T13 |
144 |
|
T16 |
12728 |
| auto[1] |
auto[1] |
auto[1] |
367093 |
1 |
|
|
T1 |
2638 |
|
T13 |
9 |
|
T16 |
1813 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896372 |
1 |
|
|
T25 |
1 |
|
T1 |
55630 |
|
T11 |
290 |
| auto[1] |
5734352 |
1 |
|
|
T1 |
40105 |
|
T13 |
207 |
|
T16 |
26661 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894151 |
1 |
|
|
T25 |
1 |
|
T1 |
90949 |
|
T11 |
290 |
| auto[1] |
736573 |
1 |
|
|
T1 |
4786 |
|
T13 |
7 |
|
T16 |
3431 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873330 |
1 |
|
|
T25 |
1 |
|
T1 |
55520 |
|
T11 |
290 |
| auto[1] |
5757394 |
1 |
|
|
T1 |
40215 |
|
T13 |
265 |
|
T16 |
28639 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2526055 |
1 |
|
|
T1 |
17283 |
|
T13 |
175 |
|
T16 |
12693 |
| auto[1] |
auto[0] |
auto[1] |
370741 |
1 |
|
|
T1 |
2267 |
|
T13 |
7 |
|
T16 |
1815 |
| auto[1] |
auto[1] |
auto[0] |
2494766 |
1 |
|
|
T1 |
18146 |
|
T13 |
83 |
|
T16 |
12515 |
| auto[1] |
auto[1] |
auto[1] |
365832 |
1 |
|
|
T1 |
2519 |
|
T16 |
1616 |
|
T19 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870356 |
1 |
|
|
T25 |
1 |
|
T1 |
56340 |
|
T11 |
290 |
| auto[1] |
5760368 |
1 |
|
|
T1 |
39395 |
|
T13 |
307 |
|
T16 |
26501 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901287 |
1 |
|
|
T25 |
1 |
|
T1 |
90715 |
|
T11 |
290 |
| auto[1] |
729437 |
1 |
|
|
T1 |
5020 |
|
T13 |
13 |
|
T16 |
3317 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7907045 |
1 |
|
|
T25 |
1 |
|
T1 |
54205 |
|
T11 |
290 |
| auto[1] |
5723679 |
1 |
|
|
T1 |
41530 |
|
T13 |
375 |
|
T16 |
27967 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2497877 |
1 |
|
|
T1 |
19471 |
|
T13 |
167 |
|
T16 |
12671 |
| auto[1] |
auto[0] |
auto[1] |
364552 |
1 |
|
|
T1 |
2793 |
|
T13 |
5 |
|
T16 |
1671 |
| auto[1] |
auto[1] |
auto[0] |
2496365 |
1 |
|
|
T1 |
17039 |
|
T13 |
195 |
|
T16 |
11979 |
| auto[1] |
auto[1] |
auto[1] |
364885 |
1 |
|
|
T1 |
2227 |
|
T13 |
8 |
|
T16 |
1646 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884467 |
1 |
|
|
T25 |
1 |
|
T1 |
55552 |
|
T11 |
290 |
| auto[1] |
5746257 |
1 |
|
|
T1 |
40183 |
|
T13 |
274 |
|
T16 |
28261 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898115 |
1 |
|
|
T25 |
1 |
|
T1 |
90455 |
|
T11 |
290 |
| auto[1] |
732609 |
1 |
|
|
T1 |
5280 |
|
T13 |
8 |
|
T16 |
3118 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882942 |
1 |
|
|
T25 |
1 |
|
T1 |
52449 |
|
T11 |
290 |
| auto[1] |
5747782 |
1 |
|
|
T1 |
43286 |
|
T13 |
243 |
|
T16 |
27272 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2500665 |
1 |
|
|
T1 |
19820 |
|
T13 |
116 |
|
T16 |
12547 |
| auto[1] |
auto[0] |
auto[1] |
365458 |
1 |
|
|
T1 |
2747 |
|
T13 |
3 |
|
T16 |
1662 |
| auto[1] |
auto[1] |
auto[0] |
2514508 |
1 |
|
|
T1 |
18186 |
|
T13 |
119 |
|
T16 |
11607 |
| auto[1] |
auto[1] |
auto[1] |
367151 |
1 |
|
|
T1 |
2533 |
|
T13 |
5 |
|
T16 |
1456 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898018 |
1 |
|
|
T25 |
1 |
|
T1 |
55329 |
|
T11 |
290 |
| auto[1] |
5732706 |
1 |
|
|
T1 |
40406 |
|
T13 |
253 |
|
T16 |
25223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894376 |
1 |
|
|
T25 |
1 |
|
T1 |
91122 |
|
T11 |
290 |
| auto[1] |
736348 |
1 |
|
|
T1 |
4613 |
|
T13 |
6 |
|
T16 |
3374 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873378 |
1 |
|
|
T25 |
1 |
|
T1 |
55235 |
|
T11 |
290 |
| auto[1] |
5757346 |
1 |
|
|
T1 |
40500 |
|
T13 |
265 |
|
T16 |
28390 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2513903 |
1 |
|
|
T1 |
18811 |
|
T13 |
149 |
|
T16 |
13806 |
| auto[1] |
auto[0] |
auto[1] |
369250 |
1 |
|
|
T1 |
2634 |
|
T13 |
2 |
|
T16 |
1932 |
| auto[1] |
auto[1] |
auto[0] |
2507095 |
1 |
|
|
T1 |
17076 |
|
T13 |
110 |
|
T16 |
11210 |
| auto[1] |
auto[1] |
auto[1] |
367098 |
1 |
|
|
T1 |
1979 |
|
T13 |
4 |
|
T16 |
1442 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7916088 |
1 |
|
|
T25 |
1 |
|
T1 |
55329 |
|
T11 |
290 |
| auto[1] |
5714636 |
1 |
|
|
T1 |
40406 |
|
T13 |
299 |
|
T16 |
28895 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900503 |
1 |
|
|
T25 |
1 |
|
T1 |
90771 |
|
T11 |
290 |
| auto[1] |
730221 |
1 |
|
|
T1 |
4964 |
|
T13 |
9 |
|
T16 |
3500 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910043 |
1 |
|
|
T25 |
1 |
|
T1 |
53358 |
|
T11 |
290 |
| auto[1] |
5720681 |
1 |
|
|
T1 |
42377 |
|
T13 |
281 |
|
T16 |
28991 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518677 |
1 |
|
|
T1 |
18187 |
|
T13 |
159 |
|
T16 |
11715 |
| auto[1] |
auto[0] |
auto[1] |
369275 |
1 |
|
|
T1 |
2372 |
|
T13 |
3 |
|
T16 |
1574 |
| auto[1] |
auto[1] |
auto[0] |
2471783 |
1 |
|
|
T1 |
19226 |
|
T13 |
113 |
|
T16 |
13776 |
| auto[1] |
auto[1] |
auto[1] |
360946 |
1 |
|
|
T1 |
2592 |
|
T13 |
6 |
|
T16 |
1926 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881389 |
1 |
|
|
T25 |
1 |
|
T1 |
55565 |
|
T11 |
290 |
| auto[1] |
5749335 |
1 |
|
|
T1 |
40170 |
|
T13 |
375 |
|
T16 |
27050 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900187 |
1 |
|
|
T25 |
1 |
|
T1 |
90880 |
|
T11 |
290 |
| auto[1] |
730537 |
1 |
|
|
T1 |
4855 |
|
T13 |
6 |
|
T16 |
3548 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911884 |
1 |
|
|
T25 |
1 |
|
T1 |
54260 |
|
T11 |
290 |
| auto[1] |
5718840 |
1 |
|
|
T1 |
41475 |
|
T13 |
231 |
|
T16 |
29083 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2490068 |
1 |
|
|
T1 |
18193 |
|
T13 |
85 |
|
T16 |
13007 |
| auto[1] |
auto[0] |
auto[1] |
364198 |
1 |
|
|
T1 |
2415 |
|
T16 |
1821 |
|
T19 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2498235 |
1 |
|
|
T1 |
18427 |
|
T13 |
140 |
|
T16 |
12528 |
| auto[1] |
auto[1] |
auto[1] |
366339 |
1 |
|
|
T1 |
2440 |
|
T13 |
6 |
|
T16 |
1727 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884245 |
1 |
|
|
T25 |
1 |
|
T1 |
57278 |
|
T11 |
290 |
| auto[1] |
5746479 |
1 |
|
|
T1 |
38457 |
|
T13 |
249 |
|
T16 |
28526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897535 |
1 |
|
|
T25 |
1 |
|
T1 |
90696 |
|
T11 |
290 |
| auto[1] |
733189 |
1 |
|
|
T1 |
5039 |
|
T13 |
7 |
|
T16 |
2892 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879136 |
1 |
|
|
T25 |
1 |
|
T1 |
53257 |
|
T11 |
290 |
| auto[1] |
5751588 |
1 |
|
|
T1 |
42478 |
|
T13 |
391 |
|
T16 |
25613 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2504251 |
1 |
|
|
T1 |
19612 |
|
T13 |
211 |
|
T16 |
11110 |
| auto[1] |
auto[0] |
auto[1] |
365334 |
1 |
|
|
T1 |
2703 |
|
T13 |
2 |
|
T16 |
1339 |
| auto[1] |
auto[1] |
auto[0] |
2514148 |
1 |
|
|
T1 |
17827 |
|
T13 |
173 |
|
T16 |
11611 |
| auto[1] |
auto[1] |
auto[1] |
367855 |
1 |
|
|
T1 |
2336 |
|
T13 |
5 |
|
T16 |
1553 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7917890 |
1 |
|
|
T25 |
1 |
|
T1 |
54580 |
|
T11 |
290 |
| auto[1] |
5712834 |
1 |
|
|
T1 |
41155 |
|
T13 |
305 |
|
T16 |
27529 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12896674 |
1 |
|
|
T25 |
1 |
|
T1 |
91110 |
|
T11 |
290 |
| auto[1] |
734050 |
1 |
|
|
T1 |
4625 |
|
T13 |
10 |
|
T16 |
3055 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7875323 |
1 |
|
|
T25 |
1 |
|
T1 |
56392 |
|
T11 |
290 |
| auto[1] |
5755401 |
1 |
|
|
T1 |
39343 |
|
T13 |
308 |
|
T16 |
27000 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2531149 |
1 |
|
|
T1 |
17755 |
|
T13 |
114 |
|
T16 |
12072 |
| auto[1] |
auto[0] |
auto[1] |
370219 |
1 |
|
|
T1 |
2410 |
|
T13 |
3 |
|
T16 |
1541 |
| auto[1] |
auto[1] |
auto[0] |
2490202 |
1 |
|
|
T1 |
16963 |
|
T13 |
184 |
|
T16 |
11873 |
| auto[1] |
auto[1] |
auto[1] |
363831 |
1 |
|
|
T1 |
2215 |
|
T13 |
7 |
|
T16 |
1514 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881673 |
1 |
|
|
T25 |
1 |
|
T1 |
52095 |
|
T11 |
290 |
| auto[1] |
5749051 |
1 |
|
|
T1 |
43640 |
|
T13 |
290 |
|
T16 |
27556 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897848 |
1 |
|
|
T25 |
1 |
|
T1 |
91281 |
|
T11 |
290 |
| auto[1] |
732876 |
1 |
|
|
T1 |
4454 |
|
T13 |
16 |
|
T16 |
3261 |