Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899871 |
1 |
|
|
T25 |
1 |
|
T1 |
53543 |
|
T11 |
290 |
| auto[1] |
5730853 |
1 |
|
|
T1 |
42192 |
|
T13 |
290 |
|
T16 |
27983 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12899354 |
1 |
|
|
T25 |
1 |
|
T1 |
90780 |
|
T11 |
290 |
| auto[1] |
731370 |
1 |
|
|
T1 |
4955 |
|
T13 |
8 |
|
T16 |
3374 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884513 |
1 |
|
|
T25 |
1 |
|
T1 |
54164 |
|
T11 |
290 |
| auto[1] |
5746211 |
1 |
|
|
T1 |
41571 |
|
T13 |
334 |
|
T16 |
28793 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2506195 |
1 |
|
|
T1 |
16946 |
|
T13 |
139 |
|
T16 |
12594 |
| auto[1] |
auto[0] |
auto[1] |
365014 |
1 |
|
|
T1 |
2282 |
|
T13 |
4 |
|
T16 |
1587 |
| auto[1] |
auto[1] |
auto[0] |
2508646 |
1 |
|
|
T1 |
19670 |
|
T13 |
187 |
|
T16 |
12825 |
| auto[1] |
auto[1] |
auto[1] |
366356 |
1 |
|
|
T1 |
2673 |
|
T13 |
4 |
|
T16 |
1787 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |