Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891586 |
1 |
|
|
T25 |
1 |
|
T1 |
54727 |
|
T11 |
290 |
| auto[1] |
5739138 |
1 |
|
|
T1 |
41008 |
|
T13 |
298 |
|
T16 |
28208 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898084 |
1 |
|
|
T25 |
1 |
|
T1 |
91072 |
|
T11 |
290 |
| auto[1] |
732640 |
1 |
|
|
T1 |
4663 |
|
T13 |
6 |
|
T16 |
3418 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882614 |
1 |
|
|
T25 |
1 |
|
T1 |
54920 |
|
T11 |
290 |
| auto[1] |
5748110 |
1 |
|
|
T1 |
40815 |
|
T13 |
204 |
|
T16 |
29110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2516412 |
1 |
|
|
T1 |
18532 |
|
T13 |
85 |
|
T16 |
12645 |
| auto[1] |
auto[0] |
auto[1] |
367364 |
1 |
|
|
T1 |
2466 |
|
T13 |
3 |
|
T16 |
1708 |
| auto[1] |
auto[1] |
auto[0] |
2499058 |
1 |
|
|
T1 |
17620 |
|
T13 |
113 |
|
T16 |
13047 |
| auto[1] |
auto[1] |
auto[1] |
365276 |
1 |
|
|
T1 |
2197 |
|
T13 |
3 |
|
T16 |
1710 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |