Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7915218 |
1 |
|
|
T25 |
1 |
|
T1 |
53439 |
|
T11 |
290 |
| auto[1] |
5715506 |
1 |
|
|
T1 |
42296 |
|
T13 |
248 |
|
T16 |
27474 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12893633 |
1 |
|
|
T25 |
1 |
|
T1 |
90716 |
|
T11 |
290 |
| auto[1] |
737091 |
1 |
|
|
T1 |
5019 |
|
T13 |
5 |
|
T16 |
3260 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863727 |
1 |
|
|
T25 |
1 |
|
T1 |
53689 |
|
T11 |
290 |
| auto[1] |
5766997 |
1 |
|
|
T1 |
42046 |
|
T13 |
130 |
|
T16 |
28270 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518551 |
1 |
|
|
T1 |
18473 |
|
T13 |
59 |
|
T16 |
12863 |
| auto[1] |
auto[0] |
auto[1] |
368979 |
1 |
|
|
T1 |
2493 |
|
T13 |
2 |
|
T16 |
1737 |
| auto[1] |
auto[1] |
auto[0] |
2511355 |
1 |
|
|
T1 |
18554 |
|
T13 |
66 |
|
T16 |
12147 |
| auto[1] |
auto[1] |
auto[1] |
368112 |
1 |
|
|
T1 |
2526 |
|
T13 |
3 |
|
T16 |
1523 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |