Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7857781 |
1 |
|
|
T25 |
1 |
|
T1 |
54168 |
|
T11 |
290 |
| auto[1] |
5772943 |
1 |
|
|
T1 |
41567 |
|
T13 |
251 |
|
T16 |
27985 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12903711 |
1 |
|
|
T25 |
1 |
|
T1 |
90825 |
|
T11 |
290 |
| auto[1] |
727013 |
1 |
|
|
T1 |
4910 |
|
T13 |
11 |
|
T16 |
3249 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7921179 |
1 |
|
|
T25 |
1 |
|
T1 |
53419 |
|
T11 |
290 |
| auto[1] |
5709545 |
1 |
|
|
T1 |
42316 |
|
T13 |
286 |
|
T16 |
27816 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2489480 |
1 |
|
|
T1 |
20253 |
|
T13 |
140 |
|
T16 |
12473 |
| auto[1] |
auto[0] |
auto[1] |
363533 |
1 |
|
|
T1 |
2706 |
|
T13 |
4 |
|
T16 |
1690 |
| auto[1] |
auto[1] |
auto[0] |
2493052 |
1 |
|
|
T1 |
17153 |
|
T13 |
135 |
|
T16 |
12094 |
| auto[1] |
auto[1] |
auto[1] |
363480 |
1 |
|
|
T1 |
2204 |
|
T13 |
7 |
|
T16 |
1559 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |