Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889875 |
1 |
|
|
T25 |
1 |
|
T1 |
53883 |
|
T11 |
290 |
| auto[1] |
5740849 |
1 |
|
|
T1 |
41852 |
|
T13 |
241 |
|
T16 |
29436 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11256801 |
1 |
|
|
T25 |
1 |
|
T1 |
70491 |
|
T11 |
290 |
| auto[1] |
2373923 |
1 |
|
|
T1 |
25244 |
|
T13 |
287 |
|
T16 |
16503 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922298 |
1 |
|
|
T25 |
1 |
|
T1 |
55856 |
|
T11 |
290 |
| auto[1] |
5708426 |
1 |
|
|
T1 |
39879 |
|
T13 |
318 |
|
T16 |
26770 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1669933 |
1 |
|
|
T1 |
7388 |
|
T13 |
17 |
|
T16 |
5282 |
| auto[1] |
auto[0] |
auto[1] |
1191183 |
1 |
|
|
T1 |
12538 |
|
T13 |
169 |
|
T16 |
8040 |
| auto[1] |
auto[1] |
auto[0] |
1664570 |
1 |
|
|
T1 |
7247 |
|
T13 |
14 |
|
T16 |
4985 |
| auto[1] |
auto[1] |
auto[1] |
1182740 |
1 |
|
|
T1 |
12706 |
|
T13 |
118 |
|
T16 |
8463 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |