Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895044 |
1 |
|
|
T25 |
1 |
|
T1 |
54218 |
|
T11 |
290 |
| auto[1] |
5735680 |
1 |
|
|
T1 |
41517 |
|
T13 |
210 |
|
T16 |
26896 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11261132 |
1 |
|
|
T25 |
1 |
|
T1 |
69556 |
|
T11 |
290 |
| auto[1] |
2369592 |
1 |
|
|
T1 |
26179 |
|
T13 |
181 |
|
T16 |
16733 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7932133 |
1 |
|
|
T25 |
1 |
|
T1 |
54502 |
|
T11 |
290 |
| auto[1] |
5698591 |
1 |
|
|
T1 |
41233 |
|
T13 |
281 |
|
T16 |
27663 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1665828 |
1 |
|
|
T1 |
7422 |
|
T13 |
63 |
|
T16 |
5622 |
| auto[1] |
auto[0] |
auto[1] |
1186091 |
1 |
|
|
T1 |
12559 |
|
T13 |
136 |
|
T16 |
8453 |
| auto[1] |
auto[1] |
auto[0] |
1663171 |
1 |
|
|
T1 |
7632 |
|
T13 |
37 |
|
T16 |
5308 |
| auto[1] |
auto[1] |
auto[1] |
1183501 |
1 |
|
|
T1 |
13620 |
|
T13 |
45 |
|
T16 |
8280 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |