Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892522 |
1 |
|
|
T25 |
1 |
|
T1 |
57257 |
|
T11 |
290 |
| auto[1] |
5738202 |
1 |
|
|
T1 |
38478 |
|
T13 |
363 |
|
T16 |
27998 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2507206 |
1 |
|
|
T1 |
16382 |
|
T13 |
142 |
|
T16 |
13149 |
| auto[1] |
auto[0] |
auto[1] |
366597 |
1 |
|
|
T1 |
2105 |
|
T13 |
9 |
|
T16 |
1782 |
| auto[1] |
auto[1] |
auto[0] |
2498120 |
1 |
|
|
T1 |
17642 |
|
T13 |
205 |
|
T16 |
11588 |
| auto[1] |
auto[1] |
auto[1] |
366279 |
1 |
|
|
T1 |
2349 |
|
T13 |
7 |
|
T16 |
1479 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |