Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869917 |
1 |
|
|
T25 |
1 |
|
T1 |
55544 |
|
T11 |
290 |
| auto[1] |
5760807 |
1 |
|
|
T1 |
40191 |
|
T13 |
221 |
|
T16 |
28070 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11241920 |
1 |
|
|
T25 |
1 |
|
T1 |
68253 |
|
T11 |
290 |
| auto[1] |
2388804 |
1 |
|
|
T1 |
27482 |
|
T13 |
352 |
|
T16 |
17250 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906243 |
1 |
|
|
T25 |
1 |
|
T1 |
52601 |
|
T11 |
290 |
| auto[1] |
5724481 |
1 |
|
|
T1 |
43134 |
|
T13 |
397 |
|
T16 |
27443 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1659938 |
1 |
|
|
T1 |
8029 |
|
T13 |
23 |
|
T16 |
5264 |
| auto[1] |
auto[0] |
auto[1] |
1190947 |
1 |
|
|
T1 |
13812 |
|
T13 |
256 |
|
T16 |
8369 |
| auto[1] |
auto[1] |
auto[0] |
1675739 |
1 |
|
|
T1 |
7623 |
|
T13 |
22 |
|
T16 |
4929 |
| auto[1] |
auto[1] |
auto[1] |
1197857 |
1 |
|
|
T1 |
13670 |
|
T13 |
96 |
|
T16 |
8881 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |