Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880038 |
1 |
|
|
T25 |
1 |
|
T1 |
56810 |
|
T11 |
290 |
| auto[1] |
5750686 |
1 |
|
|
T1 |
38925 |
|
T13 |
184 |
|
T16 |
28119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11237452 |
1 |
|
|
T25 |
1 |
|
T1 |
69977 |
|
T11 |
290 |
| auto[1] |
2393272 |
1 |
|
|
T1 |
25758 |
|
T13 |
159 |
|
T16 |
17588 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874410 |
1 |
|
|
T25 |
1 |
|
T1 |
55248 |
|
T11 |
290 |
| auto[1] |
5756314 |
1 |
|
|
T1 |
40487 |
|
T13 |
273 |
|
T16 |
28371 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1682662 |
1 |
|
|
T1 |
7812 |
|
T13 |
83 |
|
T16 |
5220 |
| auto[1] |
auto[0] |
auto[1] |
1197417 |
1 |
|
|
T1 |
14136 |
|
T13 |
122 |
|
T16 |
8698 |
| auto[1] |
auto[1] |
auto[0] |
1680380 |
1 |
|
|
T1 |
6917 |
|
T13 |
31 |
|
T16 |
5563 |
| auto[1] |
auto[1] |
auto[1] |
1195855 |
1 |
|
|
T1 |
11622 |
|
T13 |
37 |
|
T16 |
8890 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |