Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876170 |
1 |
|
|
T25 |
1 |
|
T1 |
54656 |
|
T11 |
290 |
| auto[1] |
5754554 |
1 |
|
|
T1 |
41079 |
|
T13 |
260 |
|
T16 |
29983 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11237769 |
1 |
|
|
T25 |
1 |
|
T1 |
67788 |
|
T11 |
290 |
| auto[1] |
2392955 |
1 |
|
|
T1 |
27947 |
|
T13 |
138 |
|
T16 |
17122 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883820 |
1 |
|
|
T25 |
1 |
|
T1 |
52395 |
|
T11 |
290 |
| auto[1] |
5746904 |
1 |
|
|
T1 |
43340 |
|
T13 |
196 |
|
T16 |
28003 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1686043 |
1 |
|
|
T1 |
7576 |
|
T13 |
38 |
|
T16 |
5133 |
| auto[1] |
auto[0] |
auto[1] |
1199579 |
1 |
|
|
T1 |
14143 |
|
T13 |
76 |
|
T16 |
8323 |
| auto[1] |
auto[1] |
auto[0] |
1667906 |
1 |
|
|
T1 |
7817 |
|
T13 |
20 |
|
T16 |
5748 |
| auto[1] |
auto[1] |
auto[1] |
1193376 |
1 |
|
|
T1 |
13804 |
|
T13 |
62 |
|
T16 |
8799 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |